Abstract: A method for forming a trench with a buried plate includes the steps of forming a trench in a substrate, depositing a non-doped silicate oxide in the trench and placing a doped silicate glass filling thereon. A buried trench plate is formed around the lower region of the trench in the substrate.

Abstract: A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper section of the insulation collar is greater than a layer thickness in a lower section of the insulation collar. This results in a trench capacitor having improved leakage current properties. A simplified and cost-effective method of fabricating a trench capacitor is also provided.

Abstract: A method of forming a bottom electrode of a capacitor in a memory device. A plurality of deep trenches is formed, in which the number of first deep trenches within an active area is higher than that of the second deep trenches within a peripheral area. After a doped oxide layer is formed, a photoresist layer is formed on the doped oxide layer to fill the deep trenches. Then, exposure is employed on the photoresist layer with a predetermined incident angle of light source, wherein the photoresist layer outside the level of the deep trenches is exposed, and the photoresist layer inside the deep trenches is not. Thus, the photoresist layer exposed and outside the level of the deep trenches is removed, and the photoresist layer that is not exposed and inside the deep trenches is retained. Next, a part of the photoresist layer inside the deep trenches is removed, as is the doped oxide layer outside the level of the photoresist layer.

Abstract: A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

Abstract: Oxynitridation processing for heat treating a substrate in an atmosphere containing NO (nitrogen monoxide) and ion implantation of nitrogen are used in combination to control the concentration of nitrogen introduced near the boundary between a gate oxide film and a substrate (well), in the order of higher concentration given as: n-channel MISFET having a thick gate oxide film>n-channel MISFET having a thin gate oxide film>p-channel MISFET having the thick gate oxide film, p-channel MISFET having the thin gate oxide film, with no additional use of photomasks, whereby reliability to hot carriers and reliability to NBT can be compatibilized by optimizing the concentration of nitrogen introduced to the boundary between the gate oxide films of four types of MISFET of different conduction type and different gate oxide film thickness and the substrate (well).

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: In a vertical-transistor based semiconductor structure, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a sacrificial insulator layer, forming a vertical hardmask on the inner trench walls above the sacrificial insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the vertical transistor.

Abstract: A method of forming a bottom electrode of a capacitor in a memory device. A plurality of deep trenches is formed, in which the number of first deep trenches within an active area is higher than that of the second deep trenches within a peripheral area. After a doped oxide layer is formed, a photoresist layer is formed on the doped oxide layer to fill the deep trenches. Then, exposure is employed on the photoresist layer with a predetermined incident angle of light source, wherein the photoresist layer outside the level of the deep trenches is exposed, and the photoresist layer inside the deep trenches is not. Thus, the photoresist layer exposed and outside the level of the deep trenches is removed, and the photoresist layer that is not exposed and inside the deep trenches is retained. Next, a part of the photoresist layer inside the deep trenches is removed, as is the doped oxide layer outside the level of the photoresist layer.

Abstract: The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.

Abstract: Improvements are realized in the coverage characteristics of a cell plate electrode with respect to a cylindrical storage node electrode which has a high aspect ratio (height/diameter) and a surface having minute irregularities formed thereon, thereby improving the electrical characteristics and reliability of a semiconductor device. The semiconductor device is manufactured through a step of forming a first cell plate electrode film on a cylindrical storage node electrode, a process of implanting conductive impurities into the first cell plate electrode film, and a process of forming a second cell plate electrode film on the first cell plate electrode film.

Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench.

Abstract: A method of fabricating a trench capacitor of a memory cell. A pad layer is formed on the substrate, and a deep trench is then formed. A residual first insulating layer is conformably formed on the sidewall and bottom of the trench, wherein the upper surface of the residual first insulating layer is lower than that of the substrate. A residual non-doped layer is conformably formed on the first insulating layer, wherein the upper surface of the residual non-doped layer is between the upper surfaces the residual first insulating layer and the substrate. A residual doped insulating layer is conformably formed on the residual non-doped layer, wherein the upper surface of the residual doped insulating layer is substantially level with that of the residual non-doped layer. A second insulating layer is conformably formed on the pad layer and the inner surface of the trench.

Abstract: The present invention discloses structure and manufacturing method of binary nitride-oxide (NO) dielectric node for deep trench based DRAM devices. In the present invention, a thin strained SiGe layer is deposited prior to poly deposition to modulate the chemical potential unbalance caused by work-function (WF) differences between buried plate and poly. The thin strained SiGe layer will lower the differences by its lower band-gap characteristics at the same doping level, thereby balancing the chemical potential despite of a different doping. The modulation of the chemical potential can be achieved by a proper control of a stochimetric x value. The optimized chemical potential will assure the reliability and robustness of the dielectric node, especially the binary NO dielectric node by suppressing asymmetric charging trapping and charge injection nature.

Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.

Abstract: A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a wet-chemical etching is additionally performed. An n+-doped substrate results from the driving-out of the arsenic glass being widened in the trench, by about 20 nm, selectively both with respect to the lightly doped substrate and with respect to the oxide layer and with respect to the nitride layer.

Abstract: A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Abstract: A method for manufacturing a trench capacitor uses a low-pressure gas phase doping for forming a buried plate as a capacitor plate. The use of the low-pressure gas phase doping reduces process costs and improves capacitor properties.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

Abstract: A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a buried insulating collar due to the widened trench. The insulating collar is removed in the vicinity of the surface of the substrate, through which the substrate is exposed in this region. Here, a selective epitaxial layer is subsequently grown in the trench, through which a subsequently formed selection transistor can be formed in perpendicular fashion over the trench, or very close to the trench. In addition, through the widened trench the electrode surface of the capacitor electrodes is enlarged, which ensures an increased storage capacity.

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract: In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a second impurity region formed in the substrate on a second side of the gate structure, the second impurity region including: a third impurity region of the first conductive type, a fourth impurity region of the first conductive type between the third impurity region and the second side of the gate structure, and a halo ion region of a second conductive type formed adjacent to the fourth impurity region.

Abstract: A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG-Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

Abstract: A method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.

Abstract: An improved method for reducing the cost of fabricating bottle-shaped deep trench capacitors.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of a trench. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Then, a CMP process is used to remove the ion-implanted-sensitive resist and the doped dielectric layer. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface, and the barrier layer prevent the dopants from diffusing into the upper horizontal surface.

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si3N4) uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract: A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Abstract: A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

Abstract: Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer. In another embodiment, a capacitor storage node layer is formed within a container which is received within an insulative material. A capacitor storage node layer is formed within the container and has an outer surface. A layer of material is formed within less than the entire capacitor container and covers less than the entire capacitor storage node layer outer surface. The layer of material comprises a material which is different from the insulative material within which the capacitor container is formed.

Abstract: An improved method for forming a buried plate in a bottle-shaped deep trench capacitor. The method includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-dope conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; and (h) removing the entire arsenic-ion-doped layer.

Abstract: A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer.

Abstract: A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: There is disclosed a method of forming a buried strap (BS) and its quantum conducting barrier (QCB) in a structure wherein a doped polycrystalline silicon region is exposed at the bottom of a recess and separated from a monocrystalline region of a silicon substrate by a region of an insulating material. First, a thin continuous layer of undoped amorphous silicon is deposited by LPCVD to coat said regions. The surface of this layer is nitridized to produce a Si3N4 QCB film. Now, at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer is deposited onto the structure by LPCVD. The recess is filled with undoped amorphous silicon to terminate the buried strap and its QCB. Finally, the structure is heated to activate the dopants in the buried strap to allow an electrical continuity between said polycrystalline and monocrystalline regions through the QCB by a quantum mechanical effect. All these steps are performed in situ in the same LPCVD tool.

Abstract: A semiconductor memory device includes a semiconductor substrate having convex and concave portions locally formed in a surface thereof. An anti-reflection film serves as a first mask member and is formed on the semiconductor substrate. A photoresist is formed on the anti-reflection film. The anti-reflection film is partially removed using an opening formed by patterning the photoresist so as to expose an upper surface of the convex portion. The convex portion is etched using the photoresist and the anti-reflection film left in the concave portion. The anti-reflection film and the photoresist are removed, thereby obtaining the semiconductor substrate worked in a self-alignment manner.

Abstract: A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

Abstract: Known methods for forming trench storage capacitors require the chemical vapour deposition (CVD) of an undoped silicon oxide layer in order to prevent auto doping of side wall of a semiconductor trench. This layer is deposited once an arsenic doped silicon oxide layer has been disposed and etched to an appropriate depth. Such a technique results in a complex and expensive process. It is therefore proposed to deposit (step 906) the undoped silicon oxide layer 108 in-situ immediately after the arsenic doped silicon oxide layer 106 has been deposited (step 904) and before etching takes place (step 910). It is thus possible to remove the CVD of the undoped silicon oxide, thereby simplifying the overall process and yielding a device having improved performance characteristics.

Abstract: Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.

Abstract: An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O2/CF4 chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.

Abstract: A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate.

Abstract: Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.

Abstract: The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

Abstract: High-capacity capacitors and gate insulators exhibiting moderately high dielectric constants with surprisingly low leakage using amorphous or low temperature films of perovskite type oxides including a titanate system material such as barium titanate, strontium titanate, barium strontium titanate (BST), lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate, barium lanthanum titanate, a niobate, aluminate or tantalate system material such as lead magnesium niobate, lithium niobate lithium tantalate, potassium niobate and potassium tantalum niobate, a tungsten-bronze system material such as barium strontium niobate, lead barium niobate, barium titanium niobate, and Bi-layered perovskite system material such as strontium bismuth tantalate, bismuth titanate deposited directly on a silicon surface at temperatures about 450° C. or less.

Abstract: The present invention provides a method for making the bottom electrode of a buried capacitor, which is characterized by protecting the non-bottom electrode region with a LPD oxide layer to prevent the impurities within the doped Si glass remaining in non-bottom electrode region from driving into the substrate during annealing, thus non-desired diffusing region connecting to the bottom electrode will be generated. Consequently, the leakage current existing in conventional buried capacitor will be effectively reduced according to the method of this present invention.

Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more.

Abstract: A trench storage dynamic random access memory cell with vertical transfer device can be formed in a wafer having prepared shallow trench isolation. Vertical transfer device is built as the deep trenches are formed. Using square printing to form shallow trench isolation and deep trenches, allows for scaling of the cell to very small dimensions.

Abstract: A method of fabricating a trench cell capacitor can be used in the formation of a DRAM cell. In one embodiment, a trench is formed within a semiconductor substrate. The trench is lined with a dielectric layer, e.g., an ONO layer. After lining the trench, a collar is formed in an upper portion of the trench by forming an oxide layer in the upper portion. A nitride layer on the oxide layer. The trench is then filled with semiconductor material. For example, a semiconductor region can be epitaxially grown to fill the trench.