Including Doping Of Trench Surfaces Patents (Class 438/389)
  • Patent number: 10079151
    Abstract: Embodiments of the invention provide a processing method for bottom-up deposition of a film in a recessed feature. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having a bottom and a sidewall, b) depositing a film on the bottom and on the sidewall of the recessed feature, and c) covering the film at the bottom of the recessed feature with a mask layer. The method further includes d) etching the film from the sidewall, and e) removing the mask layer to expose the film at the bottom of the recessed feature. Steps b)-e) may be repeated at least once until the film at the bottom of the recessed feature has a desired thickness. In one example, the recessed feature may be filled with the film.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 18, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N Tapily, David L O'Meara, Kaushik A Kumar
  • Patent number: 9219068
    Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
  • Patent number: 9111853
    Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Shyam Surthi
  • Patent number: 9012296
    Abstract: A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wu-An Weng, Chen-Chien Chang
  • Patent number: 8946045
    Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Patent number: 8936992
    Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8835250
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Publication number: 20140070292
    Abstract: A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8647945
    Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Geng Wang, Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi
  • Patent number: 8642423
    Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Publication number: 20130309835
    Abstract: A method for forming a semiconductor device includes forming a deep trench in a substrate having a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth. A region around the deep trench is doped to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion. A deep trench capacitor is formed in the deep trench using the buried plate as one electrode of the capacitor. An access transistor is formed to charge or discharge the deep trench capacitor. A well is formed in the first doped portion.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 21, 2013
    Inventors: Veeraraghavan S. Basker, Wilfried E. Haensch, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20130277798
    Abstract: A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 24, 2013
    Applicant: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Philip R. Germann, John E. Sheets, II
  • Patent number: 8563446
    Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
  • Publication number: 20130249052
    Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jennifer E. Appleyard, John E. Barth, JR., John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 8519484
    Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won Kim, Jae-Hwang Sim, Keon-Soo Kim, Young-Ho Lee
  • Patent number: 8513704
    Abstract: A photodiode capable of interacting with incident photons includes at least: a stack of three layers including an intermediate layer placed between a first semiconductor layer and a second semiconductor layer having a first conductivity type; and a region that is in contact with at least the intermediate layer and the second layer and extends transversely relative to the planes of the three layers, the region having a conductivity type that is opposite to the first conductivity type. The intermediate layer is made of a semiconductor material having a second conductivity type and is capable of having a conductivity type that is opposite to the second conductivity type so as to form a P-N junction with the region, inversion of the conductivity type of the intermediate layer being induced by dopants of the first conductivity type that are present in the first and second layers.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 20, 2013
    Assignee: Commissariat a l'Energie Automique et aux Energies Alternatives
    Inventor: Johan Rothman
  • Publication number: 20130134491
    Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Publication number: 20130099354
    Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chengwen Pei, Roger Allen Booth, JR., Herbert Lei Ho, Naoyoshi Kusaba
  • Publication number: 20130062677
    Abstract: A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhengwen Li, Damon B. Farmer, Michael P. Chudzik, Keith Kwong Hon Wong, Jian Yu, Zhen Zhang, Chengwen Pei
  • Patent number: 8372710
    Abstract: A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Publication number: 20130032868
    Abstract: A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chengwen Pei, Xi Li, Geng Wang
  • Patent number: 8350323
    Abstract: A semiconductor device may include, but is not limited to: a semiconductor substrate; a bit line; and a contact portion. The semiconductor substrate has a first groove having at least first and second side surfaces facing each other. The bit line is positioned in the first groove. The bit line is insulated from the semiconductor substrate. The contact portion is positioned in the first groove. The contact portion is electrically connected to the bit line. The contact portion contacts the first side surface of the first groove. The contact portion is insulated from the second side surface of the first groove.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: January 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Noriaki Mikasa
  • Publication number: 20120302032
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8299573
    Abstract: A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Xi Li, Geng Wang
  • Patent number: 8247303
    Abstract: Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 21, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Ayako Inoue, Naoto Saitoh
  • Publication number: 20120199945
    Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph E. Ervin, Yanli Zhang
  • Patent number: 8236648
    Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: August 7, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Masayuki Hashitani
  • Patent number: 8236710
    Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
  • Patent number: 8232162
    Abstract: A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang, Yanli Zhang
  • Patent number: 8226836
    Abstract: Described herein are systems, devices, and methods relating to packaging electronic devices, for example, microelectromechanical systems (MEMS) devices, including optical modulators such as interferometric optical modulators. The interferometric modulator disclosed herein comprises a movable mirror. Some embodiments of the disclosed movable mirror exhibit a combination of improved properties compared to known mirrors, including reduced moving mass, improved mechanical properties, and reduced etch times.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: July 24, 2012
    Assignee: Qualcomm MEMS Technologies, Inc.
    Inventors: Clarence Chui, Jeffrey B. Sampsell
  • Patent number: 8227847
    Abstract: The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940). Via connections (920) are provided in trenches that go through the whole thickness of the wafer.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: July 24, 2012
    Assignee: NXP B.V.
    Inventors: Francois Neuilly, Francois Le Cornec
  • Patent number: 8211769
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions that are separated from each other by a plurality of trenches, respectively, wherein the trenches are formed by etching a substrate, forming an insulation layer having openings that each expose a portion of a first sidewall of each active region, forming a filling layer which fills the openings, forming a diffusion control layer over a substrate structure including the filling layer, and forming a junction on a portion of the first sidewall of each active region.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Bo-Mi Lee
  • Patent number: 8198169
    Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
  • Publication number: 20120139080
    Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Geng Wang, Roger A. Booth, JR., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi
  • Patent number: 8168494
    Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: May 1, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Jun Osanai
  • Publication number: 20120086103
    Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: ASHIMA B. CHAKRAVARTI, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
  • Publication number: 20120086064
    Abstract: A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Byeong Y. Kim, Munir D. Naeem, James P. Norum
  • Patent number: 8143659
    Abstract: A capacitor is described which includes a substrate with a doped area of the substrate forming a first electrode of the capacitor. A plurality of trenches is arranged in the doped area of the substrate, the plurality of trenches forming a second electrode of the capacitor. An electrically insulating layer is arranged between each of the plurality of trenches and the doped area for electrically insulating the trenches from the doped area. The doped area includes first open areas and at least one second open area arranged between neighboring trenches of the plurality of trenches, wherein the at least one open area is arranged below the at least one substrate contact. A shortest first distance between neighboring trenches is separated by the first open areas and is shorter than a shortest second distance between neighboring trenches separated by the at least one second open area.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: March 27, 2012
    Assignee: Infineon Technologies AG
    Inventor: Stefan Pompl
  • Patent number: 8129238
    Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won Kim, Jae-Hwang Sim, Keon-Soo Kim, Young-Ho Lee
  • Patent number: 8008160
    Abstract: A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xi Li, Richard Wise
  • Patent number: 7932147
    Abstract: A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: April 26, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jin-Ha Park
  • Patent number: 7923815
    Abstract: By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm?3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Geng Wang, Kangguo Cheng, Johnathan E. Faltermeier, Paul C. Parries
  • Patent number: 7919385
    Abstract: A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: April 5, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Yoshitaka Nakamura
  • Patent number: 7910486
    Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: March 22, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 7883984
    Abstract: A method of manufacturing a flash memory device may include forming a trench, defining at least a common source region, on a semiconductor substrate, forming a gate poly over the semiconductor substrate, performing an ion implantation process employing a first photoresist pattern and the gate poly as a mask, wherein the ion implantation process forms a source/drain junction on the semiconductor substrate, forming a recess common source region in the trench by using a second photoresist pattern, and performing an ion implantation process on the recess common source region.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: February 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ji-Hwan Park
  • Patent number: 7863130
    Abstract: System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment includes manufacturing an integrated circuit, including forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al2O3.2SiO2), and alumina (Al2O3).
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Infineon Technologies AG
    Inventors: Matthias Hierlemann, Chandrasekhar Sarma
  • Publication number: 20100213571
    Abstract: A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Applicant: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Keith Kwong Hon Wong, Mahender Kumar
  • Patent number: 7763520
    Abstract: A capacitor device includes a substrate, a first conductive structure, a second conductive structure, a dielectric layer structure, and a recess in the substrate. The first and second conductive structures are disposed on opposite sides of the dielectric layer structure, and the dielectric layer structure extends in a meander-shaped manner in a cross-section through the recess.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 27, 2010
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Raimund Foerg, Klaus Koller, Kai-Olaf Subke
  • Patent number: 7749856
    Abstract: A method of fabricating a storage node with a supported structure is provided. A dielectric stacked comprising an etch stop layer, a first dielectric layer, a support layer and a second dielectric layer is formed on a substrate. An opening is etched into the dielectric stacked. A conductive layer is formed on the second dielectric layer and inside the opening. The conductive layer directly above the second dielectric layer is removed to form columnar node structure. The second dielectric layer is then removed. A spacer layer is deposited on the support layer and the columnar node structure. A tilt-angle implant is performed to implant dopants into the spacer layer. The undoped spacer layer is removed to form a hard mask. The support layer not covered by the hard mask is etched away to expose the first dielectric layer. The first dielectric layer and the hard mask are removed.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 6, 2010
    Assignee: Nanya Technology Corp.
    Inventors: Shih-Fan Kuan, Le-Tien Jung
  • Patent number: 7709341
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee