Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract: The present invention provides a method of forming a capacitor in an integrated circuit. The method comprises providing a semiconductor substrate having a conductive layer thereon. The partial conductive layer is removed to form an electrode. A plurality of first dopants are implanted on a surface of the electrode to form a first doped region. Then a plurality of second dopants are implanted into the electrode to form a second doped region below the first doped region. Then the capacitor is formed comprising the electrode. The first doped region and the second region can reduce voltage coefficient as well as increase capacitance of the capacitor.

Abstract: A semiconductor device has a first capacitor component and a second capacitor component on a silicon substrate. In the semiconductor device, the first capacitor component has a first lower electrode composed of an impurity-doped polycrystal silicon film, a first insulation film formed on the first lower electrode, and a first upper electrode formed on the first insulation film. The second capacitor component has a second lower electrode formed from an impurity-doped polycrystal silicon film having an impurity concentration different from an impurity concentration of the polycrystal silicon film of the first lower electrode, a second insulation film formed on the second lower electrode and a second upper electrode formed on a second insulation film.

Abstract: A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings.

Abstract: A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions.

Abstract: A manufacturing method of a semiconductor device having a CMOS logic circuit portion and a DRAM portion mixedly mounted on one chip. Preferably, the DRAM portion has a cylinder structure capacitor element. In the manufacturing method, the polysilicon film is formed on an interlayer film and on an inner wall of a cylinder-shaped opening formed in the interlayer film. Spherical or hemispherical grains called HSG are formed on the polysilicon film. The polysilicon film and the HSG on an upper surface of the interlayer film are removed while the polysilicon film and the HSG on the inner wall of the cylinder is retained. By performing these steps in this order, the HSG is reliably formed on the inner wall of the cylinder without fail. Therefore, a miniaturized capacitor element having high capacitance may be formed in a semiconductor device with a CMOS logic circuit portion and a DRAM portion mixedly mounted on one chip.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

Abstract: A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.

Abstract: Self-aligning photolithography method and a method of fabricating a semiconductor device using the same, in which the photolithography method is performed using a lower pattern without employing a separate mask. The self-aligning photolithography method includes the steps of forming a lower pattern layer on a semiconductor substrate, depositing a photoresist, and subjecting to exposure without a photomask such that the photoresist aligned with the lower pattern layer is not to be exposed by diffraction of light, and either removing or leaving only the photoresist aligned with the lower pattern layer by development.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: A method for ion implantation of high dielectric constant materials with dopants to improve sidewall stoichiometry is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with Ti dopants. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. Additionally, the invention relates to forming a capping layer over a horizontal portion of the BST film to reduce excess dopant from being implanted into the horizontal section of the BST film. The invention also relates to integrated circuits having a thin film high dielectric material with improved sidewall stoichiometry used as an insulating layer in a capacitor structure.

Abstract: A method for forming a lower electrode structure of a capacitor of a semiconductor device, includes the steps of: forming an active region in a semiconductor substrate; forming an insulation layer atop the semiconductor substrate having the active region formed therein; forming a contact hole in the insulation layer, the contact hole exposing the active region; forming a conductive plug connected to the active region through the contact hole, the conductive plug having an upper contact surface; forming a silicide contact on the upper contact surface of the conductive plug; forming a lower electrode layer in electrical contact with the silicide contact, by depositing titanium aluminum nitride on the insulation layer; and patterning the lower electrode layer to form a lower electrode having an upper surface. A natural oxide film is prevented from generating between the interface of the plug and the lower electrode.

Abstract: In a semicondutor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.

Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.

Abstract: There is disclosed a method of manufacturing a capacitor of a semiconductor device by which a CVD TiN film and a MOCVD TiN film, and a polysilicon film are sequentially stacked in forming an electrode on a Ta2O5 dielectric thin film. Therefore, it can prevent changes in thickness of the effective oxide film of the Ta2O5 capacitor against the characteristics of each of the CVD TiN film and the MOCVD TiN film, even after a rapid thermal process. It can also improve the step coverage, thus greatly improving the stability and reliability of the capacitor.

Abstract: A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

Abstract: A method is provided for making capacitors for future high density circuits. The method increases capacitance while reducing the difficulty in etching the high aspect ratio holes for the capacitor node contacts. After FETs are formed in device areas, a first insulator is deposited and first contact openings are etched for the capacitor node contact. First polysilicon (polySi) plugs are formed in the first contact openings. An etch-stop layer and a second insulating layer are deposited. Second contact openings are aligned over and etched in the second insulating layer to the first polySi plugs. Second polySi plugs are formed in the second contact openings. Openings for capacitors, aligned over and wider than the second polySi plug, are etched in the second insulating layer. The capacitors are completed by forming bottom electrodes with a thin dielectric layer in the capacitor openings and forming a top electrode.

Abstract: A method for manufacturing a semiconductor device, comprises steps of: (a) forming a gate insulating film on a semiconductor substrate and forming a plurality of gate electrodes having a first insulating film made of a first insulating material thereon and a sidewall spacer made of the first insulating material on its sidewall on said gate insulating film; (b) forming a second insulating film which is made of the first insulating material and which is thinner than said first insulating film on said semiconductor substrate at least in a region where a contact hole is to be formed in the later step; (c) embedding a third insulating film which may become an etching stopper to etching of said first insulating material between said gate electrodes; (d) forming a first resist pattern having a predetermined shape on said semiconductor substrate and etching said second insulating film, first insulating film and sidewall spacer until when said gate electrode is exposed by using said first resist pattern and said third

Abstract: A method of fabricating of a capacitor with low voltage coefficient of capacitance is described. A silicon substrate with field oxide isolations is provided. A buried layer is formed by doping N-type impurities into the substrate as the bottom plate of the capacitor. A dielectric layer is formed by thermal oxidation for the capacitor, and then a polysilicon layer is formed by the low pressure chemical vapor deposition method. A thermal diffusion step is performed to dope phosphorus into the polysilicon layer. After formation of a polysilicide layer by the low pressure chemical vapor deposition method, arsenic ions are implanted into the polysilicon layer and the polysilicide layer. Finally the polysilicide layer and the polysilicon layer are partially etched in consequence, and the top plate of the capacitor is formed.

Abstract: A method of fabricating a capacitor of a semiconductor device is disclosed including the step of forming a lower electrode layer on a semiconductor substrate, and a dielectric on the lower electrode layer, a part of the lower electrode layer, a part of the upper electrode layer adjacent to the dielectric of the capacitor including the upper electrode on the dielectric, or all of them containing oxygen.

Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.

Abstract: To reduce a junction leakage of an junction interface between a P type well portion formed on a P type substrate and a source region, an impurity region of a first conductive type or a second conductivity type is formed at the junction interface. A plug ion is implanted in the source region to increase a depletion depth of the source region and a counter doping is then performed in the source region to reduce an electrical field of the source region.

Abstract: Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type.

Abstract: High density, multi-metal layer semiconductor devices are formed with self-aligned vias and reliable interconnection patterns employing photolithography without the use of a photomask. Embodiments include modulating the amount of energy reflected into an overlying photoresist layer from underlying components to effect differential exposure of the photoresist layer.

Abstract: A high-precision, linear MOS-transistor-gate capacitor device is provided by applying a source/drain high-energy, high-dose ion implantation through implant windows in a polysilicon top plate of the capacitor. The ion implantation may be a step of generic MOS source/drain process flow.

Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.

Abstract: A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.