Having Magnetic Or Ferroelectric Component Patents (Class 438/3)
  • MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150069543
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element includes forming a first ferromagnetic layer on a base substrate, forming a tunnel barrier layer on the first ferromagnetic layer, forming a second ferromagnetic layer containing B on the tunnel barrier layer, and performing annealing in a gas-phase atmosphere including a gas, after formation of the second ferromagnetic layer, the gas producing a reaction product with B, the reaction product having a melting point lower than a treatment temperature.
    Type: Application
    Filed: January 16, 2014
    Publication date: March 12, 2015
    Inventors: Makoto NAGAMINE, Youngmin EEH, Koji UEDA, Daisuke WATANABE, Kazuya SAWADA, Toshihiko NAGASE
  • MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150069557
    Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Inventors: Masahiko NAKAYAMA, Masatoshi YOSHIKAWA, Tadashi KAI, Yutaka HASHIMOTO, Masaru TOKO, Hiroaki YODA, Jae Geun OH, Keum Bum LEE, Choon Kun RYU, Hyung Suk LEE, Sook Joo KIM
  • METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT
    Publication number: 20150072440
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the non-magnetic layer, and patterning the second magnetic layer by a RIE using an etching gas including a noble gas and a hydrocarbon gas.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Inventors: Satoshi INADA, Kazuhiro TOMIOKA, Satoshi SETO, Masatoshi YOSHIKAWA
  • MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150069558
    Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Inventors: Masahiko NAKAYAMA, Tadashi KAI, Masaru TOKO, Hiroaki YODA, Hyung Suk LEE, Jae Geun OH, Choon Kun RYU, Min Suk LEE
  • MAGNETO-RESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150069542
    Abstract: According to one embodiment, a method of manufacturing a magneto-resistive element, includes forming a first ferromagnetic layer on a substrate, forming a tunnel barrier layer on the first ferromagnetic layer, forming a second ferromagnetic layer containing B on the tunnel barrier layer, exposing a laminate of the first ferromagnetic layer, the tunnel barrier layer, and the second ferromagnetic layer under a pressurized atmosphere, and annealing the laminate while being exposed to the pressurized atmosphere, thereby promoting the orientation of the second magnetic layer.
    Type: Application
    Filed: January 16, 2014
    Publication date: March 12, 2015
    Inventors: Makoto NAGAMINE, Youngmin EEH, Koji UEDA, Daisuke WATANABE, Kazuya SAWADA, Toshihiko NAGASE
  • SPIN INJECTOR DEVICE COMPRISING A PROTECTION LAYER AT THE CENTRE THEREOF
    Publication number: 20150072442
    Abstract: A method for manufacturing a spin injector device, comprising the following steps of: a) forming a metal protection layer on a face of a substrate, so as to restrict or prevent oxidation and/or contamination of said face by its environment, the face being magnetic and electrically conductive, the protection layer being of a diamagnetic or paramagnetic nature; b) forming an upper layer onto the protection layer, able to promote a spin bias of electronics sates in the vicinity of the Fermi level of the interface between the protection layer and the upper layer according to an amplitude and a spin referential frame which are defined by the magnetism of the substrate and/or of the face of the substrate, the upper layer being an organic layer of which one or more molecular sites have, in contact with the protection layer, a paramagnetic moment.
    Type: Application
    Filed: April 15, 2013
    Publication date: March 12, 2015
    Applicants: UNIVERSITE DE STRASBOURG, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Martin Bowen, Mébarek Alouani, Samy Boukari, Eric Beaurepaire, Wolfgang Weber, Fabrice Scheurer, Loïc Joly
  • STRAIN SENSOR AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20150069540
    Abstract: According to one embodiment, a strain sensor includes a substrate, a lid, a frame, and a sensing unit. The substrate has a first surface. The lid is provided on the first surface. The frame is provided between the substrate and the lid. The frame is nonconductive and includes a magnetic body. The sensing unit is provided inside the frame between the substrate and the lid, and includes a magnetoresistance effect element.
    Type: Application
    Filed: March 11, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusaku ASANO, Kazuhito HIGUCHI, Takeshi MIYAGI, Yoshihiro HIGASHI, Michiko HARA, Hideaki FUKUZAWA, Masayuki KII, Eizo FUJISAWA
  • MAGNETIC MEMORY AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20150069553
    Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a magnetoresistive element provided on the substrate. The magnetoresistive element includes a first magnetic layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer or the second magnetic layer includes a first region, second region, and third region whose ratios of crystalline portion are higher in order closer to the tunneling barrier.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Inventors: Toshihiko NAGASE, Daisuke WATANABE, Kazuya SAWADA, Koji UEDA, Youngmin EEH, Hiroaki YODA
  • METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT
    Publication number: 20150072439
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Inventors: Kazuhiro TOMIOKA, Satoshi SETO, Masatoshi YOSHIKAWA, Satoshi INADA
  • Method for manufacturing a MEMS sensor
    Patent number: 8975090
    Abstract: A capacitance type gyro sensor includes a semiconductor substrate, a first electrode integrally including a first base portion and first comb tooth portions and a second electrode integrally including a second base portion and second comb tooth portions, formed by processing the surface portion of the semiconductor substrate. The first electrode has first drive portions that extend from opposed portions opposed to the respective second comb tooth portions on the first base portion toward the respective second comb tooth portions. The second electrode has second drive portions formed on the tip end portions of the respective second comb tooth portions opposed to the respective first drive portions. The first drive portions and the second drive portions engage with each other at an interval like comb teeth.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Goro Nakatani, Toma Fujita
  • Method for forming MTJ memory element
    Patent number: 8975089
    Abstract: The present invention is directed to a method for forming a magnetic tunnel junction (MTJ) memory element comprising the steps of providing a substrate having a bottom electrode layer thereon; depositing an MTJ layer stack on top of the bottom electrode layer; forming a composite hard mask comprising a bottom conducting mask disposed on top of the MTJ layer stack and a top conducting mask with a dielectric mask interposed therebetween; etching the MTJ layer stack with the composite hard mask thereon to form a patterned MTJ while consuming the top conducting mask, thereby exposing the dielectric mask on top; and trimming the patterned MTJ with the bottom conducting mask and the dielectric mask thereon by ion beam etching to remove redeposited material and damaged material from surface of the patterned MTJ while consuming most of the dielectric mask.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: March 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Dong Ha Jung, Kimihiro Satoh, Jing Zhang, Yiming Huai
  • Method of fabricating a magnetic tunnel junction device
    Patent number: 8975091
    Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Min-Hwa Chi, Mieno Fumitake
  • MRAM etching processes
    Patent number: 8975088
    Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Rajiv Yadav Ranjan, Parviz Keshtbod, Roger K. Malmhall
  • MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS
    Publication number: 20150064806
    Abstract: A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets.
    Type: Application
    Filed: November 10, 2014
    Publication date: March 5, 2015
    Inventors: Qing Cao, Oki Gunawan
  • METHOD FOR FABRICATING MAGNETORESISTIVE RANDOM ACCESS MEMORY ELEMENT
    Publication number: 20150064805
    Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.
    Type: Application
    Filed: October 31, 2014
    Publication date: March 5, 2015
    Inventors: Chun-I Hsieh, Chang-Rong Wu
  • MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150061053
    Abstract: According to one embodiment, a magnetoresistive element is disclosed. The element includes a first magnetic film, a second magnetic film, and a first nonmagnetic layer formed between the first magnetic film and the second magnetic film. The second magnetic film includes a first magnetic layer formed on a side of the first nonmagnetic layer, a second magnetic layer formed on a side opposite to the first nonmagnetic layer, and a second nonmagnetic layer formed between the first magnetic layer and the second magnetic layer and containing TiN.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 5, 2015
    Inventors: Masahiko NAKAYAMA, Tadashi KAI, Masaru TOKO, Toshihiko NAGASE, Hiroaki YODA
  • Magnetic Tunnel Junction Device
    Publication number: 20150061051
    Abstract: A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hang Huang, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Reversed Stack MTJ
    Publication number: 20150061052
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • METHOD FOR MANUFACTURING NIOBATE-SYSTEM FERROELECTRIC THIN FILM DEVICE
    Publication number: 20150064804
    Abstract: There is provided a method for manufacturing a niobate-system ferroelectric thin film device, including: a lower electrode film formation step of forming a lower electrode film on a substrate; a niobate-system ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask formation step of forming a desired etch mask pattern on the niobate-system ferroelectric thin film; and a ferroelectric thin film etching step of forming a desired fine pattern of the niobate-system ferroelectric thin film by wet etching using an etchant including an aqueous alkaline solution of a chelating agent.
    Type: Application
    Filed: May 12, 2014
    Publication date: March 5, 2015
    Applicant: Hitachi Metals, Ltd.
    Inventors: Fumimasa HORIKIRI, Kenji SHIBATA, Kazufumi SUENAGA, Kazutoshi WATANABE, Masaki NOGUCHI
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20150060969
    Abstract: A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. One of the lower electrode and the upper electrode is connected to an impurity region of the transistor. The second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode. The lower electrode is formed from the same material as the first electrode, the ferroelectric is formed from the same material as the first dielectric, and the upper electrode is formed from the same material as the second electrode.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 5, 2015
    Inventor: Osamu Matsuura
  • Semiconductor storage device and manufacturing method thereof
    Patent number: 8969983
    Abstract: A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kanaya
  • Three axis magnetic sensor device and method using flex cables
    Patent number: 8969101
    Abstract: A method and structure for a three-axis magnetic field sensing device. An IC layer having first bond pads and second bond pads can be formed overlying a substrate/SOI member with a first, second, and third magnetic sensing element coupled the IC layer. One or more conductive cables can be formed to couple the first and second bond pads of the IC layer. A portion of the substrate member and IC layer can be removed to separate the first and second magnetic sensing elements on a first substrate member from the third sensing element on a second substrate member, and the third sensing element can be coupled to the side-wall of the first substrate member.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 3, 2015
    Assignee: mCube Inc.
    Inventors: Hong Wan, Anthony F. Flannery
  • Method for Applying Magnetic Shielding Layer, Method for Manufacturing a Die, Die and System
    Publication number: 20150054102
    Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Inventors: Christian Peters, Robert Allinger, Klaus Knobloch, Snezana Jenei
  • MTJ STRUCTURE AND INTEGRATION SCHEME
    Publication number: 20150056722
    Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 26, 2015
    Inventors: Xia Li, Seung Hyuk Kang, Matthew Michael Nowak
  • Method of manufacturing magnetic tunnel junction memory element
    Patent number: 8962349
    Abstract: The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Benjamin Chen, Kimihiro Satoh, Jing Zhang, Dong Ha Jung
  • Co/Ni multilayers with improved out-of-plane anisotropy for magnetic device applications
    Patent number: 8962348
    Abstract: A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: February 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Multi-step deposition of ferroelectric dielectric material
    Patent number: 8962350
    Abstract: Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Bhaskar Srinivasan, Brian E. Goodlin, Haowen Bu, Mark Visokay
  • Semiconductor device and method of manufacturing the same
    Patent number: 8962347
    Abstract: A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS
    Publication number: 20150050750
    Abstract: A plasma processing method of etching a multilayered material having a structure where a first magnetic layer 105 and a second magnetic layer 103 are stacked with an insulating layer 104 therebetween is performed by a plasma processing apparatus 10 including a processing chamber 12 where a processing space S is formed; and a gas supply unit 44 of supplying a processing gas into the processing space, and includes a first etching process where the first magnetic layer is etched by supplying a first processing and generating plasma, and the first etching process is stopped on a surface of the insulating layer; and a second etching process where a residue Z is removed by supplying a second processing gas and generating plasma. The first magnetic layer and the second magnetic layer contain CoFeB, the first processing gas contains Cl2, and the second processing gas contains H2.
    Type: Application
    Filed: April 22, 2013
    Publication date: February 19, 2015
    Applicant: Tokyo Electron Limited
    Inventors: Takashi Sone, Daisuke Urayama, Masato Kushibiki, Nao Koizumi, Wataru Kume, Eiichi Nishimura, Fumiko Yamashita
  • SMALL FORM FACTOR MAGNETIC SHIELD FOR MAGNETORESTRICTIVE RANDOM ACCESS MEMORY (MRAM)
    Publication number: 20150048465
    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.
    Type: Application
    Filed: September 26, 2014
    Publication date: February 19, 2015
    Inventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
  • Magnetic tunnel junctions and fabrication method thereof
    Patent number: 8956883
    Abstract: A method is provided for fabricating a magnetic tunnel junction. The method includes providing a substrate having a first dielectric layer and a first electrode layer formed in the first dielectric layer; and forming a composite magnetic layer on the first electrode layer and the first dielectric layer. The method also includes forming a first mask layer with a first shape and a second mask layer on a surface of the composite magnetic layer. Further, the method includes removing a portion of the first mask layer to form an opening; and forming a sidewall spacer on side surfaces of the first mask layer and the second mask layer in the opening. Further, the method also includes removing the second mask layer; and forming a composite magnetic structure having the first shape outer surface and a second shape inner surface by etching the composite magnetic layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: February 17, 2015
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Zhongshan Hong
  • Method of manufacturing a FeRAM device
    Patent number: 8956881
    Abstract: A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO2 film) of a predetermined pattern is formed on the Pt film, and the Pt film and the upper electrode film are etched. Then, an insulating protective film is formed on an entire surface, and a side surface of the upper electrode film is covered with the insulating protective film. Next, the ferroelectric film and the lower electrode film are etched, thus forming a ferroelectric capacitor.
    Type: Grant
    Filed: February 16, 2013
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Method of manufacturing magnetoresistive element
    Patent number: 8956882
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 17, 2015
    Inventors: Kazuhiro Tomioka, Satoshi Seto, Masatoshi Yoshikawa, Satoshi Inada
  • SYSTEMS AND METHODS FOR INTEGRATED VOLTAGE REGULATORS
    Publication number: 20150042400
    Abstract: A multi-chip module (MCM) is disclosed, which in some embodiments can include a packaging substrate, an interposer coupled to the substrate and having a power converter coupled to one or more vias, and a CMOS integrated circuit comprising one or more connecters aligned with and disposed proximate to the one or more vias to electrically couple the interposer to the integrated circuit. Methods of forming a voltage regulator on an interposer of a multi-chip module (MCM) are also provided.
    Type: Application
    Filed: July 16, 2014
    Publication date: February 12, 2015
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Noah Andrew Sturcken, Kenneth L. Shepard
  • FABRICATION PROCESS AND LAYOUT FOR MAGNETIC SENSOR ARRAYS
    Publication number: 20150044782
    Abstract: A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout.
    Type: Application
    Filed: October 22, 2014
    Publication date: February 12, 2015
    Inventors: Phillip Mather, Jon Slaughter, Nicholas Rizzo
  • METHOD OF FORMING MAGNETIC MEMORY DEVICES
    Publication number: 20150044781
    Abstract: Provided is a method of forming a magnetic memory device. A first magnetic layer, a tunnel barrier, and a second magnetic layer are deposited on a substrate. The second magnetic layer, the tunnel barrier, and the first magnetic layer are etched to form magnetic tunnel junction structures. An ion beam etching process is performed using an oxygen-containing source gas to remove etching by-products on sidewalls of the magnetic tunnel junction structure and to oxidize the sidewalls of the magnetic tunnel junction structures.
    Type: Application
    Filed: May 23, 2014
    Publication date: February 12, 2015
    Inventor: Ken TOKASHIKI
  • Switching device having a non-linear element
    Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Methods for forming interconnection line using screen printing technique
    Patent number: 8951810
    Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: SK hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Ji Eun Kim, Hee Min Shin, Chong Ho Cho
  • Method of transfer by means of a ferroelectric substrate
    Patent number: 8951809
    Abstract: A method of carrying out a transfer of one or more first components or of a first layer onto a second substrate including: a) application and maintaining, by electrostatic effect, of the one or more first components or of the first layer, on a first substrate, made of a ferroelectric material, electrically charged, b) placing in contact, direct or by molecular adhesion, and transfer of the components or the layer onto a second substrate, and c) dismantling of the first substrate, leaving at least one part of the components or the layer on the second substrate.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 10, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Sebastien Moulet, Lea Di Cioccio, Marion Migette
  • Vertically oriented semiconductor device and shielding structure thereof
    Patent number: 8951812
    Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiu-Ying Cho
  • Small form factor magnetic shield for magnetorestrictive random access memory (MRAM)
    Patent number: 8952504
    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
  • Integrated DRAM memory device
    Patent number: 8952436
    Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Cremer, Frédérìc Lalanne, Marc Vernet
  • Magnetic domain wall shift register memory device readout
    Patent number: 8951811
    Abstract: A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael C. Gaidis, Alexander J. Gaidis
  • MEMORY CELL WITH SCHOTTKY DIODE
    Publication number: 20150035098
    Abstract: Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 5, 2015
    Inventor: Krishnakumar Mani
  • MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150035031
    Abstract: In an MRAM device, the MRAM includes a magnetic tunnel junction (MTJ) structure and a protection layer on a sidewall of the MTJ structure. The protection layer includes a fluorinated metal oxide. When an MRAM device in accordance with example embodiments is manufactured, a metal layer may be formed to cover a MTJ structure. The metal layer may be oxidized and fluorinated to form the protection layer. A free layer pattern included in the MTJ structure may not be oxidized and the metal layer may be fully oxidized. Because the free layer pattern is not oxidized, the MTJ structure has a good TMR. Because the metal layer is fully oxidized, the MRAM device may be prevented from electrical short between the free layer pattern and a fixed layer pattern.
    Type: Application
    Filed: April 28, 2014
    Publication date: February 5, 2015
    Inventor: Dae-Shik KIM
  • STT-MRAM cell structures
    Patent number: 8945950
    Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Integrated electronic assembly for conserving space in a circuit
    Patent number: 8945948
    Abstract: An integrated electronic assembly including a first electronic component defining a receptacle and at least a second electronic component wherein at least a portion of the second electronic component is disposed in the receptacle of the first electronic component, and a method for conserving space in a circuit or on a printed circuit board by integrating a plurality of electronic components so that the plurality of electronic components collectively take up a smaller amount of space on a substrate than the plurality of electronic components would if the plurality of electronic components were not integrated.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: February 3, 2015
    Assignee: Coilcraft, Incorporated
    Inventor: Stephen Michael Sedio
  • Semiconductor storage device with magnetoresistive element
    Patent number: 8946837
    Abstract: According to one embodiment, a semiconductor storage device is disclosed. The device includes first magnetic layer, second magnetic layer, first nonmagnetic layer between them. The first magnetic layer includes a structure in which first magnetic material film, second magnetic material film, and nonmagnetic material film between the first and second magnetic material films are stacked. The first magnetic material film is nearest to the first nonmagnetic layer in the first magnetic layer. The nonmagnetic material film includes at least one of Ta, Zr, Nb, Mo, Ru, Ti, V, Cr, W, Hf. The second magnetic material film includes stacked materials, including first magnetic material nearest to the first nonmagnetic layer among the stacked materials, and second magnetic material which is same magnetic material as the first magnetic material and has smaller thickness than the first magnetic material.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Watanabe, Katsuya Nishiyama, Toshihiko Nagase, Koji Ueda, Tadashi Kai
  • Magnetic memory and method of fabrication
    Patent number: 8946836
    Abstract: In one embodiment a magnetic memory includes a memory device base and a plurality of memory cells disposed on the memory cell base, where each memory cell includes a layer stack comprising a plurality of magnetic and electrically conductive layers arranged in a stack of layers common to each other memory cell. The magnetic memory further includes an implanted matrix disposed between the memory cells and surrounding each memory cell, where the implanted matrix includes component material of the layer stack of each memory cell inter mixed with implanted species, where the implanted matrix comprises a non-conducting material and a non-magnetic material, wherein each memory cell is electrically and magnetically isolated from each other memory cell.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 3, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Alexander C. Kontos, Steven Sherman, John J. Hautala, Simon Ruffell
  • Method for fabricating variable resistance memory device
    Patent number: 8945949
    Abstract: A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang Min Hwang