Having Substrate Registration Feature (e.g., Alignment Mark) Patents (Class 438/401)
  • Patent number: 11361980
    Abstract: A device and method for alignment of a first contact surface of a first substrate with a second contact surface of a second substrate which can be held on a second platform includes first X-Y positions of first alignment keys located along the first contact surface, and second X-Y positions of second alignment keys which correspond to the first alignment keys and which are located along the second contact surface. The first contact surface can be aligned based on the first X-Y positions in the first alignment position and the second contact surface can be aligned based on the second X-Y positions in the second alignment position.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 14, 2022
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Daniel Figura
  • Patent number: 11342184
    Abstract: An exposure apparatus for transferring a pattern of a reticle onto a wafer is provided. The exposure apparatus includes an illumination module, a reticle stage, a projection module, a wafer stage, and a control unit. The control unit is configured to calculate an alignment setting of the reticle. The wafer includes a first layer and a second layer disposed on the first layer. The first layer includes a first alignment parameter. The second layer includes a second alignment parameter. The control unit obtains a first weighting factor predetermined according to a property of the first layer, and a second weighting factor predetermined according to a property of the second layer. The alignment setting of the reticle is calculated according to the first alignment parameter, the first weighting factor, the second alignment parameter, and the second weighting factor.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 24, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Bum-Hwan Jeon, Soo-Hyoung Kim, Siwon Yang, Kihyung Lee, Byung-In Kwon
  • Patent number: 11302663
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Patent number: 11294293
    Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
  • Patent number: 11244907
    Abstract: Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tianji Zhou, Saumya Sharma, Dominik Metzler, Chih-Chao Yang, Theodorus E. Standaert
  • Patent number: 11121093
    Abstract: A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yue-Lin Peng, Cheng-Yi Huang, Fu-Jen Li, Shou-Wen Kuo
  • Patent number: 11114453
    Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can include a functional layer over a substrate. Single-crystalline silicon may not be essential to the substrate and the substrate may not include single-crystalline silicon. The first wafer can be flipped to bond onto the second wafer to form the bonded semiconductor device so the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form a top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.
    Type: Grant
    Filed: December 22, 2018
    Date of Patent: September 7, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shengwei Yang, Zhongyi Xia, Kun Han, Kang Li, Xiaoguang Wang, Hongbin Zhu
  • Patent number: 11002527
    Abstract: The present disclosure relates to measuring misalignment between layers of a semiconductor device. In one embodiment, a device includes a first conductive layer; a second conductive layer; one or more first electrodes embedded in the first conductive layer; one or more second electrodes embedded in the second conductive layer; a sensing circuit connected to the one or more first electrodes; and a plurality of time-varying signal sources connected to the one or more second electrodes, wherein the one or more first electrodes and the one or more second electrodes form at least a portion of a bridge structure that exhibits an electrical property that varies as a function of misalignment of the first conductive layer and the second conductive layer in an in-plane direction.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: May 11, 2021
    Assignee: INVENSENSE, INC.
    Inventors: Ilya Gurin, Leonardo Baldasarre
  • Patent number: 10879398
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Patent number: 10770327
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • Patent number: 10714520
    Abstract: A method for monolithically fabricating a light field sensor with an array of microlens. Each microlens is formed directly on a surface including a plurality of pixels of the light field sensor formed on a wafer. The manufacturing system performs a preparation of the surface including the plurality of pixels formed on the wafer. The manufacturing system deposits a layer of photoresist on the surface of the wafer. The manufacturing system performs a patterning on the deposited layer to form one or more blocks of cured photoresists. The manufacturing system performs a thermal curing of the one or more blocks of uncured photoresists to form an array of microlens of the light field sensor. Each microlens covers at least one of the plurality of pixels of the light field sensor formed on the wafer.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 14, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Xinqiao Liu, Yijing Fu
  • Patent number: 10527952
    Abstract: Scatterometry overlay targets and measurement methods are provided, which are configured to detect and eliminate process-related errors and illumination-related errors from overlay measurements of the targets. Targets comprise at least three cells associated with a measurement direction, wherein at least two of the cells comprise periodic structures at different target layers, having a same pitch and opposite offsets between the two cells, and at least an additional cell comprises a periodic structure with the same pitch at only one of the target layers. The additional cell(s) are used to detect irregularities in the respective periodic structure(s), enable estimation of process quality, provide reference images, enhance metrology simulations and provide mitigation of errors in critical process steps. Measurement methods incorporate scatterometry measurements ion the additional cell(s) for these purposes.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 7, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Tzahi Grunzweig, Jordan Pio, Alexander Svizher
  • Patent number: 10381311
    Abstract: A method of arranging a plurality of semiconductor structural elements on a carrier includes arranging at least some of the semiconductor structural elements in multiple groups G and at least one semiconductor structural element of a group G has a property E that determines the position of the respective group G of semiconductor structural elements on the carrier.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: August 13, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Tobias Meyer
  • Patent number: 10367079
    Abstract: A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Patent number: 10252507
    Abstract: A process of forward deposition of a material onto a target substrate is accomplished by passing a burst of ultrafast laser pulses of a laser beam through a carrier substrate that is transparent to a laser beam. The carrier substrate is coated with a material to be transferred on the bottom side thereof. Electrons on the back side of said transparent carrier coated with the material are excited by the first few sub-pulses of the laser beam which lifts the material from the carrier substrate and subsequent sub-pulse of the laser beam send the material into space at hypersonic speed by a shock wave that drives the material with forward momentum across a narrow gap between the carrier substrate and the target substrate, and onto the target substrate.
    Type: Grant
    Filed: November 16, 2014
    Date of Patent: April 9, 2019
    Assignee: ROFIN-SINAR TECHNOLOGIES LLC
    Inventor: S. Abbas Hosseini
  • Patent number: 10249665
    Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: April 2, 2019
    Assignee: Sony Corporation
    Inventors: Yuichi Yamamoto, Hayato Iwamoto
  • Patent number: 10163522
    Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Tsung Lien, Fang-Lan Chu, Hong-Da Lin, Wei Cheng Wu, Ku-Ning Chang, Yu-Chen Wang
  • Patent number: 10035226
    Abstract: A method for cutting a preform usable for production of a turbomachine part and including a weaving of a plurality of threads, the threads including single threads that are visually identifiable, along a cutting contour calculated based on a preform model in which the threads have a reference arrangement, the method including: taking an image of the preform; processing the image to determine a deviation in an arrangement of the threads which are visually identifiable relative to the reference layout; correcting the cutting contour according to the deviation; and cutting the preform along the corrected cutting contour.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 31, 2018
    Assignee: SNECMA
    Inventors: Yann Marchal, Philippe Marolle, Claire Rousseau
  • Patent number: 9972547
    Abstract: According to one embodiment, there is provided a measurement method. The method includes measuring an amount of overlay shift between a first layer and a second layer using a first overlay mark and a second overlay mark. The first layer is provided as a layer including the first overlay mark above a first substrate. The second layer is provided as a layer including the second overlay mark above the first overlay mark. The method includes acquiring a parameter related to asymmetry of a shape of the second overlay mark. The method includes obtaining an amount of correction with respect to a measured value of the amount of overlay shift based on the acquired parameter and the measured amount of overlay shift.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 15, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koutarou Sho
  • Patent number: 9972775
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Yong Wee Poh, Hai Cong
  • Patent number: 9902093
    Abstract: A press-forming mold has a protective film for preventing seizing during press-forming formed on at least a forming surface that comes into contact with a formed body. The protective film is formed by PVD. An arbitrary selection section extracted from the surface of the protective film is divided into a plurality of individual sections; and, when the gradient of the surface at the nth division point is represented by (dZn/dXn), taking N to represent the number of divisions, the root-mean-square R?q calculated by the following numerical expression is no greater than 0.032. R ? ? ? ? ? q = 1 N ? ? n = 1 N ? ? ( d ? ? Z n d ? ? X n ) 2 It is thereby possible to improve the seizing resistance of a press-forming mold having a protective film formed by PVD.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 27, 2018
    Assignees: NIPPON KOSHUHA STEEL CO., LTD., KOBE STEEL, LTD.
    Inventors: Takaharu Kashi, Kenji Yamamoto
  • Patent number: 9905639
    Abstract: By using a single trench mask, first and second trenches are formed that extend from a main surface into a semiconductor layer. A foundation is formed that includes first regions in and/or directly adjoining the first trenches. A superstructure is formed in alignment with the foundation by using position information directly obtained from structures formed in the first and/or the second trenches.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: February 27, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Daniel Tutuc, Andreas Voerckel
  • Patent number: 9859246
    Abstract: A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 2, 2018
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Andreas Fehkuhrer
  • Patent number: 9818661
    Abstract: A semiconductor unit includes: a substrate made of a semiconductor; and a device group formed on the substrate and configured of a plurality of first capacitors, in which the device group includes one or a plurality of first conductive layers and a second conductive layer, the first and second conductive layers provided to be superimposed on each other in part or as a whole with an insulating film in between, the first conductive layer includes an edge extending along one direction, the second conductive layer includes a plurality of sub-conductive layers having substantially same shapes as one another, and the plurality of sub-conductive layers are arranged in relatively different positions with respect to the edge of the first conductive layer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: November 14, 2017
    Assignee: SONY CORPORATION
    Inventors: Manabu Tomita, Yuzo Fukuzaki, Kazuhisa Ogawa
  • Patent number: 9741665
    Abstract: A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Chang, Shyh-Fann Ting, Ching-Chun Wang, Dun-Nian Yaung
  • Patent number: 9685505
    Abstract: A semiconductor device that includes: a semiconductor layer of a first conductivity type, having a peripheral area and a cell area inside of the peripheral area; a region of a second conductivity type in the semiconductor layer in the cell area; and a plurality of guard rings of the second conductivity type in the semiconductor layer in the peripheral area, each having a substantially same depth as the region of the second conductivity type in the cell area. The plurality of guard rings include at least one first ring that has a diffusion region in the depth profile in the semiconductor layer that is wider at a top thereof.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: June 20, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Yusuke Kubo
  • Patent number: 9659670
    Abstract: Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: May 23, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: SunYong Choi, YeonHo Pae, Ellis Chang
  • Patent number: 9627326
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 9620655
    Abstract: Laser foil trim approaches for foil-based metallization of solar cells, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes attaching a metal foil sheet to a surface of a wafer to provide a unified pairing of the metal foil sheet and the wafer, wherein the wafer has a perimeter and the metal foil sheet has a portion overhanging the perimeter. The method also includes laser scribing the metal foil sheet along the perimeter of the wafer using a laser beam that overlaps the metal foil sheet outside of the perimeter of the wafer and at the same time overlaps a portion of the unified pairing of the metal foil sheet and the wafer inside the perimeter of the wafer to remove the portion of the metal foil sheet overhanging the perimeter and to provide a metal foil piece coupled to the surface of the wafer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Robert Woehl, Richard Hamilton Sewell, Mohamed A. Elbandrawy, Taeseok Kim, Thomas P. Pass, Benjamin Ian Hsia, David Fredric Joel Kavulak, Nils-Peter Harder
  • Patent number: 9595690
    Abstract: A display apparatus including a substrate having an active area and a sealing area surrounding the active area; a display unit disposed on the active area of the substrate; a sealing member including a recess, which is formed in the sealing area of the substrate and is concave in a direction from an edge of the substrate to the active area of the substrate or from the active area of the substrate to the edge of the substrate; and an alignment mark disposed between the recess and the edge of the substrate or between the recess and the active area of the substrate.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sangshin Lee
  • Patent number: 9582859
    Abstract: A method for depth-image-based rendering, the method comprising the steps of: obtaining a first reference view; obtaining a depth map for the first reference view; obtaining a second reference view; obtaining a depth map for the second reference view; the method further comprising the steps of extracting noise present in the first and the second reference views; denoising the first and the second reference views and, based on the denoised first and second reference views, rendering an output view using depth-image-based rendering; adding the extracted noise to the output view.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 28, 2017
    Assignee: POLITECHNIKA POZNANSKA
    Inventors: Marek Domanski, Tomasz Grajek, Damian Karwowski, Krzysztof Klimaszewski, Olgierd Stankiewicz, Jakub Stankowski, Krzysztof Wegner
  • Patent number: 9568543
    Abstract: A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
  • Patent number: 9570402
    Abstract: An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 14, 2017
    Assignee: SK HYNIX INC.
    Inventors: Woo Yung Jung, Yong Hyun Lim, Jung A Yoo
  • Patent number: 9564326
    Abstract: A method of forming a semiconductor structure by; forming a first mask trench in a first mask, where the first mask is on a substrate; forming a second mask in the first mask trench; and forming a third mask between the first mask and the second mask by reacting the first mask with the second mask, where the first mask, the second mask, and the third mask all have different etching properties and the third mask is a combination of the first mask and the second mask.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9536998
    Abstract: [Problem] To provide a semiconductor device wherein withstand voltage of a gate insulating film at the upper edge of a trench is improved, and a method for manufacturing the semiconductor device. [Solution] A semiconductor device (1) includes: an n-type SiC substrate (2) having a gate trench (9) formed therein; a gate insulating film (16), which integrally includes a side-surface insulating film (18) and a bottom-surface insulating film (19); and a gate electrode (15) which is embedded in the gate trench (9), and which selectively has an overlap portion (17) that overlaps, at the upper edge (26), the surface (21) of the SiC substrate (2). In the side-surface insulating film (18), an overhung portion (27) that is selectively thick compared with other portions of the side-surface insulating film (18) is formed such that the overhung portion protrudes, at the upper end edge (26), toward the inside of the gate trench (9).
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: January 3, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Hiroyuki Sakairi
  • Patent number: 9525005
    Abstract: A CIS structure is provided, including a translucent structure, a reflective structure surrounding the translucent structure, and a micro lens disposed on a side of the translucent structure. The reflective structure includes a first reflective layer surrounding the translucent structure, a second reflective layer surrounding the first reflective layer, and a third reflective layer surrounding the second reflective layer. The first, second, and third reflective layers respectively have refractive indexes N1, N2, and N3, wherein N1>N2>N3.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: December 20, 2016
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventor: Zong-Ru Tu
  • Patent number: 9508655
    Abstract: An identification mark formation method for forming an identification mark on a refractory material single crystal substrate that is made of one selected from the group consisting of sapphire, gallium nitride, aluminum nitride, diamond, boron nitride, zinc oxide, gallium oxide, and titanium dioxide is disclosed. The method includes: (a) scanning a principal surface of the refractory material single crystal substrate with a laser beam at a first energy density such that a groove is formed in the principal surface of the refractory material single crystal substrate, thereby forming an identification mark in the principal surface of the refractory material single crystal substrate; and (b) scanning an inside of the groove of the refractory material single crystal substrate with a laser beam at a second energy density that is lower than the first energy density.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: November 29, 2016
    Assignee: HITACHI METALS, LTD.
    Inventor: Sadahiko Kondo
  • Patent number: 9455206
    Abstract: An overlay measuring method includes irradiating an electron beam onto a sample, including a multi-layered structure of overlapped upper and lower patterns formed thereon, to obtain an actual image of the upper and lower patterns. A first image representing the upper pattern and a second image representing the lower pattern are obtained from the actual image. A reference position for the upper and lower patterns is determined from a design image of the upper and lower patterns. A position deviation of the upper pattern with respect to the reference position in the first image and a position deviation of the lower pattern with respect to the reference position in the second image are calculated to determine an overlay between the upper pattern and the lower pattern.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: September 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Jin Yun, Woo-Seok Ko, Yu-Sin Yang, Sang-Kil Lee, Chung-Sam Jun
  • Patent number: 9437550
    Abstract: Semiconductor device and method of forming a semiconductor device are disclosed. The method includes providing a substrate. A dielectric layer is formed on the substrate. The dielectric layer includes an upper and lower level. The upper level of the dielectric layer is patterned to form at least first and second trench openings and alignment mark openings. One of the first and second trench openings serve as a through via (TV) trench while another trench opening serves as an interconnect trench. A TV opening aligned to the TV trench is formed. The TV opening extends partially into the substrate. A conductive layer is formed over the substrate to fill the trenches and the openings.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shunqiang Gong, Juan Boon Tan, Wei Liu, Hai Cong
  • Patent number: 9360769
    Abstract: A method of, and associated apparatus for, determining focus corrections for a lithographic projection apparatus. The method comprises exposing a plurality of global correction fields on a test substrate, each comprising a plurality of global correction marks, and each being exposed with a tilted focus offset across it; measuring a focus dependent characteristic for each of the plurality of global correction marks to determine interfield focus variation information; and calculating interfield focus corrections from the interfield focus variation information.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: June 7, 2016
    Assignee: ASML Netherlands B.V.
    Inventors: Arend Johannes Kisteman, Wim Tjibbo Tel, Thomas Theeuwes, Antoine Gaston Marie Kiers
  • Patent number: 9349695
    Abstract: A semiconductor integrated device includes a substrate having an active region defined thereon, a plurality of active fins positioned in the active region, and a plurality of first protecting fins surrounding the active region. Each of the plurality of active fins extends along a first direction and includes a first length along the first direction. The plurality of first protecting fins extend along the first direction. One of the plurality of first protecting fins immediately adjacent to the active region has a second length along the first direction, and the second length is longer than the first length.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Hong, Po-Chao Tsao
  • Patent number: 9343326
    Abstract: A chemical mechanical polishing (CMP) slurry composition for polishing an organic layer and a method of forming a semiconductor device using the same are disclosed. The CMP slurry composition may include from 0.001% to 5% by weight of oxide-polishing particles; from 0.1% to 5% by weight of an oxidant; from 0% to 5% by weight of a polishing regulator; from 0% to 3% by weight of a surfactant; from 0% to 3% by weight of a pH regulator; and from 79% to 99.889% by weight of deionized water. The use of the CMP slurry composition makes it possible to allow a silicon-free organic layer to be polished with a selectivity higher than 6:1 with respect to an oxide layer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Jeong Kim, Sang-Kyun Kim, Kwang-Bok Kim, Ye-Hwan Kim, Jung-Sik Choi, Choong-Ho Han, Gi-Sik Hong
  • Patent number: 9318443
    Abstract: An identification mark formation method for forming an identification mark on a refractory material single crystal substrate that is made of one selected from the group consisting of sapphire, gallium nitride, aluminum nitride, diamond, boron nitride, zinc oxide, gallium oxide, and titanium dioxide is disclosed. The method includes: (a) scanning a principal surface of the refractory material single crystal substrate with a laser beam at a first energy density such that a groove is formed in the principal surface of the refractory material single crystal substrate, thereby forming an identification mark in the principal surface of the refractory material single crystal substrate; and (b) scanning an inside of the groove of the refractory material single crystal substrate with a laser beam at a second energy density that is lower than the first energy density.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: April 19, 2016
    Assignee: HITACHI METALS, LTD.
    Inventor: Sadahiko Kondo
  • Patent number: 9271433
    Abstract: A method of manufacturing a display device includes providing a display panel including a first alignment mark on one side of opposite facing sides, obtaining location information of the first alignment mark by imaging the one side of the display panel, providing a flexible printed circuit board that includes a second alignment mark and a subsidiary mark on one side of the flexible printed circuit board, the subsidiary mark being spaced apart from the display panel and being spaced a predetermined distance apart from the second alignment mark, aligning the first alignment mark and the second alignment mark by disposing the subsidiary mark to be spaced the predetermined distance apart from the first alignment mark on the basis of the location information of the first alignment mark, and bonding the display panel and the flexible printed circuit board.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: February 23, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Do hyung Ryu, Hae goo Jung
  • Patent number: 9257283
    Abstract: A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 9, 2016
    Assignee: General Electric Company
    Inventors: Joseph Darryl Michael, Stephen Daley Arthur, Tammy Lynn Johnson, David Alan Lilienfeld
  • Patent number: 9252061
    Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung Yu Hsieh, Hui Peng Koh
  • Patent number: 9252106
    Abstract: Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes preparing a substrate in which a scribe lane region and a chip region are defined, forming a trench in the scribe lane region of the substrate, forming a stopper layer in a part in the trench, and forming an alignment mark material on the stopper layer.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 2, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Kil Lee, Chan-Ho Park, Nam-Ki Cho, Won-Sang Choi
  • Patent number: 9230917
    Abstract: A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: January 5, 2016
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Tarja Hauck, Alessia Sciré, Dieter Kaiser, Andreas Greiner, Morgana Nicolo, Carolin Wetzig, Dietrich Burmeister
  • Patent number: 9225336
    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: December 29, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Takayuki Ikeda, Yoshiyuki Kurokawa, Munehiro Kozuma
  • Patent number: 9190488
    Abstract: One method disclosed includes forming a replacement gate structure for a device. The method includes forming a gate cavity above a semiconductor substrate. The method further includes forming a first bulk metal layer in the gate cavity above a work function metal layer. The method further includes forming a conductive etch stop layer in the gate cavity above the first bulk metal layer. The method further includes forming a second bulk metal layer in the gate cavity above the conductive etch stop layer. The method further includes performing at least one etching process to recess the first and second bulk metal layers selectively relative to the conductive etch stop layer. The method further includes performing at least one etching process to recess at least the conductive etch stop layer.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Hoon Kim, Min Gyu Sung