Abstract: A method of anodizing a lightly doped wafer wherein there is provided a lightly p-typed doped silicon wafer having a frontside and a backside. A p-type region is formed on the backside doped sufficiently to avoid inversion to n-type when a later applied current density of predetermined maximum value is applied to the backside. The wafer is placed in the electrolyte of a chamber having an electrolyte and having a pair of electrodes, preferably platinum, on opposite sides of the wafer and in the electrolyte. The current of predetermined value is passed between the electrodes and through the wafer, the current being sufficient to cause pores to form on the frontside of the wafer. The chamber preferably has first and second regions, one of the electrodes being disposed in one of the regions and the other electrode being disposed in the other regions with the wafer hermetically sealing the first region from the second region.

Abstract: In a method of fabricating an SOI wafer, an oxide film is formed on the surface of at least one of two silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form a fine bubble layer (enclosed layer) within the wafer; the ion-implanted silicon wafer is superposed on the other silicon wafer such that the ion-implanted surface comes into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed in order to delaminate a portion of the ion-implanted wafer while the fine bubble layer is used as a delaminating plane, in order to form a thin film to thereby obtain an SOI wafer. In the method, a defect layer at the delaminated surface of the thus-obtained SOI wafer is removed to a depth of 200 nm or more through vapor-phase etching, and then mirror polishing is performed. Therefore, the obtained SOI wafer has an extremely low level of defects and a high thickness uniformity.

Abstract: Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Abstract: An n.sup.- layer is formed on a main surface of a p-type semiconductor substrate. A p.sup.- diffusion region is formed at a surface of n.sup.- layer. A p diffusion region is formed contiguous to one end of p.sup.- diffusion region. A plurality of p diffusion regions containing p-type impurity the concentration of which is higher than that of p.sup.- diffusion region are formed in p.sup.- diffusion region. A p diffusion region is formed such that it is spaced apart from p.sup.- diffusion region. A gate electrode is formed on a surface of n.sup.- layer positioned between p diffusion region and p.sup.- diffusion region with an oxide film interposed. A drain electrode is formed in contact with a surface of p diffusion region. Furthermore, an n diffusion region is formed adjacent to p diffusion region, and a source electrode is formed in contact with both a surface of n diffusion region and a surface p diffusion region.

Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.

Abstract: A method for producing a porous film on a silicon substrate is described. The substrate 14 is placed in a vacuum chamber in the presence of oxygen at specified pressure and temperature for a period of time to form a thin oxide film 10 thereon. Then the conditions in the chamber are altered so that voids 14 of a desired dimension are formed in the oxide film 10. Alternatively, a substrate 20 is subjected to specific conditions in the vacuum chamber whereat oxide islands 22 nucleate on the surface. As the islands grow, they eventually cover most of the surface leaving voids 24 of the desired size.