Abstract: Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films.

Abstract: The present disclosure provides an integrated circuit device and method for manufacturing the integrated circuit device. The disclosed method provides substantially defect free epitaxial features. An exemplary method includes forming a gate structure over the substrate; forming recesses in the substrate such that the gate structure interposes the recesses; and forming source/drain epitaxial features in the recesses. Forming the source/drain epitaxial features includes performing a selective epitaxial growth process to form an epitaxial layer in the recesses, and performing a selective etch back process to remove a dislocation area from the epitaxial layer.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).

Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.

Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: A method for fabricating a dielectric layer with improved insulating properties is provided, including: providing a dielectric layer having a first resistivity; performing a hydrogen plasma doping process to the dielectric layer; and annealing the dielectric layer, wherein the dielectric layer has a second resistivity greater than that of the first resistivity after annealing thereof.

Abstract: Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted.

Abstract: A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer.

Abstract: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.

Abstract: A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6?), wherein the material of the insulating layers (6,6?) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.

Abstract: Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

Abstract: A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, wherein the buried layer is produced at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone with a doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone with a doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first region and the second region of the semiconductor layer. A common connection device is formed for the first dopant zone and the second dopant zone.

Abstract: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the active region includes a first vertical portion and an upper primary surface, the first vertical portion extending above the upper primary surface.

Abstract: A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the low concentration impurity. And the semiconductor device further includes a high concentration impurity region of the first type conductivity having the same type conductivity as the type of the semiconductor substrate formed in at least the epitaxial layer with the low concentration impurity along an inner wall of the trench and coupled to the semiconductor substrate with the high concentration impurity of a first type conductivity, and contacts formed on the high concentration impurity region of the first type conductivity.

Abstract: According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

Abstract: In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer.

Abstract: A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer.

Abstract: In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a bottom portion and first and second trench sidewalls. At least one trench sidewall is adjacent a doped region. The at least one sidewall adjacent a doped region has a higher impurity dopant concentration than impurity doped regions surrounding the at least one trench isolation region.

Abstract: A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word gate formed over a semiconductor layer with a gate insulating layer interposed in between, impurity layers formed in the semiconductor layer, and sidewall-shaped control gates formed along both side surfaces of the word gate. The control gate includes a first control gate and a second control gate which are adjacent to each other. The first control gate is formed on a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The second control gate is formed on a second insulating layer formed of a silicon oxide film.

Abstract: A method for fabricating a raised source/drain of a semiconductor device is described. A gate structure is formed on a substrate, and then a source/drain with a shallow-junction is formed in the substrate beside the gate structure. A spacer is formed on the sidewalls of the gate structure. Thereafter, an elevated layer is formed on the gate structure and the source/drain with a shallow junction, wherein the elevated layer formed on the source/drain serves as an elevated source/drain layer.

Abstract: Semiconductor devices are known comprising a multiple p-n junction RESURF semiconductor material (10) that provides a voltage-sustaining space-charge zone when depleted from a blocking junction (40). Charge balance is important in the alternating p-type (11) and n-type (12) regions which together provide the voltage-sustaining space-charge zone. The invention provides a low-cost yet reliable way of manufacturing such a material (10), and also devices with such a material (10). A p-type silicon body (100) having an acceptor doping concentration (Na) for the p-type regions (11) of the material is subjected to irradiation with collimated beams (152) of thermal neutrons (150) at window areas (52) in a mask (50) so as to form the n-type regions (12) by transmutation of silicon atoms into phosphorus. A well-defined and controllable phosphorus doping concentration to balance the low acceptor concentration of the p-type regions (11) is achievable in this manner, even when the acceptor concentration is of boron.

Abstract: The present invention relates to a method for fabricating a DRAM cell transistor having a trench isolation structure, which can prevent the reduction in effective channel length and the deterioration of a punch-through characteristic at the edge portion of a field oxide film, which is caused by the reduction in the potential barrier between a junction region and a channel region, which is caused because the channel doping concentration at the edge portion of the field oxide film is lowered due to a boron segregation effect caused by the field oxide film, as compared to the central portion of a channel region. According to the method of the present invention, an electrode structure having the same conductive type as that of a well region is formed within the field oxide film.

Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.

Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.

Abstract: There is disclosed a method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon (SEG) process. The method includes forming a nitride film at a predetermined in a semiconductor substrate region except for the region in which a contact plug will be formed, forming an USG film on the entire surface of the substrate in which the nitride film is formed by chemical enhanced vapor deposition method or a plasma method, etching the USG film by reactive ion etch method to expose the surface of silicon in the structure, and forming a contact plug by performing in-situ process while performing selective epitaxial growth method for the silicon film exposed through the contact hole in the structure.

Abstract: A method of fabricating a semiconductor device including the following steps of: forming a first insulating layer, a first conductive layer and a stopper layer over a semiconductor layer; forming a mask insulating layer on the first conductive layer in a logic circuit region; forming a conductive layer in a formation region of word gate layers and common contact sections and forming gate electrodes; anisotropically etching the second conductive layer to form control gates in the shape of sidewalls and a conductive layer of the common contact sections, in a memory region; and patterning the third conductive layer and the first conductive layer to form word gates and word lines.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the “array” and “kerf” areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the “array” areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the “array” areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the “kerf” areas.

Abstract: A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conductivity-altering dopant, and then isolation dopant of a conductivity type opposite to that of the substrate is introduced into the trench-circumscribed silicon region. The introduced isolation dopant is then thermally driven into the substrate, with lateral diffusion of isolation dopant physically constrained by the existing first narrow trench. Epitaxial silicon is then formed over the substrate, with polysilicon formed in regions overlying the filled narrow trench. A second, wider trench encompassing the first trench is etched to consume epitaxial silicon, polysilicon, and the sacrificial material. The second trench is then filled with dielectric material.

Abstract: A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.

Abstract: A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate electrodes are formed via a gate oxide film and then sidewall oxide films are formed, on the semiconductor substrate. Thereafter, an ion implantation of a P-type impurity is performed with a dose two orders of magnitude smaller than that of the N-type impurity for element isolation, with the gate electrodes and the sidewall oxide films being employed as a mask, thereby forming P-type impurity regions. The P-type impurity regions are caused to diffuse due to thermal processing in the following step. However, the element isolating P-type impurity regions resulted from the diffusion diffuse only into immediately under the sidewall oxide films at most, thus preventing the channel width from being narrowed.

Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of kinds of semiconductor chips 1 are COB-mounted on a substrate 2 and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Semiconductor devices 10 are produced by cutting the substrate 2 into pairs of adjacently arranged two different kinds of semiconductor chips 1 together which are judged to be nondefective chips.

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type to diffuse said impurity into a region of said semiconductor.

Abstract: An identification document and a method of placing personalized data (variable text and color image) directly on the identification document having a data receiving page. The method comprises the steps of: printing personalized data directly onto a silicone release coat of a release sheet; positioning the release sheet with the side containing fused toner adjacent to the adhesive of an adhesive side of a security laminate; passing the release sheet and the security laminate through a laminator to transfer the personalized data to the adhesive of the security laminate; removing the release sheet leaving the personalized data on the security laminate; and passing the security laminate and the data receiving page through a laminator to seal personalized data between the security laminate and the data receiving page.

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.