Plural Doping Steps Patents (Class 438/419)
  • Patent number: 5976940
    Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: November 2, 1999
    Assignee: Sony Corporation
    Inventors: Takayuki Gomi, Hiroaki Ammo
  • Patent number: 5938839
    Abstract: A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type to diffuse said impurity into a region of said semiconductor.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: August 17, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 5633180
    Abstract: A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: May 27, 1997
    Assignee: Harris Corporation
    Inventor: George Bajor
  • Patent number: 5624858
    Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: April 29, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima