Recessed Oxide Laterally Extending From Groove Patents (Class 438/426)
  • Patent number: 9577035
    Abstract: Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: February 21, 2017
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Edward Preisler, Hadi Jebory
  • Patent number: 9412812
    Abstract: An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound semiconductor stack structure; a first insulating film which is formed on the element region and is not formed on the element isolation structure; a second insulating film which is formed on at least the element isolation structure and is higher in hydrogen content than the first insulating film; and a gate electrode which is formed on the element region of the compound semiconductor stack structure via the second insulating film.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: August 9, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Toshihide Kikkawa
  • Patent number: 9029237
    Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Mahito Sawada, Tatsunori Kaneoka, Katsuyuki Horita
  • Patent number: 8993394
    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Karlheinz Mueller, Robert Gruenberger, Bernhard Winkler
  • Publication number: 20150041948
    Abstract: Semiconductor devices and fabrication methods are disclosed. A mask layer having an opening is formed on a semiconductor substrate. The semiconductor substrate is etched along the opening of the mask layer to form a trench therein. The mask layer is laterally etched from the opening of the mask layer along a top surface of the semiconductor substrate to expose a surface portion of the semiconductor substrate on each side of the opening. A liner oxide layer is formed by a thermal oxidation process on interior surface of the trench and on the exposed surface portion of the semiconductor substrate. The thermal oxidation process is controlled such that an upper corner between the top surface of the semiconductor substrate and the trench is rounded after the liner oxide layer is formed. An insulation layer is formed on the liner oxide layer and fills the trench.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 12, 2015
    Inventors: XIANYONG PU, YIQUN CHEN, ZONGGAO CHEN
  • Patent number: 8912074
    Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.
    Type: Grant
    Filed: July 13, 2014
    Date of Patent: December 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
  • Patent number: 8841197
    Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Chun-Hsien Lin, Chien-Ting Lin
  • Patent number: 8802537
    Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: August 12, 2014
    Assignee: Spansion LLC
    Inventors: Yider Wu, Unsoon Kim, Kuo-Tung Chang, Harpreet Sachar
  • Patent number: 8765575
    Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Laurent Favennec
  • Patent number: 8709901
    Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Lung Chang, Wu-Sian Sie, Jei-Ming Chen, Wen-Yi Teng, Chih-Chien Liu, Jui-Min Lee, Chih-Hsun Lin
  • Patent number: 8673736
    Abstract: Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yi Yang, Chien-Hao Chen, Tze-Liang Lee, Shih-Chang Chen, Huan-Just Lin
  • Publication number: 20140065795
    Abstract: A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 6, 2014
    Applicant: ANPEC ELECTRONICS CORPORATION
    Inventors: Yung-Fa Lin, Chia-Hao Chang
  • Patent number: 8587085
    Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Katsuyuki Horita
  • Publication number: 20130288450
    Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 31, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Daniel Benoit, Laurent Favennec
  • Patent number: 8569145
    Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuo Tomita
  • Patent number: 8536017
    Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masaru Kadoshima, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
  • Patent number: 8530292
    Abstract: A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 10, 2013
    Assignees: STMicroelectronics (Grenoble 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Yves Morand, Thierry Poiroux, Jean-Charles Barbe
  • Patent number: 8530998
    Abstract: Methods and apparatus for producing a semiconductor on insulator structure include: subjecting an implantation surface of a donor single crystal semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis, wherein a liquidus viscosity of the glass substrate is about 100,000 Poise or greater.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: September 10, 2013
    Assignee: Corning Incorporated
    Inventors: Kishor Purushottam Gadkaree, Matthew John Dejneka, Adam James Ellison
  • Patent number: 8440539
    Abstract: A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: May 14, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Michael A. Mendicino
  • Publication number: 20130087828
    Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.
    Type: Application
    Filed: June 21, 2010
    Publication date: April 11, 2013
    Inventors: Makoto Koshimizu, Hideki Niwayama, Kazuyuki Umezu, Hiroki Soeda, Atsushi Tachigami, Takeshi Iijima
  • Patent number: 8394705
    Abstract: Provided is a method of manufacturing a semiconductor device. According to the method, a first buried oxide layer is formed in the semiconductor substrate in a first region, such that a first semiconductor layer is defined on the first buried oxide layer. An active portion is defined by forming a trench in the semiconductor substrate in a second region. A capping semiconductor pattern is formed on a top surface and an upper portion of a sidewall of the active portion. An oxide layer is formed by oxidizing the capping semiconductor pattern and an exposed lower portion of the sidewall of the active portion, such that the oxide layer surrounds a non-oxidized portion of the active portion. The non-oxidized portion of the active portion is a core and one end of the core is connected to a first optical device formed at the first semiconductor.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: March 12, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Gyoo Kim, Dae Seo Park, Jun Taek Hong, Gyungock Kim
  • Patent number: 8349687
    Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
  • Patent number: 8318581
    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Karl-Heinz Mueller, Bernhard Winkler, Robert Gruenberger
  • Patent number: 8313661
    Abstract: A liner removal process is described, wherein an excess portion of a conformal liner formed in a trench is substantially removed while reducing or minimizing damage to a bulk fill material in the trench.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: November 20, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Vinh Luong, Akiteru Ko
  • Patent number: 8268703
    Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: September 18, 2012
    Assignee: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
  • Patent number: 8222101
    Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyoung-Bong Rouh
  • Patent number: 8211778
    Abstract: A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Roberto Colombo, Luca Di Piazza
  • Patent number: 8207573
    Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Se-Keun Park
  • Patent number: 8198170
    Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: June 12, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Man Fai Ng, Bin Yang
  • Patent number: 8058952
    Abstract: The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: November 15, 2011
    Assignee: NXP B.V.
    Inventors: Jozef T. M. Van Beek, Bart Van Velzen
  • Patent number: 8048765
    Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: November 1, 2011
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Bruce Chih-Chieh Shen, Henry Kuo-Shun Chen
  • Patent number: 8017496
    Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Gyun Kim, Dong-Suk Shin
  • Patent number: 8017420
    Abstract: Provided is a method of forming optical waveguide. The method includes forming a trench on a semiconductor substrate to define an active portion, and partially oxidizing the active portion. An non-oxidized portion of the active portion is included in a core through which an optical signal passes, and an oxidized portion of the active portion is included in a cladding.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 13, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In-Gyoo Kim, Dong-Woo Suh, Gyung-Ock Kim
  • Patent number: 7998772
    Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Bor-Zen Tien, Tzong-Sheng Chang, Yung-Fu Shen, Jieh-Ting Chang
  • Patent number: 7989310
    Abstract: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then RIE etched to initially remove the oxide layer from the wafer surface with continued etching to remove the oxide layers in upper trench portions to define later sealing portions of the voids or to displace the first bottlenecks downward to define further bottlenecks. A second SiO2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.
    Type: Grant
    Filed: February 5, 2005
    Date of Patent: August 2, 2011
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Karlheinz Freywald
  • Patent number: 7960736
    Abstract: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: June 14, 2011
    Assignee: Corning Incorporated
    Inventors: Kishor P. Gadkaree, Linda R. Pinckney
  • Patent number: 7960276
    Abstract: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David L. Rath, Chih-Chao Yang, Keith Kwong Hon Wong
  • Patent number: 7955960
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
  • Patent number: 7951661
    Abstract: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 31, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Sang Kim
  • Patent number: 7939423
    Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: May 10, 2011
    Assignee: Eon Silicon Solution Inc.
    Inventor: Yider Wu
  • Patent number: 7932159
    Abstract: The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cha Deok Dong
  • Patent number: 7892929
    Abstract: A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai, Jeffrey Junhao Xu
  • Patent number: 7871897
    Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-woon Shin, Soo-jin Hong, Guk-hyon Yon, Si-young Choi, Sun-ghil Lee
  • Patent number: 7867845
    Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: January 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon A. Haller, Prashant Raghu, Ravi Iyer
  • Patent number: 7855117
    Abstract: In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Jun Jang, Ho-Min Son, Woong Lee, Yong-Woo Hyung, Jung-Geun Jee
  • Patent number: 7816228
    Abstract: In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: October 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hwan Kim, Chang-Woo Oh, Yong-Lack Choi, Na-Young Kim
  • Patent number: 7807498
    Abstract: A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 5, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Masanobu Shoji, Toru Fujita
  • Patent number: 7803692
    Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: September 28, 2010
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
  • Patent number: 7795108
    Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: September 14, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Tiesheng Li, Yu Wang, Yingying Lou, Anup Bhalla
  • Patent number: 7767515
    Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: August 3, 2010
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik, Xi-Wei Lin