Abstract: A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas.

Abstract: A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

Abstract: A trench is etched in a silicon substrate covered with an oxide/nitride stack and a field oxide layer is then grown through oxidation of the silicon in the substrate such that the trench is partly filled. There is reduced oxide encroachment into the active areas under the nitride layer because of the partial field oxide growth. Double oxide layers are deposited over the surface of the field oxide layer and the oxide/nitride stack such that the oxide layers fill the remainder of the trench and produce a nearly planar topology. The double oxide layers are then etched back to the nitride layer through chemical mechanical polishing, leaving the field isolation region. After stripping the oxide/nitride stack, a gate oxide layer is grown. A minimal amount of oxide is required to fill the trench because the trench is already almost filled with the field oxide layer and because of the shallow depth of the trench. Consequently, the etch back step causes minimal dishing.

Abstract: A semiconductor device isolation structure includes a trench formed in a substrate vertically from the major surface of the substrate, a trench plug for filling the trench, and a buried insulation region formed under the trench adjacent thereto, and a method of the same includes the steps of forming a trench in a substrate and vertically from the major surface of the substrate, selectively implanting oxide ions under the trench of the substrate, and forming a trench plug so as to fill the trench.

Abstract: A method used during the formation of a semiconductor device comprises the steps of providing a semiconductor substrate assembly having at least one recess therein then forming a first dielectric layer within the recess. The first dielectric layer is formed with a thickness that will prevent the first dielectric layer from impinging on itself in the recess, for example with a thickness less than half a width of the trench. The dielectric layer is then annealed in a manner that will increase the volume of the first dielectric layer. After annealing the first dielectric layer, a second dielectric layer is formed over the first dielectric layer within the recess. The second dielectric layer is formed with a sufficient thickness such that it impinges on itself in the recess. The second dielectric layer is then annealed.

Abstract: The first trench is formed in the region of the semiconductor substrate, in which an element isolation region is to be formed, and the first buried member, which is insulative, is buried in the first trench. Then, the second trench, having a width smaller than that of the first trench, is made in the first buried member, and the portion of the semiconductor substrate which is located at the bottom portion of the first trench, and the insulating second buried member is buried in the second trench, thereby forming the element isolation region.

Abstract: A semiconductor device having a gate electrode stack formed using a patterned oxide layer is disclosed. The device is formed by forming an oxide layer over a surface of a substrate and forming at least one opening in the oxide layer. A high permittivity plug (e.g., a BST plug) is formed in the lower portion of the opening. A conductive plug (e.g., a metal silicide plug) is formed in an upper portion of the opening over the high permittivity plug. Remaining portions of the oxide layer are then removed. The conductive plug and high permittivity plug may form a gate electrode and a gate insulating layer, respectively.

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is filled-in or buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract: An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.

Abstract: The present invention provides a method to achieve shallow trench isolation (STI) on the quarter-micron scale. A thin oxide layer, a thick nitride layer, a thick oxide layer and a thin nitride layer are formed sequentially on a silicon substrate. A photo-resist (PR) layer is then applied as a mask for the isolation regions. The top nitride layer, the top oxide layer and the bottom nitride layer are then etched away from the areas not covered by the PR layer. The PR layer is then removed. An isotropic oxide etch is then applied to create a recess along the bottom oxide layer. A thin oxide layer is then grown on the exposed silicon surface. A thin nitride layer is then deposited to fill the recess in the bottom oxide layer. An anisotropic nitride etch is applied to form a nitride spacer along the isolation edge. A thick oxide layer is then grown and removed. This step is repeated as necessary to obtain the desired trench slope.

Abstract: A process for fabricating a recessed field oxide area comprises providing a substrate having isolation stacks and first and second recesses having openings therein, the first recesses being wider than the second recesses. The recesses can have a depth in the approximate range of 200.ANG.-3000.ANG.. Next, the first and second recesses are lined with nitride, and the substrate is blanketed with a conformal material which bridges the openings of the second recesses but not the openings of the first recesses. The conformal material and the nitride is removed from horizontal surfaces of the isolation stacks, and essentially all of the conformal material is removed from the first recesses. At least a portion of the conformal material is left in the second recesses. Subsequent to the step of removing the conformal material, the substrate and the conformal material is oxidized to create field oxide areas at the first and second recesses.

Abstract: Methods of forming trench-based isolation regions with reduced susceptibility to edge defects include the steps of forming trenches at a face of a semiconductor substrate and then filling the trenches with electrically insulating regions. However, to prevent exposure of those portions of the substrate extending adjacent the trenches, supplemental oxide regions are formed at the interfaces between the upper portions of the trench sidewalls and the electrically insulating regions in the trenches, by exposing the electrically insulating regions to an oxidation atmosphere at a temperature in a range between about 950.degree. C. and 1100.degree. C. In particular, the supplemental oxide regions are formed as thermal oxides of higher density than the electrically insulating regions in the trenches. Thus, the supplemental oxide regions are more resistant to chemical etchants.

Abstract: Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.

Abstract: An isolation region is formed on a substrate by forming spaced apart mesas on the substrate, each mesa including a barrier region which caps the mesa. An insulation riser is then formed in the substrate, disposed between and separated from the spaced apart mesas. Spaced apart trenches are formed in the substrate on opposite sides of the insulation riser, each trench disposed between the insulation riser and a respective one of the mesas. An insulating material layer is formed on the substrate, the insulating material layer filling the spaced apart trenches and covering the insulation riser and the mesas, and then is chemical mechanical polished to expose the mesas and thereby form an isolation region spanning the spaced apart trenches. Preferably, barrier spacers are formed on sidewall portions of the mesas, and a surface portion of the substrate between the barrier regions is thermally oxidized using the barrier regions and the barrier spacers as an oxidation barrier to form the insulation riser.

Abstract: Methods of forming electrical isolation regions in semiconductor substrates include the steps of forming a first electrical isolation region at a face of a semiconductor substrate, then forming a trench in the semiconductor substrate, laterally adjacent the first electrical isolation region, and then forming a trench isolation region in the trench so that the trench isolation region is contiguous with the first isolation region. In particular, these methods include the steps of forming a pad insulating layer on the face of a semiconductor substrate and then forming a first nitride layer on the pad insulating layer. The first nitride layer is then patterned by removing a portion thereof to define an opening extending opposite an inactive region within the semiconductor substrate. A second nitride layer is then formed on the patterned first nitride layer and in the opening.

Abstract: A method of forming shallow trenches in a semiconductor substrate is provided. This method allows the thus-formed trenches to be shaped with a rounded top corner having a desired radius of curvature in accordance with actual requirements. From experiments, it is learned that the radius of curvature of the top corners of the trenches decreases linearly with the depth of a pre-trench formed by over-etching in the substrate. The relationship between radius of curvature and depth of pre-trench can be pre-established by experimentation. After that, the top corners of the shallow trenches in the substrate can be controlled to be shaped with a desired radius of curvature by adjusting the depth of the pre-trench based on the pre-established linear relationship.

Abstract: A device-isolating trench having a taper at its upper portion is formed in a silicon semiconductor substrate. Then, a silicon oxide film is formed on the inner wall of the trench and the surface of the semiconductor substrate near the trench by an oxidizing method, and polycrystalline silicon is buried in the trench.

Abstract: A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to define and form the trench isolation region (108). Silicon sidewalls of the trench (108) and the polysilicon layer (106) are then exposed to an oxidizing ambient to form a thermal oxide trench liner (107a) and an erosion-protection polysilicon-oxide layer (107b). A trench fill material (110a) is then deposited and chemically mechanically polished (CMP) utilizing the polysilicon layer (106) as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material (110c) and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide (107d). The annular polysilicon-oxide protection regions (107d) either reduce or entirely eliminate adverse sidewall parasitic erosion which occurs in conventional trench technology when processing active areas (124).

Abstract: A semiconductor device isolating structure and method for forming such a structure. In one embodiment, an opening is formed through a mask layer overlying a semiconductor substrate. A trench of a desired depth is then etched into the semiconductor substrate at the area of the semiconductor substrate underlying the opening in the mask layer. The trench is then filled with a dielectric material. After an oxide planarizing process, the present invention exposes the dielectric-filled trench to an oxidizing environment. By filling the trench with dielectric material prior to the oxidization step, the present invention selectively oxidizes the semiconductor substrate at corners formed by the intersection of the sidewalls of the trench and the top surface of the semiconductor substrate. In so doing, the present invention forms smoothly rounded semiconductor substrate corners under the mask layer.

Abstract: Isolation regions are fabricated on a substrate by forming a pattern region on the substrate, exposing spaced apart first and second areas of the substrate. The second area is then covered, preferably using sidewall spacers formed adjacent sidewall portions of the pattern region, while a portion of the first area is left exposed. A first insulation region is then formed on the exposed portion of the first area. The second area is then exposed and a trench isolation region is formed at the second area. Preferably, the pattern region is formed by forming a masking layer on the substrate and patterning the masking layer using a single photolithographic mask. The first insulation layer preferably is formed by thermally oxidizing the exposed portion of the first area. Preferably, the first area is wider than the second area.

Abstract: A process for forming a silicon oxide-filled shallow trench on the active surface of a silicon chip starts with forming a trench in the silicon chip that has an upper portion with vertical side walls and a lower portion with tapered side walls. Then oxygen is implanted selectively into the walls of the lower portion of the trench and the chip is heated to react the implanted oxygen with the silicon to form silicon oxide. The rest of the trench is then filled with deposited silicon oxide, typically by depositing a layer of silicon oxide over the surface and then planarizing the deposited silicon oxide essentially to the level of the top of the trench. The silicon-filled shallow trench serves to divide the surface portion of the chip into discrete regions, each for housing one or more circuit components of an integrated circuit.

Abstract: A semiconductor substrate and a method of fabricating the same, and provides which the active area to be formed the active element is defined by the trench filled with any conductive polycrystal silicon in which any portion of a large number of the epitaxial layer is crystally grown on any conductive silicon substrate, and the multi-aperture silicon oxide layer is formed from the metal line to be used to the passive element or the transmitting line outside the trench, so that the interference between the passive element and the semiconductor substrate is prevented, and to attenuate the transmitting signal prevents to be attenuated in the high frequency band operation. Therefore, the semiconductor substrate for a unit active element and the MMIC to be able to operate the high frequency band is manufactured into the silicon, and thus it is advantageous to reduce the cost and enhance the yield.

Abstract: An EPROM allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM comprises a semiconductor substrate; a field insulating layer defining a device formation region of the semiconductor substrate; a gate insulating layer; a floating gate formed on the field insulating layer and the field insulating layer; a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer, one of the side walls of the trench insulating layer being self-aligned with the end face of the floating gate; a first interlaminar insulating layer covering the floating gate; a control gate located above the floating gate; a second interlaminar insulating layer formed over the whole surface; and a bit line.

Abstract: A device isolation method divides a semiconductor substrate into active and inactive regions. A first device isolation layer is formed in a first inactive region using a trench isolation method. Then, local oxidation is used to form a second device isolation layer in a second inactive region which is wider than the first. A dishing phenomenon (generated during CMP processing) is eliminated, and proper device isolation is realized without exposing the active region.

Abstract: The present invention relates to a semiconductor isolation method for high density semiconductor(devices of which the isolation pitch is below 0.5 .mu.m. The present invention provides the semiconductor isolation method to improve the isolating characteristics of the semiconductor device by separately performing the isolation process for the area where the isolation pitch is wide from the area where it is narrow.

Abstract: A semiconductor device with a trench element isolation structure having a trench element isolation film formed to have a small width at the boundary between an active region and a field region, thereby capable of obtaining an improved element isolation function while easily planarizing an insulating film formed in the trench. A thick oxide film is formed at the field region provided with no trench, thereby preventing formation of a parasitic capacitor between the semiconductor substrate and the gate electrode.

Abstract: In the manufacture of semiconductor integrated circuit devices, semiconductor regions such as, e.g., doped regions or tubs are separated by an etched trench which is self-aligned with respect to such regions on account of the presence of an etch-resistant layer overlying the regions during etching. In accordance with preferred processing of the invention a first layer is formed alongside the trench to be etched, a spacer second layer is formed alongside the edge of the first layer, and a third layer is formed abutting the spacer. The spacer is etched away while first and third layers remain in place, and the trench is etched in the space between the first and third layers. A preferred etchant comprises CF.sub.3 Br and oxygen.