Abstract: The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first width. The semiconductor device further includes isolation patterns respectively located between the active patterns to insulate the active patterns from one another.

Abstract: Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.

Abstract: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

Abstract: An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be more finely formed. The method of producing a semiconductor device according to the present invention includes forming a small opening by utilizing cubical expansion due to the oxidation of silicon. Thereby forming the lower electrode smaller than that can be formed by lithography techniques.

Abstract: An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width.

Abstract: A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a plasma CVD method with using a silicon source gas. By using anisotropic character of a plasma, the epitaxial layer is selectively deposited on a bottom of the trench. Thus, the trench is filled with the epitaxial layer having no void.

Abstract: A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer filling the trench, the dopant diffusion barrier layer a barrier to diffusion of semiconductor dopants. Also a power transistor formed by the same method.

Abstract: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line.

Abstract: A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

Abstract: By providing a conductive connection between the active semiconductor layer and the substrate material in an SOI device during the anisotropic etch process for forming a deep trench portion in the substrate material, the uniformity of the etch conditions may be increased, thereby enabling greater etch depth and enhanced controllability with respect to the shape of the deep trench portion.

Abstract: According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer.

Abstract: A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.

Abstract: The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device, in one embodiment, includes a substrate having a first device region and a second device region, wherein the first device region includes a first gate structure and first source/drain regions and the second device region includes a second gate structure and second source/drain regions. The semiconductor device further includes a trench isolation structure configured to isolate the first device region from the second device region, the trench isolation structure comprising: 1) an isolation trench located within the substrate, wherein the isolation trench includes an opening portion and a bulbous portion, and further wherein a maximum width of the opening portion is less than a maximum width of the bulbous portion, and 2) dielectric material substantially filling the isolation trench.

Abstract: A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.

Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

Abstract: A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so that the entire circuit is compatible with SOI technology.

Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

Abstract: The semiconductor device comprises a p type Si substrate 10; a SiGe buffer layer 12 formed on the p type Si substrate 10 and having element isolation grooves 16 formed in the surface, which define an active region 18; a SiGe regrown buffer layer 20 formed on the SiGe buffer layer 12; a strained Si channel layer 22 formed on the side walls of the element isolation grooves 16 and on the SiGe regrown buffer layer 20 in the active region; a SiN film 24 formed on the strained Si channel layer 22 on the side walls of the element isolation grooves 16; and an element isolation insulation film 26 buried in the element isolation grooves.

Abstract: An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

Abstract: The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact with an inner surface of the isolation trench, a silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the silicon films. According to the present invention, the silicon film within the isolation trench can be substantially regarded as a part of the silicon substrate. Therefore, even when the width of the isolation trench is increased to increase the etching rate, the width of the insulation film becoming a dead space can be made sufficiently small. Consequently, the chip area can be decreased.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.

Abstract: A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

Abstract: Compression stress applying portions 20 of SiGe film are formed in the source/drain regions of the p-MOSA region 30a. Then, impurities are implanted in the p-MOS region 30a and the n-MOS region 30b to form shallow junction regions 22a, 22b and deep junction regions 23a, 23b. The impurity in the shallow junction regions 22a, 22b is prevented from being diffused immediately below the gate insulation film 15 by the thermal processing in forming the SiGe film, the short channel effect is prevented, and the hole mobility of the channel region of the p-MOS transistor 14a. The operation speed of the p-MOS transistor 13a is balanced with that of the n-MOS transistor, whereby the operation speed of the complementary semiconductor device 10 can be increased. The semiconductor device fabricating method can increase and balance the operation speed of a p-transistor with that of an n-transistor.

Abstract: A semiconductor device includes: a silicon substrate; a first trench formed on a surface portion of the silicon substrate to isolate a plurality of active regions from one another; a first element isolation layer embedded in the first trench; a plurality of selectively-grown silicon layers formed on the respective active regions; and a second element isolation layer embedded in a second trench defined by the top surface of the first element isolation layer and opposing side surfaces of adjacent two of the selectively-grown silicon layers.

Abstract: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.

Abstract: A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench.

Abstract: Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the formation of shallow trench isolation (STI) regions. Following trench formation, the layers of epitaxial silicon are grown from silicon-containing layers on opposing sides of the tunnel dielectric layer, thereby permitting their thickness to be limited to approximately one-half of the thickness of the tunnel dielectric layer. The epitaxial silicon may be oxidized prior to filling the trench with a dielectric material or a dielectric fill may occur prior to oxidizing at least the epitaxial silicon covering the ends of the tunnel dielectric layer.

Abstract: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention provides a channel region formed over a device isolation structure to form a semiconductor device including a SOI (Silicon-on-Insulator) channel structure, thereby decreasing ion implanting concentration of a channel region and improving tWR (Write Recovery time) and LTRAS (Long Time for Row Address Strobe) characteristics of the device.

Abstract: A semiconductor fabrication method. First, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench includes a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. Next, portions of the blocking layer on the {110} side wall surfaces are removed without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.

Abstract: A method of fabricating a semiconductor device includes forming a conductive layer on a semiconductor substrate, forming an insulating layer on the conductive layer, forming a word line and isolation trenches by patterning the insulating layer and the conductive layer, forming an isolation layer that fills the isolation trenches, forming a cell contact hole in the insulating layer such that the cell contact hole is self-aligned with the word line and exposes the word line, and forming a cell diode in the cell contact hole.

Abstract: A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

Abstract: Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed method further comprises forming an etching groove in the active region. The etching groove separates a source region and a drain region. The disclosed method also comprises growing an epitaxial layer within the etching groove; forming a gate insulating layer on the epitaxial layer; depositing a first polysilicon layer on inner sidewalls of the opening and on the gate insulating layer; forming a dielectric layer on the first polysilicon layer; and depositing a second polysilicon layer on the dielectric layer.

Abstract: A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first and third device structures are device isolation structures. A portion of the second device structure is etched to define a bit line contact region, the bit line contact region extending from an upper surface of the second device structure to a lower surface of the second device structure. The second film of the second device structure is etched to define an under-cut space between the first and second films. A semiconductor layer is formed within the under-cut space and the bit line contact region. The third film of the second device structure is etched or removed to define a recess, the recess defining a gate region. A gate structure is formed at least partly within the recess.

Abstract: According to one exemplary embodiment, a method of fabricating a bitline in a memory array includes forming a trench in a substrate, where the trench has sidewalls and a bottom surface. The method further includes performing a selective epitaxial process to partially fill the trench with selective epitaxially grown silicon, where the selective epitaxially grown silicon is situated on the sidewalls and bottom surface of the trench. The selective epitaxially grown silicon is doped in the selective epitaxial process. The method further includes performing a silicon reflow process to cause the selective epitaxially silicon to be redistributed in the trench. The method further includes performing a number of selective epitaxial process/silicon reflow process cycles to substantially fill the trench with the selective epitaxially grown silicon. The method further includes extending a top surface of the selective epitaxially grown silicon in the trench above an ONO stack to form the bitline.

Abstract: A method of fabricating a semiconductor device using selective epitaxial growth (SEG) is disclosed. The method comprises; forming a seed window exposing a portion of a substrate through an interlayer insulating layer, growing a single crystal silicon SEG layer in the seed window using the exposed portion of the substrate as a seed, depositing an amorphous silicon layer on the interlayer insulating layer and in contact with the SEG layer, and performing an annealing process on the amorphous silicon layer over an annealing interval, and during the annealing interval applying microwave energy to the amorphous silicon layer.

Abstract: Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: A method of fabricating a semiconductor device uses selective epitaxial growth (SEG), by which leakage current generation is minimized using lateral SEG growth in case a contact intrudes a shallow track isolation feature. The method includes steps of forming a sidewall spacer on a gate, selectively growing an epitaxial layer in a lateral direction relative to the sidewall spacer and the gate, and forming a contact on the epitaxial layer.

Abstract: A method of fabricating a transistor of a semiconductor device comprises forming first and second trenches for gates in a substrate; forming a liner layer on innerwalls of the first and second trenches; forming first and second epitaxial gate electrodes by performing an epitaxial growth on the first and second trenches comprising the liner layers therein; forming isolation structures in the substrate, wherein the isolation structures contact the first and second epitaxial gate electrodes, respectively; forming a gate insulation layer and a gate electrode over a region of the substrate between the first and second epitaxial gate electrodes; and forming source and drain regions in the substrate disposed in respective edge regions of the gate electrode and overlapping the gate electrode.

Abstract: Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

Abstract: Methods for fabricating a shallow trench isolation (STI) of a semiconductor device are disclosed. A disclosed method includes: forming a trench on a semiconductor substrate, forming an oxide layer on the semiconductor substrate and the trench, forming a photoresist pattern on the oxide layer exposing the oxide layer on a bottom surface of the trench, forming STI films on sidewalls of the trench by etching the exposed oxide layer using the photoresist pattern as an etch protection layer, removing the photoresist pattern, developing an epitaxial layer between the STI, and planarizing the epitaxial layer and the oxide layer.

Abstract: The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of isolation trenches within semiconductive silicon-comprising material. The isolation trenches comprise sidewalls comprising exposed semiconductive silicon-comprising material. An epitaxial silicon-comprising layer is grown from the exposed semiconductive silicon-comprising material sidewalls within the isolation trenches. Electrically insulative trench isolation material is formed within the isolation trenches over the epitaxially-grown silicon-comprising layer. Other aspects and implementations are contemplated.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: A method for forming device isolation film of semiconductor device is provided, the method including forming a pad oxide film, a pad nitride film, and an oxide film for device isolation on a semiconductor substrate, etching a predetermined region of the oxide film for device isolation, the pad nitride film, the pad oxide film, and the semiconductor substrate to form a trench, forming a SEG silicon layer in the trench to form an active region, and forming a gap-fill insulating film on the resulting structure having a gap between sidewalls of the trench and the SEG silicon layer.

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract: Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.

Abstract: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line.