Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first electrode located on the semiconductor layer; a second electrode located on the semiconductor layer; a third electrode located on the semiconductor layer between the first electrode and the second electrode, and separated from them; a first semiconductor region that is located in the semiconductor layer and is of a second conductivity type; a first cathode region of the first conductivity type; a first anode region of the second conductivity type; a second cathode region of the first conductivity type; a second anode region of the second conductivity type; a third anode region of the second conductivity type; a third cathode region of the first conductivity type; a second semiconductor region of the second conductivity type; a fourth anode region of the second conductivity type; and a fourth cathode region of the first conductivity type.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction.

Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

Abstract: A semiconductor device includes: a metal-oxide semiconductor (MOS) transistor on a substrate; a deep trench isolation structure in the substrate and around the MOS transistor; and a trap rich isolation structure in the substrate and surrounding the deep trench isolation structure. Preferably, the deep trench isolation structure includes a liner in the substrate and an insulating layer on the liner, in which the top surfaces of the liner and the insulating layer are coplanar. The trap rich isolation structure is made of undoped polysilicon and the trap rich isolation structure includes a ring surrounding the deep trench isolation structure according to a top view.

Abstract: Exemplary methods of forming a semiconductor structure may include forming a liner along sidewalls of a trench defined from a first surface of a semiconductor substrate. The liner may extend along the first surface of the semiconductor substrate. The methods may include filling the trench with a dielectric material. The methods may include removing the dielectric material and the liner from the first surface of the semiconductor substrate. The methods may include forming a layer of the liner across the first surface of the semiconductor substrate and the trench defined within the semiconductor substrate.

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

Abstract: Method for gap fill includes performing in order the following: (a) performing, consecutively, a first plurality of cycles of an atomic layer deposition process on a substrate; (b) purging process gases from the atomic layer deposition process; (c) performing a first plasma treatment on the substrate by introducing a fluorine plasma in the process chamber; (d) purging process gases from the plasma treatment; (e) repeating, in order, operations (a) through (d) until a predefined plurality of cycles has been performed; (f) performing, consecutively, a second plurality of cycles of the atomic layer deposition process on the substrate; (g) purging process gases from the atomic layer deposition process; (h) performing a second plasma treatment on the substrate by introducing a fluorine plasma in the process chamber; (i) purging process gases from the plasma treatment; (j) repeating, in order, operations (f) through (i) until a predefined plurality of cycles has been performed.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a first mandrel layer and a second mandrel layer on the dielectric layer and patterning the first mandrel layer and the second mandrel layer to form respective first and second patterns in the first and second mandrel layers. The first pattern includes a first line segment and a first wing segment. The first wing segment is filled with a first spacer material to form a first spacer. The method further includes removing exposed portions of the first and second mandrel layers, transferring an image of the first and second patterns, patterning the dielectric layer and depositing a metal into the patterned dielectric layer to form a metallic interconnect structure. The metallic interconnect structure includes first and second metallic lines with the second metallic line having a line break corresponding to the first spacer.

Abstract: A three-dimensional semiconductor device includes: a common source line passing between a first channel structure and a second channel structure and between a first dummy channel structure and a second dummy channel structure, in which a distance in a first direction between the common source line and the first channel structure is equal to a distance in the first direction between the common source line and the second channel structure, and a distance in the first direction between the common source line and the first dummy channel structure is different from a distance in the first direction between the common source line and the second dummy channel structure.

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

Abstract: A semiconductor device includes a substrate comprising a plurality of active regions extending in a first direction and a device isolation region electrically isolating the plurality of active regions, a gate trench extending across the plurality of active regions and the device isolation region, a gate structure extending in the gate trench of each of and along opposite sidewalls of the plurality of active regions, a gate dielectric film formed between the gate trench and the gate structure in each of the plurality of active regions, and an insulating barrier film provided in each of the plurality of active regions under the gate trench spaced apart from a lower surface of the gate trench and extending in an extension direction of the gate trench.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack, channel holes passing through the stack, dummy channel holes passing through the stack and disposed between the channel holes, a slit passing through the stack and the dummy channel holes.

Abstract: A method for performing gap fill of a feature on a substrate includes the following operations: (a) moving the substrate into a process chamber; (b) performing a plurality of cycles of an ALD process; (c) purging process gases from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine-containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber; (e) purging process gases from the plasma treatment from the process chamber; (f) repeating operations (b) through (e) until a predefined number of cycles has been performed.

Abstract: A planarization process includes the following steps. A first dielectric layer and a second dielectric layer are sequentially formed to conformally cover a pattern in a cell area and a substrate in the cell area and an isolation area, thereby the first dielectric layer and the second dielectric layer having a dishing in the isolation area. A dummy material is formed in the dishing and exposes a part of the second dielectric layer right above the pattern. A first removing process is performed to remove the exposed part of the second dielectric layer. The dummy material is removed. A second removing process is performed to remove an exposed part of the first dielectric layer by using the second dielectric layer as an etch stop layer. A third removing process is performed to remove the second dielectric layer and the first dielectric layer.

Abstract: A semiconductor device can include a semiconductor substrate having a memory cell region and a pad region that is adjacent to the memory cell region, the pad region can include a first pad region, a second pad region between the memory cell region and the first pad region, and a buffer region that is between the first and second pad regions. A separation source structure can include a first portion and a second portion that are parallel to each other in a plan view of the semiconductor device. A first source structure and a second source structure can be disposed between the first and second portions of the separation source structure, where the first and second source structures can have end portions that oppose each other, the first source structure being disposed in the first pad region, and the second source structure being disposed in the second pad region.

Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.

Abstract: A three-dimensional semiconductor device is disclosed. The device may include an electrode structure that can include a plurality of electrodes that are stacked on a substrate and extend in a first direction. Vertical structures can penetrate the electrode structure to provide a plurality of columns spaced apart from each other in a second direction crossing the first direction. The plurality of columns can include first and second edge columns located adjacent to respective opposite edges of the electrode structure, and the plurality of columns can include a center column located between the first and second edge columns. Distances between adjacent ones of the plurality of columns can decrease in a direction from the first and second edge columns toward the center column.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

Abstract: A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

Abstract: A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a plurality of conductive members containing a metal and provided on the substrate, a stacked body provided in each region between the conductive members, a semiconductor pillar piercing the stacked body, a memory film and internal stress films. The plurality of conductive members extend in a first direction and are separated from each other in a second direction. The internal stress films also extend in the first direction and are separated from each other in the second direction. The first direction and the second direction are parallel to an upper surface of the substrate and intersect each other. The internal stress films contain material having internal stress having the reverse polarity of internal stress of the metal.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.

Abstract: A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.

Abstract: The present invention discloses a LTPS TFT pixel unit and a manufacture method thereof. The method comprises steps of: providing a substrate and forming a buffer layer on the substrate; forming a semiconductor pattern layer and a first insulative layer on the buffer layer, and the semiconductor pattern layer and the first insulative layer are located in the same layer and heights of the semiconductor pattern layer and the first insulative layer are the same. With the aforesaid arrangement, the present invention can reduce the side effect of the LTPS TFT pixel unit and promote the electrical property thereof.

Abstract: The disclosed technology covers messaging systems and methods, and computer program products embodying such systems and methods. A computer program product may include a computer-readable storage medium with instructions executable by one or more processors to perform a method. The method may include receiving, at a message server configured to receive a plurality of messages for a plurality of computing devices, a first message intended for a first user profile. The first user profile and one or more other user profiles may exist on a single computing device. The method may also include receiving a first status update from the first computing device indicating that the first user profile is stopped or non-active, and postponing delivery of the first message to the first computing device, based on the first user profile being stopped or non-active. These and other aspects of messaging systems, methods, and computer program products are disclosed herein.

Abstract: A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer.

Abstract: A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one selection line is stacked on top of the word lines and includes a second conductive layer. At least one gate line is formed in a peripheral region of the substrate and includes the second conductive layer.

Abstract: A lateral avalanche photodiode device comprises a semiconductor substrate (1) having a trench (4) with side walls (5) extending from a main surface (2) to a rear surface (3). A first doped region (11) is present at the side walls of the trench, and a second doped region (12) is arranged at a distance from the first doped region. A third doped region (13) is located adjacent to the first doped region, extends through the substrate from the main surface to the rear surface, and is arranged between the first doped region and the second doped region. The third doped region (13) is the avalanche multiplication region of the photodiode structure. The second doped region and the third doped region have a first type of conductivity, and the first doped region has a second type of conductivity which is opposite to the first type of conductivity. The region of the substrate that is between the first doped region and the second doped region is of the first type of conductivity.

Abstract: A semiconductor device includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device also includes a first epitaxial fin and a second epitaxial fin over the semiconductor substrate, and the first epitaxial fin and the second epitaxial fin protrude from the isolation structure. The semiconductor device further includes a gate stack over and traversing the first epitaxial fin and the second epitaxial fin. In addition, the semiconductor device includes a recess extending from a top surface of the isolation structure. The recess is between the first epitaxial fin and the second epitaxial fin.

Abstract: Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

Abstract: The embodiments described above provide mechanisms of forming contact structures with low resistance. A strained material stack with multiple sub-layers is used to lower the Schottky barrier height (SBH) of the conductive layers underneath the contact structures. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer, and a SiGe top layer. The GeB layer moves the Schottky barrier to an interface between GeB and a metal germanide, which greatly reduces the Schottky barrier height (SBH). The lower SBH, the Ge in the SiGe top layer forms metal germanide and high B concentration in the GeB layer help to reduce the resistance of the conductive layers underneath the contact structures.

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract: Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract: Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

Abstract: Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.

Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Abstract: A semiconductor diode includes a semiconductor body and trench structures extending from a surface of the semiconductor body into the semiconductor body. The semiconductor body includes a doped layer of a first conductivity type and a doped zone of a second conductivity type opposite to the first conductivity type. The doped zone is formed between the doped layer and a first surface of the semiconductor body. The trench structures are arranged between electrically connected portions of the semiconductor body. The trench structures do not include conductive structures that are both electrically insulated from the semiconductor body and electrically connected with another structure outside the trench structures.

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices.

Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

Abstract: According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.

Abstract: A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source/drain region of the FinFET, and etching through the exposed isolation layer to expose the semiconductive material of the source/drain region in the two areas; forming a recess in each of the source/drain region from the exposed semiconductive material; selectively epitaxially growing another semiconductive material in the recesses to increase the source/drain strain; and removing the rest of the isolation layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench on a semiconductor layer of a first conductive type; forming a first insulation film which covers an inner surface of the trench; forming a first conductive material on the first insulation film; etching the first conductive material and then the first insulation film such that the semiconductor layer is exposed on an inner surface of an upper portion of the trench and an upper end portion of the first conductive material is positioned above an upper end portion of the first insulation film; re-etching the first conductive material; forming a second insulation film which covers the semiconductor layer exposed on the inner surface of the upper portion of the trench and the first conductive material; and forming a second conductive material on the first insulation film and the second insulation film.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes dry-etching a member containing silicon in a first pressure range equal to or more than a first pressure or in a second pressure range equal to or less than a second pressure, wherein the first pressure is obtained by multiplying a saturated pressure by 0.85, the saturated pressure is defined as a pressure under which an etching rate is one of a maximum value or a value obtained by multiplying the maximum value by a predetermined coefficient, and the etching rate is a half value of the maximum value under the second pressure.

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.