Abstract: In one aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, comprising: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract: A method for fabricating an isolation layer in a semiconductor device is disclosed. The disclosed method comprises steps of: forming a trench on a semiconductor substrate; forming a flowing insulating layer within the trench; making the insulating layer precise; and forming a precise insulating layer over an upper surface of the whole structure on which the flowing insulating layer is formed. According to the method of fabricating an isolation layer in a semiconductor device, occurrence of fine pores at adjacent active regions of sidewalls in a trench can be prevented.

Abstract: A method of forming a trench isolation in a substrate includes the steps of forming a trench groove in a substrate, forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, where the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove, and forming a second electrically insulating layer over the first electrically insulating layer. The second electrically insulating layer fills the first hollow and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove. The second electrically insulating layer has a second surface migration smaller than the first surface migration.

Abstract: The present invention provides a method of forming a trench isolation in a substrate, which comprises the steps of: forming a trench groove in a substrate; forming a first electrically insulating layer which fills the trench groove and extends over an upper surface of the substrate, wherein the first electrically insulating layer has a first surface migration, and an upper surface of the first electrically insulating layer has a first hollow positioned over the trench groove; and forming a second electrically insulating layer over the first electrically insulating layer, wherein the second electrically insulating layer fills the first hollow, and an upper surface of the second electrically insulating layer has a second hollow positioned over the trench groove, and the second electrically insulating layer has a second surface migration smaller than the first surface migration.

Abstract: A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.

Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; curing the layer of spin-on glass material by exposing the spin-on glass material to electron beam radiation at a first temperature for a first period and subsequently exposing the spin-on glass material to an electron beam at a second temperature for a second period, where the second temperature is greater than the first temperature. The method concludes by depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.

Abstract: Methods for making thin silicon layers suspended over recesses in glass wafers or substrates are disclosed. The suspended silicon wafers can be thin and flat, and can be made using methods not requiring heavy doping or wet chemical etching of the silicon. Devices suitable for production using methods according to the invention include tuning forks, combs, beams, inertial devices, and gyroscopes. One embodiment of the present invention includes providing a thin silicon wafer, and a glass wafer or substrate. Recesses are formed in one surface of the glass wafer, and electrodes are formed in the recesses. The silicon wafer is then bonded to the glass wafer over the recesses. The silicon wafer is them etched to impart the desired suspended or silicon wafer structure. In another embodiment of the present invention, the silicon wafer has a patterned metal layer. The silicon wafer is bonded to the glass wafer, with the patterned metal layer positioned adjacent the recesses in the glass wafer.

Abstract: Semiconductor devices and methods for manufacturing the same in which deterioration of the electrical characteristic is suppressed are described. One method for manufacturing a semiconductor device includes the steps of: forming a first polysilicon layer 32 on a gate dielectric layer 20; forming a silicon nitride layer 92 on the first polysilicon layer 32; forming a second polysilicon layer 94 on the silicon nitride layer 92; forming sidewall spacers; forming an insulation layer 60 that covers the second polysilicon layer 94; planarizing the insulation layer 60 until an upper surface of the second polysilicon layer 94 is exposed; removing the second polysilicon layer 94; removing the silicon nitride layer 92 to form a recessed section 80; and filling a metal layer 34 in the recessed section 80 to form a gate electrode 30 that includes at least the first polysilicon layer 32 and the metal layer 34.

Abstract: A process for forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of the shallow trench shape used to accommodate the STI structure, has been developed. After defining a shallow trench shape featuring rounded corners, a group of thin insulator liner layers, each comprised of either silicon oxide or silicon nitride, is deposited on the exposed surfaces of the shallow trench shape via atomic layer depositing (ALD), procedures. A high density plasma procedure is used for deposition of silicon oxide, filling the shallow trench shape which is lined with the group of thin insulator liner layers. The silicon nitride component of the insulator liner layers, prevents diffusion or segregation of P type dopants from an adjacent P well region to the silicon oxide of the STI structure.

Abstract: In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4-y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4-y if present is converted to (CH3)xSiO2-x. Next, a layer of an electrically insulative material is formed to fill the trench.

Abstract: Solid material gasification method comprises a solution preparation step wherein a first solid material is dissolved in a solvent to prepare a gasification solution, a solvent removal step wherein a second solid material is separated by removing the solvent used to prepare the gasification solution from that solution, and a solid sublimation step wherein the second solid material is gasified by sublimation.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: This invention relates to a method of filling at least one trench or other opening in a substrate including depositing a dielectric material into the trench or opening and annealing the deposited material during or after the application of pressure. The process may be stepwise and the anneal step may at least include or be followed by the exposure of the substrate to an H2 plasma.

Abstract: In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4−y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4−y if present is converted to (CH3)xSiO2−x. Next, a layer of an electrically insulative material is formed to fill the trench.

Abstract: A first silicon-containing reaction gas and an oxygen precursor representing a further reaction gas are fed to the reaction chamber and a high-density plasma, preferably above 1016 ions/m3, is produced. Through at least partial substitution of the precursor O2 that is normally used, H2O2 and/or H2O are fed to the reaction chamber in order to further reduce the sputtering effects due to O2 ions during the deposition, which lead to undesirable redepositions of the SiO2 on side walls of the depression.

Abstract: STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings.

Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: A process for forming insulator filled, shallow trench isolation (STI), regions in a semiconductor substrate, featuring a disposable polysilicon stop layer used to allow uniform insulator fill to be obtained, independent of shallow trench width, has been developed. The process features filling shallow trench shapes with a first high density plasma (HDP), deposited silicon oxide layer, followed by the deposition of the thin polysilicon stop layer, and a second HDP silicon oxide layer. After a planarizing chemical mechanical polishing procedure residual regions of the second HDP silicon oxide, still remaining in regions overlying the insulator filled shallow trench shapes, are selectively removed using the thin polysilicon layer as a stop layer. The polysilicon layer is then thermally oxidized. The thickness of the polysilicon layer can be varied such that the resultant polysilicon oxide layer serves to alleviate the possible oxide loss in the STI regions during subsequent clean processes.

Abstract: The present invention provides a method of rounding the corner of the shallow trench isolation region, comprising the steps of: etching silicon substrate using a patterned mask layer and a pad oxide layer as an etch mask to form a trench in the silicon substrate, then removing part of the pad oxide layer, forming silicon dioxide on the surface of the silicon substrate in the trench, then removing part of the pad oxide layer and the silicon dioxide on the surface of the silicon substrate in the trench, repeating the step of oxidizing the surface of the silicon substrate and removing part of the pad oxide layer and silicon dioxide to round the corner of the trench, then performing the subsequent steps to form the shallow trench isolation region.

Abstract: In order to isolate a plurality of MOS and bipolar devices provided on the same chip, a plurality of first and second trenches are provided on a semiconductor substrate. Each of the first trenches is filled with silicon oxide containing no impurity and is used to isolate the MOS devices. On the other hand, the second trenches are formed within the first trenches. Each second trench is filled silicon oxide containing phosphorous and boron and is used to isolate the bipolar devices. The inner surface of each second trench is coated with a silicon nitride film for preventing boron (or phosphorous) from being diffused into the surrounding region.

Abstract: A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer, used for planarization of various width, silicon oxide filled, STI regions, has been developed. After completely filling all STI shapes with a high density plasma (HDP), silicon oxide layer, resulting in a non-planar, HDP silicon oxide top surface topography, a BPSG layer is deposited. An anneal procedure is then performed resulting in a planar top surface topography of the reflowed BPSG layer. A chemical mechanical polishing procedure is next employed to remove the planar, reflowed BPSG layer, and portions of the underlying HDP silicon oxide, from the top surface of a silicon nitride stop layer, resulting in a planar top surface topography for all silicon oxide filled, insulator regions.

Abstract: The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench—trench short circuiting.

Abstract: An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O2/CF4 chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.

Abstract: In fabrication of a semiconductor device, firstly an isolation trench is formed on a substrate to isolate a plurality of semiconductor elements, and then a thermal oxide film is formed on a sidewall of the trench, whereupon a silicon oxide film is formed on the substrate by chemical vapor deposition. Finally the entire substrate is annealed in a high-pressure ambient.

Abstract: A method for eliminating the divots and seams present in a shallow trench isolation region of a semiconductor device is provided which improves the corner Vt control. The method disclosed herein applies spun-on glass to a surface of a semiconductor device and then anneals the applied spun-on glass prior to stripping the sacrificial oxide layer present on the semiconductor device. The annealing step employed in the present invention densifies the spun-on glass so that its etch rate approximates that of the sacrificial oxide layer.

Abstract: A method used during the formation of a semiconductor device comprises the steps of providing a semiconductor substrate assembly having at least one recess therein then forming a first dielectric layer within the recess. The first dielectric layer is formed with a thickness that will prevent the first dielectric layer from impinging on itself in the recess, for example with a thickness less than half a width of the trench. The dielectric layer is then annealed in a manner that will increase the volume of the first dielectric layer. After annealing the first dielectric layer, a second dielectric layer is formed over the first dielectric layer within the recess. The second dielectric layer is formed with a sufficient thickness such that it impinges on itself in the recess. The second dielectric layer is then annealed.

Abstract: A semiconductor device includes an n-channel MOSFET isolated by an element isolation region of STI structure. A silicon nitride (SiN) region is formed in an Si substrate near the interface between the element isolation region and the Si substrate. The silicon nitride region is formed by ion-implanting nitrogen (N) into the Si substrate. The silicon nitride region is acts as a barrier layer for preventing substrate impurity of the n-channel MOSFET (impurity contained in the channel region) from being thermally diffused into the element isolation region. The silicon nitride region is distributed from the main surface of the Si substrate in the end portion of the element isolation region to a region deeper than the substrate depth which determines the threshold voltage of the MOSFET.

Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract: Disposable spacers of an organic material or a low-temperature inorganic material provide advantages in the formation of STI trenches and contact holes and additional freedom in line spacing.

Abstract: This invention is directed to a method for reforming an undercoating surface prior to the formation of a film by the CVD technique using a reaction gas containing an ozone-containing gas having ozone contained in oxygen and TEOS. It effects the reform of the surface by forming an undercoating insulating film on a substrate prior to the formation of film and exposing the surface of the undercoating insulating film to plasma gas.

Abstract: The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: A method for forming a BPSG film from a two-step deposition process and related apparatus and devices. A conformal layer of BPSG is deposited on a substrate. A more stable layer of BPSG is deposited at a higher deposition rate over the conformal layer. The method is suitable for filling trenches at least as narrow as 0.06 microns with aspect ratios of at least 5.5:1.

Abstract: In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an uppermost surface. A material is formed beside the elevational step. The material extends to above the elevational step uppermost surface and lower and upper layers. The lower layer polishes at slower rate than the upper layer under common polishing conditions. The lower layer joins the upper layer at an interface. The material is polished down to about the elevational level of the elevational step uppermost surface utilizing the common polishing conditions. In another aspect, the invention encompasses a method of forming an isolation region. A substrate is provided. The substrate has an opening extending therein and a surface proximate the opening. A material is formed within the opening. The material extends to above the substrate surface, and comprises a lower layer and an upper layer.

Abstract: A method of fabricating a shallow trench isolation (STI). The method forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer in the vicinity of an interface between a STI and a substrate. Then, a planarization process is performed, and the spin-on glass layer is annealed into an oxide layer with good thermal stability.

Abstract: The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer, backfilling with oxide, and polishing by chemical-mechanical polishing (CMP) to produce a planar, trench isolated, wafer. To ensure planarity of the wafer after CMP, and avoid dishing of the field oxide, a dual silicon nitride polish stop layer is used. The first polish stop layer is applied selectively to protect the active device regions, and the second polish stop layer is applied selectively to protect the field oxide regions.

Abstract: A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric layer is removed so as to expose the dielectric capped bond pad and the dielectric capped interconnect. A third dielectric layer is then formed over the exposed dielectric capped bond pad and the exposed dielectric capped interconnect and over the second dielectric.

Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.

Abstract: A recess-free buffer layer is formed on a semiconductor substrate having island structures formed thereon. A first buffer layer is formed over the substrate and the island structures. A first reflow process is then performed for reflowing the first buffer layer into spaces between the island structures. A portion of the first buffer layer located outside the spaces is removed. A second buffer layer is formed over the first buffer layer and the island structures. The method can further include a step of performing a second thermal soft-bake process to the second buffer layer. The second buffer layer can also be patterned after the soft-bake process.

Abstract: A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

Abstract: A method to reduce to reduce DRAM capacitor STI junction leakage current. A Shallow Trench Isolation opening is formed, within this opening Field Oxide is deposited. The top surface of the FOX is etched down and a second layer of oxide is deposited over the FOX and the adjacent active regions. This second layer of oxide is etched bringing the top surface down to below the level of the top surface of the surrounding active areas but leaving spacers where the top surface of the FOX intersects with the active areas.

Abstract: A method for forming trench isolation in the silicon substrate is disclosed. This method allows for an improved bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After a trench is formed, sidewall silicon dioxide is grown on the sidewall of the trench by a first oxidation process. Then, PE-TEOS is deposited on the silicon substrate and the sidewall of the trench. The PE-TEOS layer around the entrance of the trench is then etched back using argon gas. The second oxidation process or the first annealing proceeds to enhance the bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After the second oxidation process or the annealing, the trench is filled with O.sub.3 -TEOS, and then PE-TEOS is deposited over the O.sub.3 -TEOS layer. Finally, the second annealing process follows.

Abstract: A shallow trench isolation structure is formed by providing a pad layer and a silicon nitride polish stop layer on a surface of a P-type silicon substrate. The silicon nitride polish stop layer and the pad oxide layer are patterned to define openings corresponding to portions of the substrate that will be etched to form trenches. Trenches are defined in the P-type silicon substrate by anisotropic etching. A boron doped oxide or glass is deposited along the walls and floor of the trench. An undoped TEOS oxide is provided over the doped oxide or glass to complete filling of the trench. The device is subjected to a high temperature reflow process, causing the dielectric materials to flow, partially planarizing the device and causing the boron of the first layer to diffuse into the walls and floor of the trench. Chemical mechanical polishing removes excess portions of the dielectric layers.

Abstract: A process for creating an insulator filled, shallow trench isolation region, in a semiconductor substrate, has been developed. The process features the use of a high temperature hydrogen anneal, performed after an anisotropic RIE procedure, used to create the shallow trench shape, in the semiconductor substrate. The high temperature hydrogen anneal procedure repairs defects in the semiconductor substrate, created by the shallow trench, RIE procedure, and also creates a denuded zone, at or near the shallow trench shape, exposed silicon surface. The defect free denuded zone allows the formation of a uniform insulator trench liner to be realized, and also allows a minimum of junction leakage to occur at the region in which a source/drain-substrate junction, is butted against the side of the insulator filled, shallow trench.

Abstract: An insulator (5) is a frame element for covering the outer edges of the active region (3), and protrudes upwardly above the surface of a semiconductor substrate (1) to constitute part of the inner walls of a trench (9) filled with an insulating film (2). A gate oxide film (21) is formed on the surface of the active region (3) adjacent the center thereof. The etching rate of the insulator (5) is lower than that of the insulating film (2). The insulator (5) prevents the sidewalls of the insulating film (2) from being etched away to suppress the formation of the depression positioned lower than the surface of the semiconductor substrate (1), thereby to alleviate influences upon an electric field adjacent the outer edges of the active region (3).