Multiple Insulative Layers In Groove Patents (Class 438/435)
  • Patent number: 10607832
    Abstract: Disclosed are method and apparatus for forming a thin layer. The method for forming the thin layer comprises providing a substrate including patterns, forming a bonding layer on the substrate covering an inner surface of a gap between the patterns, forming a preliminary layer on the bonding layer filling the gap; and thermally treating the preliminary layer to form the thin layer. The bonding layer is a self-assembled monomer layer formed using an organosilane monomer. The preliminary layer is formed from a flowable composition comprising polysilane.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyeong Lee, Soonwook Jung, Bongjin Kuh, Pyung Moon, Sukjin Chung
  • Patent number: 10566326
    Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae Young Kwak, Ki Byung Park, Kyoung Hwan Yeo, Seung Jae Lee, Kyung Yub Jeon, Seung Seok Ha, Sang Jin Hyun
  • Patent number: 10559473
    Abstract: A semiconductor process for improving loading effects in planarization is provided including steps of forming multiple first protruding patterns on a first region and a second region of a substrate, wherein the pattern density of the first protruding patterns in the first region is larger than the one in the second region, forming a first dielectric layer on the substrate and the first protruding patterns, wherein the first dielectric layer includes multiple second protruding patterns corresponding to the first protruding patterns below, forming a second dielectric layer on the first dielectric layer, performing a first planarization process to remove parts of the second dielectric layer, so that the top surface of the second protruding patterns are exposed, performing an etch process to remove the second protruding patterns of the first dielectric layer, removing the remaining second dielectric layer, and performing another planarization process to the first dielectric layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 11, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10529576
    Abstract: Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of a die included in each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: January 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Eiji Kurose
  • Patent number: 10510560
    Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 17, 2019
    Assignees: Nanyang Technological University, Massachusetts Institute of Technology
    Inventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
  • Patent number: 10373683
    Abstract: A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 10115796
    Abstract: A method of fabricating a semiconductor device includes forming a first, a second and a third trenches extending through a dielectric layer over a substrate, forming a material layer in the first, the second and the third trenches, forming a sacrificial layer to fully fill in the remaining first and the second trenches, recessing the sacrificial layer in the first trench and the second trench, recessing the material layer in the first trench and in the second trench. After recessing the material layer, a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the first trench and a top surface of the remaining material layer is co-planar with a top surface of the remaining sacrificial layer in the second trench. The method also includes removing the remaining sacrificial layer in the first trench and the second trench.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Dah Chen, Han-Wei Wu, Ming-Feng Shieh
  • Patent number: 10068997
    Abstract: A thin Ge layer is formed between an SiGe intrinsic base and single-crystal Si extrinsic base structures to greatly simplify the fabrication of raised-base SiGe heterojunction bipolar transistors (HBTs). The fabrication process includes sequentially depositing the SiGe intrinsic base, the Ge, and Si extrinsic base layers as single-crystal structures over a patterned silicon wafer while the wafer is maintained inside a reaction chamber. The Ge layer subsequently functions as an etch stop, and protects the crystallinity of the underlying SiGe intrinsic base material during subsequent dry etching of the Si extrinsic base layer, which is performed to generate an emitter window. A wet etch then removes residual Ge from the emitter window to expose a contact portion of the SiGe layer surface without damage. A polysilicon emitter structure is formed in the emitter window, and then salicide is formed over the base stacks to encapsulate the SiGe and Ge structures.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 4, 2018
    Assignee: Newport Fab, LLC
    Inventor: Edward J. Preisler
  • Patent number: 10062561
    Abstract: Methods are described for reducing the wet etch rate of dielectric films formed on a patterned substrate by flowing the material into gaps during deposition. Films deposited in this manner may initially exhibit elevated wet etch rates. The dielectric films are treated by exposing the patterned substrate to a high pressure of water vapor in the gas phase. The treatment may reduce the wet etch rate of the dielectric films, especially the gapfill portion of the dielectric film. Scanning electron microscopy has confirmed that the quantity and/or size of pores is reduced or eliminated by the procedures described herein. The treatment has also been found to reduce the etch rate, e.g., at the bottom of gaps filled with the dielectric film.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 28, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kurtis S Leschkies, Keith Tatseun Wong, Steven Verhaverbeke
  • Patent number: 10043753
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Huy Cao, Zhiguo Sun, Joseph F. Shepard, Jr., Moosung M. Chae
  • Patent number: 9929233
    Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Zailong Bian, Janos Fucsko
  • Patent number: 9812319
    Abstract: A method for forming a film filled in a trench of a substrate without seam or void includes: depositing a conformal SiN film in a trench of a substrate placed in a reaction space, using a halide compound as a precursor, until the trench is filled with the conformal SiN film serving as a filled film which has a seam and/or void; and then oxidizing the filled film without deposition of film to make the filled film expand until the seam and/or void of the filled film are/is diminished.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 7, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Hideaki Fukuda
  • Patent number: 9721828
    Abstract: A method of filling STI trenches with dielectric with reduced particle formation. A method of depositing unbiased STI oxide on an integrated circuit during STI trench fill that reduces STI defects during STI CMP.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andrew Brian Nelson, Richard A. Stice, Joe Tran
  • Patent number: 9633839
    Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 25, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Weimin Zeng, Thanh X. Nguyen, Yana Cheng, Yong Cao, Daniel Lee Diehl, Srinivas Guggilla, Rongjun Wang, Xianmin Tang
  • Patent number: 9508715
    Abstract: The present invention provides a semiconductor structure including a substrate, having a recess disposed thereon. Two first protruding portions are disposed on two sides of the recess respectively, an epitaxial layer is disposed in the recess, and an insulating layer is disposed on the substrate. A top portion of the first protruding portion is higher than a top surface of the insulating layer.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: November 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Chien-Ting Lin, Shih-Hung Tsai, Ssu-I Fu, Hon-Huei Liu, Jyh-Shyang Jenq
  • Patent number: 9472416
    Abstract: Methods for surface interface engineering in semiconductor fabrication are provided herein. In some embodiments, a method of processing a substrate disposed atop a substrate support in a processing volume of a processing chamber includes: generating an ion species from an inductively coupled plasma formed within the processing volume of the processing chamber from a first process gas; exposing a first layer of the substrate to the ion species to form an ammonium fluoride (NH4F) film atop the first layer, wherein the first layer comprises silicon oxide; and heating the substrate to a second temperature at which the ammonium fluoride film reacts with the first layer to selectively etch the silicon oxide.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: October 18, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jim Zhongyi He, Ping Han Hsieh, Melitta Manyin Hon, Chun Yan, Xuefeng Hua
  • Patent number: 9366814
    Abstract: The application relates to methods of manufacture of improved optical containment structures. The invention relates to arrays of zero-mode waveguide structures comprising nanoscale apertures having non-reflective coatings on their walls. The methods provide for selectively coating the walls of the zero mode waveguides, allowing for selective functionalization of the bases.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: June 14, 2016
    Assignee: Pacific Biosciences of California, Inc.
    Inventors: Jeremy Gray, Ronald L. Cicero, Annette Grot
  • Patent number: 9356025
    Abstract: The present invention relates to enhancing MOSFET performance with the corner stresses of STI.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 31, 2016
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 9299956
    Abstract: A method is disclosed for forming leak-free coatings on polymeric or other surfaces that provide optical functions or protect underlying layers from exposure to oxygen and water vapor and do not crack or peel in outdoor environments. This method may include both cleaning and surface modification steps preceding coating. The combined method greatly reduces defects in any barrier layer and provides weatherability of coatings. Specific commercial applications that benefit from this include manufacturing of photovoltaic devices or organic light emitting diode (OLED) devices including lighting and displays.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: March 29, 2016
    Assignee: Aixtron, Inc.
    Inventors: Stephen E. Savas, Allan Wiesnoski, Hood Chatham, Carl Galewski
  • Patent number: 9252052
    Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: February 2, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMicroelectronics, Inc., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet
  • Patent number: 9240458
    Abstract: Provided is a fabricating method of a nonvolatile memory. The fabricating method includes forming a plurality of gates extending in a first direction on a substrate to be adjacent to each other, forming a gap-fill layer filling at least a portion of a space between the plurality of gates, forming a supporter pattern supporting the plurality of gates on the plurality of gates and the gap-fill layer, and forming an air gap in the space between the plurality of gates by removing the gap-fill layer.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seok Na, Ji-Hwon Lee, Joong-Shik Shin, Chang-Sun Lee
  • Patent number: 9209243
    Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yi Chuang, Ta-Hsiang Kung, Hsing-Jui Lee, Ming-Te Chen
  • Patent number: 9196728
    Abstract: An integrated circuit on a rotated substrate with an LDMOS transistor. A method of enhancing the CHC performance of an LDMOS transistor by growing a second STI liner oxide. A method of enhancing the CHC performance of an LDMOS transistor building the LDMOS transistor on a rotated substrate and growing a second STI liner oxide.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: November 24, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Seetharaman Sridhar
  • Patent number: 9184089
    Abstract: Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang
  • Patent number: 9159604
    Abstract: A method includes forming a recess in a substrate and filling a dielectric layer in the recess. The method further includes forming a capping layer over the substrate and the dielectric layer. A top portion of the capping layer is then removed, while leaving a bottom portion of the capping layer over the dielectric layer. A gate structure is then formed over the remaining capping layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 9147596
    Abstract: A method for forming shallow trench isolation (STI) structures includes using a hard mask, such as silicon nitride, in shallow trench etching and also as a polishing stop layer in planarizing the dielectric that fills the trenches. After the shallow trench is filled with the dielectric material and planarized, a top portion of the hard mask is removed, resulting in a top portion of the filled dielectric material to protrude above the remaining hard mask. The protruding dielectric is then treated in an oxygen plasma and annealed at a high temperature to form a densified oxide cap layer. The densified oxide layer can provide greater resistance to corrosion and can protect the shallow trench isolation structure during subsequent wet processing, such as DHF clean. Variations in the STI structures can be reduced and device performance improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 29, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Hao Deng
  • Patent number: 9142422
    Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Hung-Wei Liu, Zhiguo Sun, Huang Liu, Jin Ping Liu
  • Patent number: 9142443
    Abstract: To provide a semiconductor device having improved reliability at an improved production yield. After forming an insulating film on the main surface of a semiconductor substrate as an oxide film, form a silicon nitride film on the insulating film. Then, form an element isolating trench by plasma dry etching, form an insulating film made of silicon oxide so as to fill the trench by using HDP-CVD, and remove the insulating film outside the trench by CMP, while leaving the insulating film in the trench. Then, remove the silicon nitride film, followed by removal of the insulating film by wet etching to expose the semiconductor substrate. At this time, the insulating film is wet etched while applying light of 140 lux or greater to the main surface of the semiconductor substrate.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhiko Hasegawa
  • Patent number: 9040337
    Abstract: Provided are a stretchable electronic device and a method of manufacturing the same. The manufacturing method includes forming coil interconnection on a first substrate, forming a first stretchable insulating layer that covers the coil interconnection, forming a second substrate on the first stretchable insulating layer, separating the first substrate from the coiling interconnection and the first stretchable insulating layer, and forming a transistor on the coil interconnection.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chan Woo Park, Jae Bon Koo, Sang Chul Lim, Ji-Young Oh, Soon-Won Jung
  • Publication number: 20150118823
    Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventors: Olivier Nier, Denis Rideau, Pierre Morin, Emmanuel Josse
  • Publication number: 20150118824
    Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventors: Denis Rideau, Emmanuel Josse, Olivier Nier
  • Publication number: 20150115396
    Abstract: A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: Marko Lemke, Rolf Weis, Ralf Rudolf
  • Patent number: 9018075
    Abstract: The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Toru Ito, Hiroaki Ishimura, Akito Kouchi, Hayato Watanabe
  • Patent number: 9018076
    Abstract: A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ogawa, Akihisa Yamaguchi
  • Publication number: 20150108601
    Abstract: A semiconductor device includes an oxide film structure having different thicknesses depending on where the oxide film structure is formed. In the semiconductor device, a wall oxide film is formed to have different thicknesses depending on locations of sidewalls of an active region. The semiconductor device includes an active region, a first wall oxide film disposed over a first sidewall of the active region that extends along a first direction of the active region, the first wall oxide film having a first thickness, and a second wall oxide film disposed over a second sidewall of the active region that extends along a second direction of the active region, a second wall oxide film having a second thickness that is different from the first thickness.
    Type: Application
    Filed: April 1, 2014
    Publication date: April 23, 2015
    Applicant: SK hynix Inc.
    Inventor: Se In KWON
  • Publication number: 20150108600
    Abstract: Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Song Guo, Yushi Hu, Roy Meade, Sanh D. Tang, Michael P. Violette, David H. Wells
  • Patent number: 9012301
    Abstract: In the method of manufacturing a semiconductor apparatus of the present invention, after forming trench isolation regions 100c, 100f, and 100g on a surface of a semiconductor substrate 101 so as to isolate element regions on which the semiconductor elements are to be formed, a silicon nitride film (antioxidant film) 109 is formed so as to cover the trench isolation regions and to stick out from the trench isolation regions with partially overlapping element regions adjacent to the trench isolation regions, and a thermal oxide film 110 that is thicker than a thermal oxide film required in a semiconductor element of a predetermined size among a plurality of semiconductor elements, is formed on the element region using the antioxidant film as a mask.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: April 21, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Hikida
  • Patent number: 9012302
    Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kedar Sapre, Nitin Ingle, Jing Tang
  • Patent number: 8980715
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8975152
    Abstract: Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Sukwon Hong, Hiroshi Hamana, Jingmei Liang
  • Patent number: 8969172
    Abstract: [Problem] To provide a method for forming an isolation structure having a low shrinkage percentage and a low tensile stress. [Means for Solving] A first polysilazane composition containing a porogen is cast on the surface of a substrate to form a coat, and then the coat is fired to form a porous siliceous film having a refractive index of 1.3 or less. Thereafter, the surface of the porous siliceous film is soaked with a second polysilazane composition, and then fired to form an isolation structure of a siliceous film having a refractive index of 1.4 or more.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 3, 2015
    Assignee: AZ Electronic Materials USA Corp.
    Inventors: Naoko Nakamoto, Katsuchika Suzuki, Shinji Sugahara, Tatsuro Nagahara
  • Patent number: 8962430
    Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: February 24, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Nicolas Loubet, Bruce Doris
  • Patent number: 8962446
    Abstract: Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Robert J. Hanson, Janos Fucsko
  • Patent number: 8957418
    Abstract: A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 17, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi, Hiroshi Matsukizono
  • Publication number: 20150044855
    Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Inventors: Xiuyu Cai, Ruilong Xie, William J. Taylor, JR.
  • Patent number: 8940615
    Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
  • Patent number: 8927387
    Abstract: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B Doris, Balasubramanian S Haran, Sanjay Mehta, Stefan Schmitz
  • Patent number: 8927390
    Abstract: A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kedar Sapre, Nitin Ingle, Jing Tang
  • Patent number: 8921183
    Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 30, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Jen-Jui Huang, Hung-Ming Tsai
  • Publication number: 20140374838
    Abstract: An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Neng-Kuo Chen, Gin-Chen Huang, Ching-Hong Jiang, Sey-Ping Sun, Clement Hsingjen Wann