With Epitaxial Deposition Of Semiconductor In Groove Patents (Class 438/44)
  • Patent number: 9356190
    Abstract: A GaN-based LED includes: a substrate with front and back sides; an epitaxial layer formed over the front side of the substrate and including, from top down, a P-type layer, a light-emitting area, and an N-type layer; a current spreading layer formed over the P-type layer; a P electrode formed over the current spreading layer; a first reflecting layer between the current spreading layer and the epitaxial layer, disposed at a peripheral area of the epitaxial layer in a band-shaped distribution; and a second reflecting layer over the back side the substrate. The band-shaped or annular distribution can increase a probability light extraction of the LED sideways. By controlling the ratio of lights extracted upwards and sideways, the light-emitting distribution evenness can be adjusted and the uneven heat dissipation can be improved.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: May 31, 2016
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiansen Zheng, Suhui Lin, Kangwei Peng, Lingyuan Hong, Lingfeng Yin
  • Patent number: 9196709
    Abstract: A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface. The top surface includes a flat surface, and a slant surface having a (111) surface plane. The slant surface has a bottom edge connected to the flat surface, and a top edge connected to one of the isolation regions. The method further includes performing an epitaxy to grow a semiconductor material in the recess, wherein the semiconductor material is grown from the flat surface and the slant surface, and performing an annealing on the semiconductor material.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9190395
    Abstract: A GaN-based LED includes a substrate; an epitaxial layer over the substrate; a current spreading layer over a P-type layer; and a P electrode over the current spreading layer. The epitaxial layer includes the P-type layer, a light-emitting area, and an N-type layer. An annular reflecting layer and a metal reflecting layer are formed between the P electrode and the epitaxial layer. The geometric center vertically corresponds to the P electrode; the annular reflecting layer is formed between the current spreading layer and the P-type layer; the metal reflecting layer is formed between the current spreading layer and the P electrode; and a preset distance is arranged between the annular reflecting layer and the metal reflecting layer. The annular reflecting layer and the metal reflecting layer reduce light absorption of the P electrode and improve light extraction efficiency.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: November 17, 2015
    Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Jiansen Zheng, Suhui Lin, Kangwei Peng, Lingyuan Hong, Anhe He
  • Patent number: 9153431
    Abstract: A method of epitaxially growing nitrogen-based compound semiconductor thin films on a semiconductor substrate, which is periodically patterned with grooves. The method can provide an epitaxial growth of a first crystalline phase epitaxial film on the substrate, and block the growth of an initial crystalline phase with barrier materials prepared at the sides of the grooves. Semiconductor devices employing the epitaxial films are also disclosed.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: October 6, 2015
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Patent number: 9147728
    Abstract: The present disclosure relates to a semiconductor nanostructure. The semiconductor nanostructure includes a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane. The at least one ridge extends from the first crystal plane along a crystallographic orientation of the second crystal plane. A width of cross section at a position of half the height of the at least one ridge is less than 17 nm. The semiconductor nanostructure is a patterned structure which can lead to generate a quantum confinement effect, such that the impurity scattering phenomenon is reduced.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: September 29, 2015
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jian Wu, Zheng Liu, Wen-Hui Duan, Bing-Lin Gu
  • Patent number: 9048173
    Abstract: A method for selective formation of a dual phase gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patterned dielectric material structures on silicon substrate. An etch is employed that selectively removes exposed portions of the silicon substrate. The etch forms openings within the silicon substrate that expose a surface of the silicon substrate having a (111) crystal plane. A contiguous AlN buffer layer is then formed on exposed surfaces of each patterned dielectric material structure and on exposed surfaces of the silicon substrate. A dual phase gallium nitride material is then formed on a portion of the contiguous AlN buffer layer and surrounding each sidewall of each patterned dielectric material structure.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 2, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9029177
    Abstract: An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 12, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Butendeich, Alexander Walter, Matthias Peter, Tobias Meyer, Tetsuya Taki, Hubert Maiwald
  • Patent number: 9012953
    Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Steven Lester, Jeff Ramer, Jun Wu, Ling Zhang
  • Patent number: 9000415
    Abstract: The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including AlxGa(1-x)N (0<x<1) and a quantum well layer including AlyGa(1-y)N (0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes AlGaN. The intermediate layer includes AlN and has a plurality of air voids formed in the AlN. At least some of the air voids are irregularly aligned and the number of the air voids is 107 to 1010/cm2.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 7, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hae Jin Park, Kyoung Hoon Kim, Dong Ha Kim, Kwang chil Lee, Jae Hun Kim, Hwan Hui Yun
  • Patent number: 8969190
    Abstract: Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Joachim Patzer
  • Patent number: 8936951
    Abstract: Provided are a semiconductor laser and a method of manufacturing the same. The method includes: providing a substrate including a buried oxide layer; forming patterns, which includes an opening part to expose the substrate, by etching the buried oxide layer; forming a germanium single crystal layer in the opening part; and forming an optical coupler, which is adjacent to the germanium single crystal layer, on the substrate.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Gyoo Kim, Gyungock Kim, Sang Hoon Kim, Ki Seok Jang, JiHo Joo
  • Patent number: 8932888
    Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 13, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8921141
    Abstract: Aspects of the invention provide methods and devices. In one embodiment, the invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanopyramids are grown utilizing a CVD based selective area growth technique. The nanopyramids are grown directly or as core-shell structures.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: December 30, 2014
    Assignee: Glo AB
    Inventors: Olga Kryliouk, Nathan Gardner, Giuliano Portilho Vescovi
  • Patent number: 8890114
    Abstract: A light-emitting device comprises a first semiconductor layer; a second semiconductor layer; an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electron blocking layer formed between the first semiconductor layer and the active layer; and a second electron blocking layer formed between the second semiconductor layer and the active layer, wherein the thickness of the second electron blocking layer is not equal to that of the first electron blocking layer, and/or the band gap energy of the second electron blocking layer is not equal to that of the first electron blocking layer.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 18, 2014
    Assignee: Epistar Corporation
    Inventors: Sheng-Horng Yen, Ta-Cheng Hsu
  • Publication number: 20140332763
    Abstract: According to an aspect of the present invention, an organic luminescence display includes a substrate, a first electrode on the substrate, a pixel defining layer on the first electrode and partially exposing the first electrode, an auxiliary layer on the pixel defining layer, an organic layer on the first electrode and an edge of the auxiliary layer, and a second electrode on the organic layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: November 13, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jun-Young Kim
  • Patent number: 8877652
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8835263
    Abstract: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: September 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Johan Weijtmans, Jiong-Ping Lu, Rick Wise
  • Patent number: 8822248
    Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ji-Soo Park
  • Publication number: 20140242738
    Abstract: A manufacturing method for an LED includes providing a substrate having a buffer layer and a first N-type epitaxial layer, forming a blocking layer on the first N-type epitaxial layer, and etching the blocking layer to form patterned grooves penetrating the blocking layer to the first N-type epitaxial layer. A second N-type epitaxial layer is then formed on the blocking layer to contact the first N-type epitaxial layer; a light emitting layer, a P-type epitaxial layer and a conductive layer are thereafter disposed on the second N-type epitaxial layer; an N-type electrode is formed to electrically connect with the first N-type epitaxial layer, and a P-type electrode is formed on the conductive layer. The N-type electrode is disposed on the blocking layer and separated from the second N-type epitaxial layer and has a portion extending into the patterned grooves to contact the first N-type epitaxial layer.
    Type: Application
    Filed: May 4, 2014
    Publication date: August 28, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: YA-WEN LIN, SHIH-CHENG HUANG, PO-MIN TU, CHIA-HUNG HUANG, SHUN-KUEI YANG
  • Publication number: 20140241391
    Abstract: A semiconductor light-emitting element includes a substrate, a recess in the substrate, and a ridge portion disposed in the recess, the ridge portion having a constant width, in which the recess has a width that varies in the longitudinal direction of the ridge portion, the ridge portion is formed of a compound semiconductor multilayer structure including an active layer, and the active layer has a thickness that varies in the longitudinal direction of the ridge portion.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Sony Corporation
    Inventor: Hiroaki Abe
  • Patent number: 8815656
    Abstract: A semiconductor processing method is provided which promotes greater growth on <110> crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on <110> crystallographic planes and the least amount of growth occurs on <100> crystallographic planes. The process can be applied to form embedded stressor regions in planar field effect transistors, and the process can be used to grow semiconductor layers on exposed wall surfaces of adjacent fins in source-drain regions of finFETs to fill spaces between the fins.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Judson R. Holt, Keith H. Tabakman, Alexander Reznicek
  • Patent number: 8816367
    Abstract: According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first and second semiconductor layers and a light emitting layer. The first electrode includes a first region, a second region, and a third region provided between them. The first semiconductor layer includes a first portion on the first region and a second portion on the second region. The light emitting layer includes a third portion on the first portion and a fourth portion on the second portion. The second semiconductor layer includes a fifth portion on the third portion and a sixth portion on the fourth portion. The insulating layer is provided between the first and second portions on the third region and between the third and fourth portions. The second electrode includes a seventh portion provided on the insulating layer, eighth and ninth portions contacting side surfaces of the fifth and sixth portions.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Kotaro Zaima, Hiroshi Ono, Shinji Yamada, Shigeya Kimura, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8816321
    Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tadashi Takeoka, Yoshihiko Tani, Kazuya Araki, Yoshihiro Ueta
  • Patent number: 8803189
    Abstract: A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou, Hung-Ta Lin
  • Patent number: 8772825
    Abstract: A stacked semiconductor device and an associated manufacturing method are disclosed. A first semiconductor unit having a first surface, which is defined as being not a polar plane, is provided. At least one pit is formed on the first surface, and the pit has a second surface that lies at an angle relative to the first surface. A polarization enhanced tunnel junction is formed on the second surface, and a second semiconductor unit is formed above the tunnel junction.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 8, 2014
    Assignee: Phostek, Inc.
    Inventors: Jinn Kong Sheu, Wei-Chih Lai
  • Patent number: 8766281
    Abstract: A light emitting diode chip includes a substrate, an epitaxial layer, two inclined plane units, and two electrode units. The substrate has top and bottom surfaces. The epitaxial layer is disposed on the top surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer toward the bottom surface of the substrate, and includes an inclined sidewall formed on the epitaxial layer, and a substrate inclined wall formed on the substrate. Each of the electrode units includes an electrode disposed on the epitaxial layer, and a conductive portion extending from the electrode to the substrate inclined wall along corresponding one of the inclined plane units.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: July 1, 2014
    Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.
    Inventor: Chih-Chiang Kao
  • Patent number: 8765501
    Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 1, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Tuoh-Bin Ng, Olga Kryliouk, Sang Won Kang, Jie Cui
  • Patent number: 8765510
    Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8759203
    Abstract: A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu
  • Patent number: 8742443
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer, a functional layer and a light generating layer. The buffer layer is located on a top surface of the substrate. The functional layer includes a plurality of high-temperature epitaxial layers and low-temperature epitaxial layers alternatively arranged between the buffer layer and light generating layer. A textured structure is formed in the low-temperature epitaxial layer. A SiO2 layer including a plurality of convexes is located on the textured structure to increase light extraction efficiency of the LED epitaxial structure. A manufacturing method of the LED epitaxial structure is also disclosed.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: June 3, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu
  • Patent number: 8742429
    Abstract: A semiconductor light emitting device includes a first semiconductor layer having a bottom surface with uneven patterns, an active layer formed on the first semiconductor layer, a second semiconductor layer formed on the active layer, a second electrode formed on the second semiconductor layer, and a first electrode formed under the first semiconductor layer.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: June 3, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jin Sik Choi
  • Patent number: 8728840
    Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Thomas Gehrke
  • Publication number: 20140134773
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Application
    Filed: October 9, 2012
    Publication date: May 15, 2014
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventor: Sensor Electronic Technology, Inc.
  • Patent number: 8722441
    Abstract: A method for fabricating a light emitting device includes forming a trench in a first surface on first side of a substrate. The trench comprises a first sloped surface not parallel to the first surface, wherein the substrate has a second surface opposite to the first surface of the substrate. The method also includes forming alight emission layer over the first trench surface, but not over the remainder of the first substrate surface, and removing at least a portion of the substrate from the second side of the substrate to expose the light emission layer and allow it to emit light out of the protrusion or protrusions on the second side of the substrate. These protrusions may be elongated pyramids.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 13, 2014
    Assignee: SiPhoton Inc.
    Inventors: Shaoher X. Pan, Jay Chen
  • Patent number: 8709846
    Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Niraj Rana, Zaiyuan Ren
  • Patent number: 8698284
    Abstract: A nitride-based semiconductor substrate may includes a plurality of hollow member patterns arranged on a substrate, a nitride-based seed layer formed on the substrate between the plurality of hollow member patterns, and a nitride-based buffer layer on the nitride-based seed layer so as to cover the plurality of hollow member patterns, wherein the plurality of hollow member patterns contact the substrate in a first direction and both ends of each of the plurality of hollow member patterns are open in the first direction.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Moon Lee
  • Patent number: 8697466
    Abstract: A method of manufacturing a nitride semiconductor device includes the step of forming a second nitride semiconductor layer having an inclined facet by metal-organic chemical vapor deposition, in which a molar flow ratio of a group V element gas to a group III element gas that are supplied to a growth chamber of a metal-organic chemical vapor deposition growth apparatus is set at 240 or less.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Komada
  • Patent number: 8685773
    Abstract: A method for making a semiconductor epitaxial structure is provided. The method includes growing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, epitaxially growing a doped semiconductor epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be suspended above the epitaxial growth surface.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: April 1, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8684749
    Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 1, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventors: Steven Lester, Jeff Ramer, Jun Wu, Ling Zhang
  • Patent number: 8686433
    Abstract: A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Nobuaki Matsui, Hirotaka Obuchi, Yasuo Nakanishi, Kazuaki Tsutsumi, Takao Fujimori
  • Patent number: 8680589
    Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Josephine B. Chang, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8647929
    Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 11, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jin-Ping Han
  • Patent number: 8633045
    Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a carbon nanotube layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The carbon nanotube layer can be a carbon nanotube film drawn from a carbon nanotube array and including a plurality of successive and oriented carbon nanotubes joined end-to-end by van der Waals attractive force therebetween.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 21, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Chen Feng, Shou-Shan Fan
  • Patent number: 8628989
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20130328075
    Abstract: According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first and second semiconductor layers and a light emitting layer. The first electrode includes a first region, a second region, and a third region provided between them. The first semiconductor layer includes a first portion on the first region and a second portion on the second region. The light emitting layer includes a third portion on the first portion and a fourth portion on the second portion. The second semiconductor layer includes a fifth portion on the third portion and a sixth portion on the fourth portion. The insulating layer is provided between the first and second portions on the third region and between the third and fourth portions. The second electrode includes a seventh portion provided on the insulating layer, eighth and ninth portions contacting side surfaces of the fifth and sixth portions.
    Type: Application
    Filed: December 26, 2012
    Publication date: December 12, 2013
    Inventors: Jumpei Tajima, Kotaro Zaima, Hiroshi Ono, Shinji Yamada, Shigeya Kimura, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8592237
    Abstract: A method for manufacturing a thin film transistor substrate including forming bus lines by etching a surface of a substrate to form bus line patterns and filling the bus line patterns with a bus line metal; forming a semiconductor channel layer at one portion of a pixel area defined by the bus lines; and forming source-drain electrodes on the semiconductor channel layer, a pixel electrode extending from the drain electrode within the pixel area, and a common electrode parallel with the pixel electrode. The bus lines are formed as being thicker but the bus lines are buried in the substrate so that the line resistance can be reduced and the step difference due to the thickness of bus line does not affect the device.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: November 26, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Jungil Lee, Injae Chung, Joonyoung Yang, Gisang Hong
  • Patent number: 8557622
    Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: October 15, 2013
    Assignee: STC.UNM
    Inventors: Seung Chang Lee, Steven R. J. Brueck
  • Patent number: 8525221
    Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits lights when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: September 3, 2013
    Assignee: Toshiba Techno Center, Inc.
    Inventors: Steven Lester, Jeff Ramer, Jun Wu, Ling Zhang
  • Patent number: 8507304
    Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: August 13, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Olga Kryliouk, Yuriy Melnik, Hidehiro Kojiri, Tetsuya Ishikawa
  • Patent number: 8502263
    Abstract: Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jizhong Li, Anthony J. Lochtefeld