With Epitaxial Deposition Of Semiconductor In Groove Patents (Class 438/44)
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Patent number: 7537980Abstract: In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially filling the first opening. A second SEG process may be performed to form a second plug filling the first opening. A third SEG process may be carried out to form a first channel layer on the first insulation interlayer pattern. A second insulation interlayer may be formed on the first channel layer. The second insulation interlayer, the first channel layer and the second plug arranged on the first plug may be removed to expose the first plug. The first plug may be removed to form a serial opening. The serial opening may be filled with a metal wiring.Type: GrantFiled: August 28, 2006Date of Patent: May 26, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee
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Patent number: 7534706Abstract: A method is provided for making a silicided gate in a semiconductor device. In accordance with the method, a gate (213) is provided which comprises a first portion (214) and a second portion (213). The first portion of the gate has a width w1 and the second portion of the gate has a width w2 as taken along a plane perpendicular to the length of the gate, wherein w2>w1. A layer is silicide (231) is then formed on the second portion.Type: GrantFiled: February 6, 2006Date of Patent: May 19, 2009Assignee: Freescale Semiconductor, Inc.Inventor: James G. Boyd
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Patent number: 7508001Abstract: The present invention aims to provide a long-lived semiconductor laser device with low threshold current and available for high-output operation in a blue-violet semiconductor laser device using a nitride semiconductor layer. In the semiconductor laser device, the following layers are sequentially formed on a GaN substrate 1: an n-type GaN layer 2; an n-type AlGaN cladding layer 3, a first n-type GaN guiding layer 4; and a p-type AlGaN blocking layer 6 (current-blocking layer), further a striped opening is formed on a portion of the p-type AlGaN blocking layer 6, a second n-type GaN guiding layer 5 is formed to cover the opening, and the following layers are sequentially formed on the second n-type GaN guiding layer 5: an InGaN multiple quantum well active layer 7; an undoped GaN guiding layer 8; a p-type AlGaN electron overflow suppression layer 9, a p-type AlGaN cladding layer 10, and a p-type GaN contact layer 11.Type: GrantFiled: June 17, 2005Date of Patent: March 24, 2009Assignee: Panasonic CorporationInventors: Tetsuzo Ueda, Masaaki Yuri
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Patent number: 7504292Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.Type: GrantFiled: December 5, 2006Date of Patent: March 17, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keh-Chiang Ku, Pang-Yen Tsai, Chun-Feng Nieh, Li-Ting Wang
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Publication number: 20090020771Abstract: The present disclosure relates to an III-nitride compound semiconductor light emitting device and a method of manufacturing the same. The III-nitride compound semiconductor light emitting device includes a substrate with a groove formed therein, a plurality of nitride compound semiconductor layers being grown on the substrate, and including an active layer for generating light by recombination of electron and hole, and an opening formed on the groove along the plurality of nitride compound semiconductor layers.Type: ApplicationFiled: August 21, 2008Publication date: January 22, 2009Applicant: EPIVALLEY CO., LTD.Inventors: Chang-Tae Kim, Hyun-Min Jung, Eui-Gue Jeon, Hyun-Suk Kim, Gi-Yeon Nam, Byeong-Kyun Choi
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Patent number: 7477334Abstract: A method of manufacturing an electro-optical device, which, on a substrate, has a plurality of data lines, a plurality of scanning lines, a plurality of driving elements formed to correspond to intersections of the plurality of data lines and the plurality of scanning lines for pixels, and a plurality of pixel electrodes provided to correspond to the driving elements, includes forming an etching stopping layer, forming a common line that is provided above the etching stopping layer to short-circuit the plurality of scanning lines and the plurality of scanning lines, forming a first interlayer insulating film that isolates the plurality of data lines and the plurality of pixel electrodes from the plurality of scanning lines and the plurality of driving elements, forming contact holes that electrically connect the plurality of data lines and the plurality of pixel electrodes to the plurality of driving elements, forming the plurality of data lines, and forming a cutting hole in the first interlayer insulating fType: GrantFiled: June 21, 2006Date of Patent: January 13, 2009Assignee: Seiko Epson CorporationInventors: Minoru Moriwaki, Masahiro Yasukawa
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Patent number: 7465977Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.Type: GrantFiled: October 27, 2003Date of Patent: December 16, 2008Assignee: Microbridge Technologies Inc.Inventors: Leslie M. Landsberger, Oleg Grudin
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Patent number: 7459380Abstract: In accordance with the present invention, improved methods for reducing the dislocation density of nitride epitaxial films are provided. Specifically, an in-situ etch treatment is provided to preferentially etch the dislocations of the nitride epitaxial layer to prevent threading of the dislocations through the nitride epitaxial layer. Subsequent to etching of the dislocations, an epitaxial layer overgrowth is performed. In certain embodiments, the etching of the dislocations occurs simultaneously with growth of the epitaxial layer. In other embodiments, a dielectric mask is deposited within the etch pits formed at the dislocations prior to the epitaxial layer overgrowth.Type: GrantFiled: May 5, 2006Date of Patent: December 2, 2008Assignee: Applied Materials, Inc.Inventors: David Bour, Sandeep Nijhawa, Jacob Smith, Lori Washington
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Patent number: 7445949Abstract: A method of manufacturing a semiconductor laser device is provided. First, a first mask layer is formed on an epitaxial structure to define a protrudent area in a ridge structure. Thereafter, a conformal second mask layer is formed over the epitaxial structure to cover the first mask layer. A third mask layer is formed over the second mask layer. The exposed second mask layer is removed. Using the first and the third mask layers as etching masks, a portion of the epitaxial structure is removed. The third mask layer and the remaining second mask layer are removed to form the ridge structure. An insulation layer is formed on the epitaxial structure and then the first mask layer is removed to expose the top surface of the protrudent area. A conductive layer is formed on the epitaxial structure such that it contacts with the top surface of the protrudent area.Type: GrantFiled: August 6, 2004Date of Patent: November 4, 2008Assignee: National Central UniversityInventors: Hung-Cheng Lin, Jen-Inn Chyi, Guan-Ting Chen
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Publication number: 20080247433Abstract: A nitride semiconductor laser which features low resistance and high reliability. A buried layer is formed by selective growth and the shape of a p-type cladding layer is inverted trapezoidal so that the resistance of the p-type cladding layer and that of a p-type contact layer are decreased. For long-term reliability of the laser, the buried layer is a high-resistance semi-insulating layer which suppresses increase in leak current.Type: ApplicationFiled: August 20, 2007Publication date: October 9, 2008Inventors: Tomonobu Tsuchiya, Shigehisa Tanaka, Akihisa Terano
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Patent number: 7410819Abstract: In a method for producing a nitride semiconductor light-emitting device according to the present invention, first, a nitride semiconductor substrate having groove portions formed is prepared. An underlying layer comprising nitride semiconductor is formed on the nitride semiconductor substrate including the side walls of the groove portions, in such a manner that the underlying layer has a crystal surface in each of the groove portions and the crystal surface is tilted at an angle of from 53.5° to 63.4° with respect to the surface of the substrate. Over the underlying layer, a light-emitting-device structure composed of a lower cladding layer containing Al, an active layer, and an upper cladding layer containing Al is formed. According to the present invention, thickness nonuniformity and lack of surface flatness, which occur when accumulating a layer with light-emitting-device structure of nitride semiconductor over the nitride semiconductor substrate, are alleviated while inhibiting occurrence of cracking.Type: GrantFiled: December 8, 2005Date of Patent: August 12, 2008Assignee: Sharp Kabushiki KaishaInventors: Teruyoshi Takakura, Shigetoshi Ito, Takeshi Kamikawa
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Patent number: 7371596Abstract: A system and method for parallel-beam scanning a surface. An energetic beam source emits an energetic collimated beam which is received by an optical device, comprising: one or more optical media, operable to receive the emitted beam, such as two pairs of coordinated mirrors or a right prism, and at least one actuator coupled to the one or more optical media, and operable to rotate each of the one or more optical media around a respective axis to perform a parallel displacement of the beam in a respective direction, wherein the respective direction, the beam, and the respective axis are mutually orthogonal. The optical device is operable to direct the beam to illuminate a sequence of specified regions of a surface.Type: GrantFiled: December 30, 2004Date of Patent: May 13, 2008Assignee: Semicube, Inc.Inventors: Raymond M. Warner, Jr., Lynn Millar, legal representative, John E. MacCrisken, Mark S. Williams, Earl E. Masterson
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Patent number: 7351633Abstract: A method of fabricating a semiconductor device using selective epitaxial growth (SEG) is disclosed. The method comprises; forming a seed window exposing a portion of a substrate through an interlayer insulating layer, growing a single crystal silicon SEG layer in the seed window using the exposed portion of the substrate as a seed, depositing an amorphous silicon layer on the interlayer insulating layer and in contact with the SEG layer, and performing an annealing process on the amorphous silicon layer over an annealing interval, and during the annealing interval applying microwave energy to the amorphous silicon layer.Type: GrantFiled: June 12, 2006Date of Patent: April 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Jun-Seuck Kim
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Patent number: 7338827Abstract: A method for fabricating nitride semiconductor devices according to the present invention includes the steps of: (A) providing a nitride semiconductor substrate, which will be split into chip substrates, which includes device portions that will function as the respective chip substrates when the substrate is split and interdevice portions that connect the device portions together, and in which the average thickness of the interdevice portions is smaller than the thickness of the device portions; (B) defining a masking layer, which has striped openings over the device portions, on the upper surface of the nitride semiconductor substrate; (C) selectively growing nitride semiconductor layers on portions of the upper surface of the nitride semiconductor substrate, which are exposed through the openings of the masking layer; and (D) cleaving the nitride semiconductor substrate along the interdevice portions of the nitride semiconductor substrate, thereby forming nitride semiconductor devices on the respectively spType: GrantFiled: March 9, 2004Date of Patent: March 4, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Gaku Sugahara, Yasutoshi Kawaguchi, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
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Patent number: 7319076Abstract: A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge section is defined in the overgrowth layer and portions of the sacrificial layer are removed to define a shank section in the overgrowth layer under the ridge section. The ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section.Type: GrantFiled: September 26, 2003Date of Patent: January 15, 2008Assignee: Intel CorporationInventor: Peter J. Hanberg
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Patent number: 7294519Abstract: Provided are a semiconductor light-emitting device having nano-needles and a method of manufacturing the same. The provided semiconductor light-emitting device improves the extraction efficiency of photons, and includes a gallium nitride (GaN) group multi-layer and nano-needles grown on the GaN group multi-layer. The nano-needles improve the extraction efficiency of photons.Type: GrantFiled: June 17, 2005Date of Patent: November 13, 2007Assignee: Luxpia Co., Ltd.Inventors: Jong Soo Lee, Min Sang Lee, Young Ki Lee
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Patent number: 7294520Abstract: A method for fabricating a plurality of semiconductor bodies, in particular based on nitride compound semiconductor material. The method includes forming a mask layer (3) over a substrate (1) or over an initial layer (2), which mask layer has a plurality of windows (4) leading to the substrate (1) or to the initial layer (2), etching back the substrate (1) or the initial layer (2) in the windows (4), in such a manner that pits (41) are formed in the substrate (1) or in the initial layer (2) starting from these windows.Type: GrantFiled: February 17, 2004Date of Patent: November 13, 2007Assignee: Osram Opto Semiconductors GmbHInventors: Volker Harle, Hans-Jürgen Lugauer, Stephan Miller, Stefan Bader
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Patent number: 7285431Abstract: This invention relates to a method for manufacturing a GaN based LED of a back hole structure, and the method comprises: epitaxially growing an N type GaN layer, a multi-quantum wells emitting active region and a P type GaN layer in turn on an insulation substrate made of sapphire or other materials; etching the N type GaN layer by photoetching, and forming a P type ohmic contact electrode and an N type ohmic contact electrode; scribing the chip to divide the dies on the epitaxial chip into individual die; forming a SiO2 insulation isolation layer on both sides of the silicon chip, forming a metal electrode on a face side, and forming a back hole pattern on a back side; forming a back hole; forming a bump pattern for plating on the face side of the silicon chip by thick resist photoetching; forming a layer of alloy with low melting point on the back side of the silicon chip, thus forming a base; on the back side of the base, directly attaching the base to a heat sink of a housing; bonding the die with the facType: GrantFiled: June 27, 2005Date of Patent: October 23, 2007Assignee: Institute of Semiconductors, Chinese Academy of SciencesInventors: Jinmin Li, Guohong Wang, Liangchen Wang, Long Ma, Zhongchao Fan
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Patent number: 7250320Abstract: A semiconductor light emitting element, manufacturing method thereof, integrated semiconductor light emitting device, manufacturing method thereof, illuminating device, and manufacturing method thereof are provided. An n-type GaN layer is grown on a sapphire substrate, and a growth mask of SiN, for example, is formed thereon. On the n-type GaN layer exposed through an opening in the growth mask, a six-sided steeple-shaped n-type GaN layer is selectively grown, which has inclined crystal planes each composed of a plurality of crystal planes inclined from the major surface of the sapphire substrate by different angles of inclination to exhibit a convex plane as a whole. On the n-type GaN layer, an active layer and a p-type GaN layer are grown to make a light emitting element structure. Thereafter, a p-side electrode and an n-side electrode are formed.Type: GrantFiled: February 19, 2004Date of Patent: July 31, 2007Assignee: Sony CorporationInventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Jun Suzuki, Toyoharu Oohata
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Patent number: 7198970Abstract: This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask material to form openings therein extending to the substrate surface; growing active material in the openings; removing the mask material to form the device with reduced extended defect density; and depositing electrical contacts on the device.Type: GrantFiled: January 23, 2004Date of Patent: April 3, 2007Assignee: The United States of America as represented by the Secretary of the NavyInventors: Martin Peckerar, Richard Henry, Daniel Koleske, Alma Wickenden, Charles R. Eddy, Jr., Ronald Holm, Mark E. Twigg
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Patent number: 7198971Abstract: The present invention relates to a nitride semiconductor thin film having less defects and a method of growing the same. According to the present invention, the nitride semiconductor thin film with lower defect density can be manufactured by forming grooves on a substrate, sequentially forming a buffer layer and a first nitride semiconductor thin film on a whole surface of the substrate, etching higher defect density regions of the first nitride semiconductor thin film, and then laterally growing a second nitride semiconductor thin film. Thus, a highly crystalline nitride semiconductor thin film can be obtained. Therefore, there are advantages in that high-efficiency, high-power and high-reliability optical devices or electronic devices can be manufactured and high throughput can also be obtained by using the obtained nitride semiconductor thin film.Type: GrantFiled: December 29, 2004Date of Patent: April 3, 2007Assignee: LG Electronics Inc.Inventor: Johngeon Shin
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Patent number: 7163876Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.Type: GrantFiled: March 12, 2002Date of Patent: January 16, 2007Assignees: Toyoda Gosei Co., Ltd, Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
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Patent number: 7157297Abstract: On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.Type: GrantFiled: May 10, 2005Date of Patent: January 2, 2007Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Eiji Yamada, Masahiro Araki
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Patent number: 7141444Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate.Type: GrantFiled: March 12, 2001Date of Patent: November 28, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Yuta Tezen, Hiroshi Yamashita, Seiji Nagai, Toshio Hiramatsu
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Patent number: 7135348Abstract: A semiconductor light emitting device is fabricated by forming a mask having an opening on a substrate, forming a crystal layer having a tilt crystal plane tilted from the principal plane of the substrate by selective growth from the opening of the mask, and forming, on the crystal layer, a first conductive type layer, an active layer, and a second conductive type layer, which extend within planes parallel to the tilt crystal plane, and removing the mask. The semiconductor light emitting device can be fabricated without increasing fabrication steps while suppressing threading dislocations extending from the substrate side and keeping a desirable crystallinity. The semiconductor light emitting device is also advantageous in that since deposition of polycrystal on the mask is eliminated, an electrode can be easily formed, and that the device structure can be finely cut into chips.Type: GrantFiled: January 16, 2003Date of Patent: November 14, 2006Assignee: Sony CorporationInventors: Hiroyuki Okuyama, Goshi Biwa
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Patent number: 7134179Abstract: A process of forming a capacitive audio transducer, preferably having an all-silicon monolithic construction that includes capacitive plates defined by doped single-crystal silicon layers. The capacitive plates are defined by etching the single-crystal silicon layers, and the capacitive gap therebetween is accurately established by wafer bonding, yielding a transducer that can be produced by high-volume manufacturing practices.Type: GrantFiled: December 13, 2004Date of Patent: November 14, 2006Assignee: Delphi Technologies, Inc.Inventors: John E. Freeman, William J. Baney, Timothy M. Betzner, Dan W. Chilcott, John C. Christenson, Timothy A. Vas, George M Queen, Stephen P Long
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Patent number: 7125736Abstract: To improve crystallographic property of a nitride III-V compound semiconductor layer grown on a sapphire substrate, a plurality of recesses are made on a major surface of the sapphire substrate, and the nitride III-V compound semiconductor layer is grown thereon. At least a part of the inner surface of each recess makes an angle not less than 10 degrees with respect to the major surface of the sapphire substrate. The recesses are buried with nitride III-V compound semiconductor crystal having a higher Al composition ratio than the nitride III-V compound semiconductor layer, such as AlxGa1-xN crystal whose Al composition ratio x is 0.2 or more, for example. Each recess has a depth not less than 25 nm and a width not less than 30 nm. The recesses may be made either upon thermal cleaning of the sapphire substrate or by using lithography and etching, thermal etching, or the like.Type: GrantFiled: April 25, 2005Date of Patent: October 24, 2006Assignee: Sony CorporationInventor: Etsuo Morita
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Patent number: 7122392Abstract: A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.Type: GrantFiled: June 30, 2003Date of Patent: October 17, 2006Assignee: Intel CorporationInventor: Mike Morse
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Patent number: 7112461Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.Type: GrantFiled: November 18, 2003Date of Patent: September 26, 2006Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Yvon Gris
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Patent number: 7109049Abstract: Provided is a method for fabricating a nitride semiconductor light-emitting device including a nitride semiconductor substrate having a groove and a ridge formed on the top surface thereof so as to extend in the shape of stripes and a nitride semiconductor growth layer consisting of a plurality of nitride semiconductor layers laid on top of the nitride semiconductor substrate. The method involves a step of forming a 10 ?m or more wide flat region above at least either of the groove and ridge by forming the nitride semiconductor growth layer on top of the nitride semiconductor substrate so that the height of the nitride semiconductor growth layer laid above the groove is smaller than the height of the nitride semiconductor growth layer laid above the ridge.Type: GrantFiled: February 17, 2005Date of Patent: September 19, 2006Assignee: Sharp Kabushiki KaishaInventors: Teruyoshi Takakura, Takeshi Kamikawa, Yoshika Kaneko
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Patent number: 7049627Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: August 22, 2003Date of Patent: May 23, 2006Assignee: AmberWave Systems CorporationInventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
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Patent number: 7041524Abstract: A semiconductor laser device according to the present invention has a semiconductor substrate having a first region and a second region adjacent to the first region, a first active layer formed on the first region and made of a compound semiconductor, a first clad layer formed on the first active layer and made of a compound semiconductor containing a first dopant, and a second active region formed on the second region and made of a compound semiconductor containing a second dopant having a diffusion coefficient with respect to the first active region which is higher than that of the first dopant.Type: GrantFiled: October 12, 2004Date of Patent: May 9, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshikazu Onishi
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Patent number: 7034341Abstract: An AlGaAs-based semiconductor laser 29 is formed on an n-type GaAs substrate 21 and thereafter etching is carried out until reaching an n-type AlGaAs clad layer 23 from the surface. Next, the n-type AlGaAs clad layer 23 is removed by etching with an etchant having selectivity to GaAs. Subsequently, the surface of an n-type GaAs buffer layer 22 is lightly etched. Thus, the n-type GaAs buffer layer 22 of the AlGaAs-based semiconductor laser 29 is left in a slightly abraded state on the n-type GaAs substrate 21, maintaining the flatness of the groundwork layer during growing an AlGaInP-based semiconductor laser 38 at the second time. Therefore, the flatness of the crystals of, in particular, an active layer grown at the second time can be improved, and the poor characteristics of the AlGaInP-based semiconductor laser 38 attributed to the poor flatness of the groundwork can be improved.Type: GrantFiled: April 14, 2003Date of Patent: April 25, 2006Assignee: Sharp Kabushiki KaishaInventors: Keisuke Miyazaki, Kazuhiko Wada, Taiji Morimoto
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Patent number: 7026182Abstract: To provide a semiconductor device, such as semiconductor laser, having no need of complicated process, ensuring a high yield and mass-productivity necessary for cost reduction, and exhibiting excellent initial characteristics and reliability, nitride semiconductor layers containing a plurality of group III elements are formed on a base body surface having recess (opening) such that the nitride semiconductor layer varies in at least one of composition ratio of the group III elements, band gap energy, refractive index, electrical conductivity and specific resistance within the layer in response to the recess of the base body. In addition, by heating the structure in an atmosphere containing hydrogen and using a layer containing Al as an etching stop layer, controllability and production yield can be improved without influences from fluctuation in etching depth, or the like. Further, etching and re-growth can be conducted consecutively to provide an inexpensive process.Type: GrantFiled: April 5, 2004Date of Patent: April 11, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ishikawa, Shin-Ya Nunoue
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Patent number: 6979584Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.Type: GrantFiled: December 21, 2000Date of Patent: December 27, 2005Assignee: Toyoda Gosei Co, Ltd.Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu
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Patent number: 6972206Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.Type: GrantFiled: April 18, 2005Date of Patent: December 6, 2005Assignee: Sony CorporationInventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima
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Patent number: 6949394Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.Type: GrantFiled: August 20, 2003Date of Patent: September 27, 2005Assignee: Nippon Telegraph and Telephone CorporationInventors: Fumihiko Kobayashi, Take Miyazawa, Hidefumi Mori, Jun-ichi Nakano
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Patent number: 6911351Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0?u, v, w?1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0?x, y, z?1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.Type: GrantFiled: January 16, 2003Date of Patent: June 28, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Kidoguchi, Akihiko Ishibashi, Ryoko Miyanaga, Gaku Sugahara, Masakatsu Suzuki, Masahiro Kume, Yuzaburo Ban, Kiyoyuki Morita, Ayumu Tsujimura, Yoshiaki Hasegawa
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Patent number: 6869806Abstract: Films of gallium manganese nitride are grown on a substrate by molecular beam epitaxy using solid source gallium and manganese and a nitrogen plasma. Hydrogen added to the plasma provides improved uniformity to the film which may be useful in spin-based electronics.Type: GrantFiled: March 14, 2003Date of Patent: March 22, 2005Assignee: WiSys Technology Foundation, Inc.Inventors: Yongjie Cui, Lian Li
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Patent number: 6864112Abstract: The present invention relates to a method for the production of semiconductor components. This method comprises the steps of applying masking layers and components on epitaxial semiconductor substrates within the epitaxy reactor without removal of the substrate from the reactor. The masking layers may be HF soluble such that a gas etchant may be introduced within the reactor so as to etch a select number and portion of masking layers. This method may be used for production of lateral integrated components on a substrate wherein the components may be of the same or different type. Such types include electronic and optoelectronic components. Numerous masking layers may be applied, each defining particular windows intended to receive each of the various components. In the reactor, the masks may be selectively removed, then the components grown in the newly exposed windows.Type: GrantFiled: November 28, 2000Date of Patent: March 8, 2005Assignee: Osram Opto Semiconductors GmbH & Co. oHGInventor: Volker Härle
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Patent number: 6855571Abstract: The present invention provides a method for fabricating a GaN-based semiconductor laser device comprising the steps of forming a GaN-based semiconductor layer 102 on a substrate 101; forming, on the surface of the first GaN-based semiconductor layer, a mask layer 103 that comprises a striped pattern composed of a plurality of band-like portions 103a that are regularly arranged in the width direction and an alignment pattern formed by altering the regularity of some portion of the plurality of band-like portions 103a; depositing a second GaN-based semiconductor layer 104 on the mask layer 103 by the selective lateral growth method with starting points at portions of the first GaN-based semiconductor layer 104 that are exposed from the mask layer 103; forming a multi-layered semiconductor that comprises an n-type GaN-based semiconductor layers 105 to 107, an active layer 108, and a p-type GaN-based semiconductor layers 109 to 111 on the second GaN-based semiconductor layer 104; and forming a current injection rType: GrantFiled: February 14, 2003Date of Patent: February 15, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Gaku Sugahara, Atsushi Yamada, Akihiko Ishibashi, Toshiya Yokogawa
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Patent number: 6852559Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an epitaxial source/drain junction layer having an insulating film thereunder. The method comprises the step of forming a under-cut under an epitaxial source/drain junction layer so that an insulating film filling the under-cut can be formed.Type: GrantFiled: June 30, 2003Date of Patent: February 8, 2005Assignee: Hynix Semiconductor Inc.Inventors: Byung Il Kwak, Kyung Jun Ahn
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Patent number: 6849473Abstract: In a semiconductor light-emitting device, on an n-GaAs substrate are stacked an n-GaAs buffer layer, an n-cladding layer, an undoped active layer, a p-cladding layer, a p-intermediate band gap layer and a p-current diffusion layer. Further, a first electrode is formed under the n-GaAs substrate, and a second electrode is formed on the grown-layer side. In this process, a region of the p-intermediate band gap layer just under the second electrode is removed, the p-current diffusion layer is stacked in the removal region on the p-cladding layer, and a junction plane of the p-current diffusion layer and the p-cladding layer becomes high in resistance due to an energy band structure of type II. This semiconductor light-emitting device is capable of reducing ineffective currents with a simple construction and taking out light effectively to outside, thus enhancing the emission intensity.Type: GrantFiled: September 25, 2002Date of Patent: February 1, 2005Assignee: Sharp Kabushiki KaishaInventors: Kazuaki Sasaki, Junichi Nakamura, Shouichi Ohyama
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Patent number: 6844246Abstract: A GaN layer 32 grows in vertical direction on a GaN layer 31 where neither a first mask 41m nor a second mask 42m is formed. When thickness of the GaN layer 32 becomes larger than that of the first mask 41m, it began to grown in lateral direction so as to cover the first mask 41m. Because the second mask 42m is not formed on the upper portion of the first mask 41m, the GaN layer 32 grows in vertical direction. On the contrary, at the upper region of the GaN layer 31 where the mask 41m is not formed, the second mask 42m is formed like eaves, the growth of the GaN layer 32 stops and threading dislocations propagated with vertical growth also stops there. The GaN layer 32 grows in vertical direction so as to penetrate the region where neither the first mask 41m nor the second mask 42m is formed. When the height of the GaN layer 32 becomes larger than that of the second mask 42m, the GaN layer 32 begins to grow in lateral direction again and covers the second mask 42m.Type: GrantFiled: March 19, 2002Date of Patent: January 18, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Kazuyoshi Tomita, Masahito Kodama
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Patent number: 6844213Abstract: A microneedle and a process of forming the microneedle of single-crystal silicon-based material without the need for deposited films. The microneedle comprises a piercing end, an oppositely-disposed second end, and an internal passage having an opening adjacent the piercing end. The cross-section of the microneedle, and therefore the passage within the microneedle, is defined by first and second walls formed of doped single-crystal silicon-based material and separated by the passage, and first and second sidewalls separated by the passage, sandwiched between the first and second walls, and formed of single-crystal silicon-based material that is more lightly doped than the first and second walls.Type: GrantFiled: March 22, 2002Date of Patent: January 18, 2005Assignee: Integrated Sensing SystemsInventor: Douglas Ray Sparks
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Patent number: 6821805Abstract: Disclosed is a semiconductor device which comprises a substrate in which surface is formed a depression having a closed figure when viewed from the substrate normal and a semiconductor layer which is formed on the surface of the substrate by crystal growth from at least an inside face of the depression.Type: GrantFiled: October 5, 2000Date of Patent: November 23, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinji Nakamura, Masahiro Ishida, Kenji Orita, Osamu Imafuji, Masaaki Yuri
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Patent number: 6821804Abstract: This invention describes new LEDs having light extraction structures on or within the LED to increase its efficiency. The new light extraction structures provide surfaces for reflecting, refracting or scattering light into directions that are more favorable for the light to escape into the package. The structures can be arrays of light extraction elements or disperser layers. The light extraction elements can have many different shapes and are placed in many locations to increase the efficiency of the LED over conventional LEDs. The disperser layers provide scattering centers for light and can be placed in many locations as well. The new LEDs with arrays of light extraction elements are fabricated with standard processing techniques making them highly manufacturable at costs similar to standard LEDs. The new LEDs with disperser layers are manufactured using new methods and are also highly manufacturable.Type: GrantFiled: September 17, 2003Date of Patent: November 23, 2004Assignee: Cree, Inc.Inventors: Brian Thibeault, Michael Mack, Steven DenBaars
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Patent number: 6821798Abstract: A monolithic semiconductor optical device with excellent temperature and modulation characteristics and associated method of manufacturing whereby the device has a semiconductor substrate, a semi-insulating buried heterostructure GaInAsP-based DFB laser; and either a buried ridge type AlGaInAs-based EA or a self aligned structure (SAS) AlGaInAs-based EA modulator.Type: GrantFiled: January 15, 2002Date of Patent: November 23, 2004Assignee: The Furukawa Electric Co., Ltd.Inventors: Satoshi Arakawa, Tatsuto Kurobe, Nariaki Ikeda, Takeharu Yamaguchi
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Patent number: 6818463Abstract: Nitride semiconductor devices and methods of producing same are provided. The present invention includes forming a nitride semiconductor layer on a base body of the nitride semiconductor under selective and controlled crystal growth conditions. For example, the crystal growth rate, the supply of crystal growth source material and/or the crystal growth area can be varied over time, thus resulting in a nitride semiconductor device with enhanced properties.Type: GrantFiled: April 18, 2002Date of Patent: November 16, 2004Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
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Patent number: 6818465Abstract: Nitride semiconductor devices and methods of fabricating same are provided. The nitride semiconductor device includes a crystal layer grown into a three-dimensional shape having a side surface portion and an upper layer portion, wherein an electrode layer is formed on the upper layer portion via a high resistance region formed by an undoped gallium nitride layer or the like. Since the high resistance region is provided on the upper layer portion, a current flows so as to bypass the high resistance region of the upper layer portion, to form a current path extending mainly or substantially along the side surface portion while avoiding the upper layer portion, thereby suppressing the flow of a current in the upper layer portion poor in crystallinity.Type: GrantFiled: April 22, 2003Date of Patent: November 16, 2004Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata