Abstract: A bendable display panel and a fabricating method thereof are disclosed, including: providing the flexible substrate and the inorganic film layer formed on the flexible substrate, the inorganic film layer includes a deep hole region disposed in a bending area; dry etching the deep hole region to form a deep hole having a slope, and a bottom of the deep hole is located on the flexible substrate; filling the deep hole with an organic material to form an organic film layer; and forming a metal wiring layer on the inorganic film layer and the organic film layer. In the method, a deep hole having a slope is formed by gas dry etching. The etching method can control the slope to improve the climbing ability of the metal wiring, and reduce or avoid the loss of electrical signal caused by disconnection of the metal wiring, thereby improving the display panel quality.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: A semiconductor layer having n-type is made of silicon carbide, and has an element region and a terminal region. A plurality of field limiting ring regions having p-type are provided in the terminal region of the semiconductor layer, and are arranged spaced apart from one another. A field insulating film is provided in the terminal region of the semiconductor layer, and is in contact with the field limiting ring regions and the semiconductor layer. Each of the field limiting regions includes a halogen-containing field limiting ring part in contact with the field insulating film and containing halogen family atoms.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.

Abstract: A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Abstract: The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (11?)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy.

Abstract: Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.

Abstract: [PROBLEMS] To provide a semiconductor element manufacturing method by which a semiconductor element having high accuracy and high function can be manufactured by controlling diffusion depth and diffusion concentration in a pn junction region with high accuracy. [MEANS FOR SOLVING PROBLEMS] A diffusion control layer (2) composed of a thin film of a substance having a smaller diffusion coefficient than that of a diffusion source (3) is formed between a surface of a substrate (1) and the diffusion source (3), and an element of the diffusion source (3) is permitted to thermally diffuse through the diffusion control layer (2). Thus, the diffusion depth and the diffusion concentration in the semiconductor region, which is formed on the surface portion of the substrate and has a conductivity type different from that of the substrate, can be highly accurately controlled, and the semiconductor element having high accuracy and high function can be manufactured.

Abstract: Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality of the epitaxial material improves relative to selective processes where no deposition occurs on insulators. Use of a germanium catalyst during the etch phases of the process aid etch rates and facilitate economical maintenance of isothermal and/or isobaric conditions throughout the cycles. Throughput and quality are improved by use of trisilane, formation of amorphous material over the insulating regions and minimizing the thickness ratio of amorphous:epitaxial material in each deposition phase.

Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.

Abstract: A method of forming a buried oxide/crystalline III-V semiconductor dielectric stack is presented. The method includes providing a substrate and forming a layered structure on the substrate comprising of layers of different materials, one of the different materials is selected to be an oxidizable material to form one or more buried low index oxide layers. A first sequence of oxidizing steps are performed on the layered structure by exposing the edges of the layered structure to a succession of temperature increases in the presence of steam from an initial temperature to the desired oxidation temperature for a time interval equal to the sum of the time intervals of the succession of temperature increases. Also, the method includes performing a second sequential oxidizing step with steam on the layered structure at the specific oxidation temperature for a specific time interval.

Abstract: A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.

Abstract: The invention relates to a method of producing a semiconductor device, comprising the following steps consisting in: forming first, second and third semiconductor layers (1, 2, 3), whereby the first and second layers (1, 3) contain a smaller concentration of oxidizable species than the second layer (2); forming a mask (4) on the third layer (3); and oxidizing the second layer (2) with the diffusion of oxidizing species through the third layer (3).

Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

Abstract: A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

Abstract: The method of the present invention includes providing a semiconductor substrate with a recess; performing a pre-cleaning step on the semiconductor substrate; and performing a first reduction step, a lateral etching step and a second reduction step on the semiconductor substrate. The MOS structure includes a semiconductor substrate, a gate structure on the semiconductor substrate, a pair of recesses with beak sections extending to and under the gate structure, and a strain material filling the recess. The recess inside the semiconductor substrate processed by the method including the lateral etching step forms a beak section.

Abstract: In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.

Abstract: A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.

Abstract: The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus (10) comprising a chamber (12) having a gas input port (14) and a gas output port (16), and means (18) for mounting a silicon substrate within the chamber (12), said apparatus further including a gas source connected to the input port and arranged to provide nitrogen or a noble gas as a carrier gas.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.

Abstract: Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxial structure in the recess. A crystal lattice of the vertical epitaxial structure is aligned with a crystal lattice of the strained substrate.

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract: A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in the trench; exposing an active area of the semiconductor substrate by removing the pad oxide film and the nitride film; forming an epitaxial layer including a dopant in the exposed active area; forming a gate electrode on the epitaxial layer; and forming source and drain regions in the active area beside the gate electrode. The semiconductor device can prevent surface damage of a semiconductor substrate, may occur when performing ion implantation for threshold voltage control, and does not require annealing after ion implantation.

Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.

Abstract: A semiconductor device and fabrication method thereof is disclosed. The method includes the steps of providing a substrate with a trench and a stacked layer thereon, performing an epitaxy process to form an epitaxial layer in the trench, conformably depositing an oxide layer on the epitaxial layer, and removing a portion of the oxide layer and the epitaxial layer on the bottom of the trench.

Abstract: An epitaxial growth method for forming a high-quality epitaxial growth semiconductor wafer is provided. The method includes forming a single crystalline layer on a single crystalline wafer; forming a mask layer having nano-sized dots on the single crystalline layer; forming a porous buffer layer having nano-sized pores by etching the mask layer and the surface of the single crystalline layer; annealing the porous buffer layer; and forming an epitaxial material layer on the porous buffer layer using an epitaxial growth process.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: The invention relates to a method of producing a semiconductor device, comprising the following steps consisting in: forming first, second and third semiconductor layers (1, 2, 3), whereby the first and second layers (1, 3) contain a smaller concentration of oxidisable species than the second layer (2); forming a mask (4) on the third layer (3); and oxidising the second layer (2) with the diffusion of oxidising species through the third layer (3).

Abstract: A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention provides a channel region formed over a device isolation structure to form a semiconductor device including a SOI (Silicon-on-Insulator) channel structure, thereby decreasing ion implanting concentration of a channel region and improving tWR (Write Recovery time) and LTRAS (Long Time for Row Address Strobe) characteristics of the device.

Abstract: A method for manufacturing a semiconductor element includes preparing an SOI layer having a transistor forming area and an element isolation area, forming an oxidation-resistant mask layer on the SOI layer, forming a resist mask over the transistor forming area on the oxidation-resistant mask layer, a first etching that etches the oxidation-resistant mask layer using the resist mask so that a predetermined thickness of the oxidation-resistant mask layer remains, a second etching that etches the remaining oxidation-resistant mask layer, using the resist mask and exposing the SOI layer at the element isolation area, and oxidizing the exposed SOI layer using the remaining oxidation-resistant mask layer, to form an element isolation layer. An etching rate during the first etching is higher than during the second etching and a silicon-to-etching selection ratio during the second etching is higher than during the first etching.

Abstract: This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperfections in bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride islands used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished.

Abstract: A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second oxide layers are etched such that the first oxide layer is wholly removed and the second oxide layer remains only on the first silicon epitaxial layer. A third oxide layer is thermally grown on entire resultant surfaces and then blanket-etched to remain only on sidewalls of the first silicon epitaxial layer. A second silicon epitaxial layer is grown on the exposed substrate between the first active regions, thus forming second active regions. The second oxide layer remaining on the first silicon epitaxial layer is removed. The first and second active regions are separated and electrically isolated by the third oxide layer.

Abstract: Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.

Abstract: An initial single-crystal substrate 1 having, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery of the recess. A layer of amorphous material having the same chemical composition as that of the initial substrate is deposited on the structure obtained. The structure obtained is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate.

Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: Deep isolation trenches having sides and a bottom are formed in a semiconductor substrate. The sides and the bottom are coated with an electrically insulating material that delimits an empty cavity, and forms a plug to close the cavity. The sides of the trench are configured with a neck that determines the depth of the plug, and a first portion that tapers outwards from the neck as the distance from the bottom increases. Deep isolation trenches may be applied, in particular, to bipole and BiCMOS circuits.

Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.

Abstract: An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: The method for selectively forming an epitaxial thin film on a semiconductor substrate by controlling a flow rate of a gas material supplied to a deposition atmosphere includes the step of determining a relation between the growth rate of the epitaxial thin film and the gas flow rate by changing the flow rate of the gas supplied to the deposition atmosphere under a prescribed temperature condition. In this step, a mass transfer limited region, a kinetically limited region and an intermediate region are determined. The method further includes the step of supplying the gas material at the flow rate corresponding to the intermediate region to form the epitaxial thin film on the semiconductor substrate. Thus, the method for selectively forming a flat epitaxial thin film by controlling the growth temperature and the gas flow rate is provided.

Abstract: A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The silicon wafer substrate may then, optionally, be removed from the epitaxial layer.

Abstract: A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.

Abstract: There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.

Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.

Abstract: A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas.