Abstract: A number of npn and pnp bipolar transistors are formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others The higher frequency transistors have their emitters located closer to the collectors, by positioning a collector, or emitter, of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidising the silicon surface, and subsequently removing the oxide to leave the recess.

Abstract: Presented is a process for manufacturing circuit structures of the SOI type integrated on a semiconductor substrate having a first type of conductivity. The process includes forming at least one well with a second type of conductivity in the semiconductor substrate and forming a hole within the well. The hole is then coated with an insulating coating layer, and an opening is formed through the insulating coating layer at the bottom of the hole. The hole is then filled with an epitaxial layer grown from a seed that was made accessible through the opening in the hole.

Abstract: A method for forming a crystal layer including the steps of (1) supplying first impurity atoms onto a surface of a crystal substrate to form a surfactant layer adsorbed on the surface, (2) supplying nucleus atoms which bond with the first impurity atoms, (3) repeating step (2) until second impurity atoms are supplied in step (4), and (4) supplying second impurity atoms which bond with the first impurity atoms and the nucleus atoms to epitaxially grow a crystal layer including the nucleus atoms as a crystal nucleus material doped with the first and second impurity atoms. A co-dopant having a three-atom composite formed by supplying the atoms on the surface of the crystal enables smooth doping thereof to produce the crystal having the high density dopant or a low resistance.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: A process for forming a groove in a semiconductor substrate, to be used to fabricate grooved gate, MOSFET devices, has been developed. The process features the use of an insulator mask, used as an etch mask for definition of the groove feature in the semiconductor substrate. A selective, anisotropic RIE procedure, using an etchant with a specific etch rate ratio of silicon, (semiconductor substrate), to silicon oxide, (insulator mask), is used to establish the desired groove depth, in the semiconductor substrate. The combination of a specific thickness of insulator shape, and a specific etch rate ratio for the selective, anisotropic RIE procedure, allows the desired depth of the groove to be established when the insulator shape is completely removed from the top surface of the semiconductor substrate.

Abstract: A method for fabricating a high-bias device is provided. The method contains forming an N-type epitaxial silicon layer over a P-type substrate. At least a first stacked double well is formed in the epitaxial silicon layer at a region, where a field oxide (FOX) structure is to be formed. A second stacked double well is formed in the epitaxial silicon layer at a region, where a source region is to be formed inside. A FOX structure is formed on the first stacked double well. A gate oxide layer is formed on the epitaxial silicon layer. A conductive gate layer is formed over the substrate to cover a region extending from a portion of the FOX structure to a portion of the second stacked double well. A source region is formed in the second stacked double well with the second-type dopant. A drain region is formed in the epitaxial silicon layer at the opposite side of the FOX layer.

Abstract: The present invention relates to a bioactive feed pellet comprising besides commonly used nutritionally valuable components, a biologically active ingredient such as a therapeutically or prophylactically active compound, a vaccine, a pigment, a vitamin, and/or an enzyme, whereby the bioactive ingredient has been applied to the pellet in the form of a primary coating dispersion and/or emulsion and/or solution in a fatty component or a mixture of dietary oil, said component or dietary oil comprising a triglyceride, and/or fatty acid thereof, having a melting point of above 35.degree. C. in an amount of at least 0.05% by weight of the total weight of the pellet, and in an amount comprising at least 0.2% by weight of said coating, and that a further, second coating layer of an oily product has been applied after said coating dispersion, and/or emulsion and/or solution comprising the bioactive ingredient.

Abstract: A semiconductor device (10) of the present invention has a gate (32) insulatively disposed above the substrate, source and drain regions (36, 38) disposed near the surface in the substrate adjacent opposite sides of the gate (32), and a field oxide region (26) disposed in the surface of the substrate surrounding the source and drain regions (36, 38) and defining an active moat region (20). The channel stop region (24) is disposed below the field oxide region (26) and is spaced from the active moat region (20) with a predetermined spacing.

Abstract: Disclosed is a method of manufacturing a semiconductor device having a reliable element isolation insulating film on an SOI substrate having an SOI layer. That is, the step of forming a semiconductor device on an SOI substrate includes the steps of sequentially depositing a silicon oxide film and an insulating film resistant to oxidation on the surface of the SOI layer of the SOI substrate to form a stacked film, etching the stacked film into a predetermined pattern shape to expose the SOI layer, selectively forming a thin silicon layer on the exposed SOI layer, and selectively thermally oxidizing the thin silicon layer and the exposed SOI layer by using the stacked film as a thermal oxidization mask. In the thermal oxidization step, all the thin silicon layer and the exposed SOI layer are thermally oxidized to be converted into an element isolation insulating film, and the element isolation insulating film is formed in contact with a buried oxide film below the region.

Abstract: A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.

Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.

Abstract: A method of forming a silicon layer disclosed herein includes the steps of depositing an amorphous silicon layer on a substrate, irradiating a silane gas to the substrate, and performing an annealing process in a high vacuum or in an inert gas. The amorphous silicon layer is thereby converted into a silicon layer having an uneven surface caused by hemispherical or spherical silicon grains. The annealing process may be performed while irradiating a hydrogen gas or an oxidizing gas. In this case, such a silicon layer that has an even surface is formed.

Abstract: The method of forming a III-V group compound semiconductor crystalline layer on a semiconductor crystal containing at least V-group compound, includes the steps of: performing the crystal growth of the III-V compound semiconductor crystalline layer; and supplying an n-type dopant and a material compound containing a V-group element onto the semiconductor crystal without causing the crystal growth of the III-V compound semiconductor crystalline layer.

Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.