Abstract: A first semiconductor layer is epitaxially grown on a semiconductor substrate and patterned to form concave and convex portions. A second semiconductor layer is formed on the first semiconductor layer using a top epitaxial mask covering the top surface of the convex portion. Lattice defects D propagating from the first semiconductor layer exist only in a region located above the center of the concave portion (a defect region Ra), while in the other region (a low defect region Rb) lattice defects D propagating from the first semiconductor layer hardly exist.

Abstract: This is a method for forming a recessed LOCOS isolation region, which includes the steps of forming a first silicon nitride layer between the pad oxide layer and a polysilicon buffer layer and a second nitride layer over the polysilicon buffer layer. In addition, the method for forming LOCOS isolation regions can include the additional steps of forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation regions have provided a low-profile recessed field oxide with reduced oxide encroachment into the active moat region.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: A manufacturing method that is capable of easily manufacturing a semiconductor device exhibits high reliability with no decrease in field isolation voltage from overetching. A field oxide is formed on a silicon substrate by a LOCOS method and a silicon nitride layer is then formed on the field oxide. Polysilicon is deposited on the surface of the field oxide and on the surface of a silicon nitride layer. The polysilicon layer is deposited thicker than a thickness of the silicon nitride layer. The polysilicon layer deposited on the silicon nitride layer and on the field oxide is removed by a polishing CMP method or the like, whereby the surface of the silicon nitride layer is exposed. A structure having the polysilicon layer existing on only the surface of the field oxide is then obtained by removing the silicon nitride layer. The polysilicon layer functions as a protective layer for the field oxide, thereby preventing the field oxide layer from being etched during overetching.

Abstract: A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite.

Abstract: A method of forming a nonvolatile semiconductor memory device of the present invention comprises: an isolation film formed on a semiconductor substrate of one conductivity type; a floating gate which is formed in an active region isolated by said isolation film so as to be disposed in a gap between adjacent isolation films and make each of end portions coincident with each end of said isolation film in a self-aligned manner; a tunnel oxide film which covers said floating gate; a control gate formed on said tunnel oxide film so as to comprise a region which overlaps said floating gate; a diffusion region of an opposite conductivity type and formed in a surface of the semiconductor substrate adjacent to said floating gate and the control gate.

Abstract: The present invention discloses an isolation method for fabricating isolation regions with less bird's peak sizes in semiconductor devices. A first pad oxide layer and a silicon nitride layer are first formed on a wafer substrate. After an undercut process is performed to the first pad oxide layer and forms a cave under the silicon nitride layer, a second pad oxide layer is formed over the wafer substrate. Next, a polysilicon layer is then deposited along the profile described above. Then, an anisotropic process is used to form sidewall spacers by etching the polysilicon layer. A recessed structure is then formed to the wafer substrate by a semi-isotropic process, and follows a thermal oxidation to fabricate isolation regions composed of silicon dioxide on the surface of the wafer substrate. The silicon nitride layer and the first pad oxide layer are then removed for continuing the active region processes.

Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.

Abstract: A method of semiconductor circuit fabrication utilizing the poly buffered LOCOS process is disclosed. Amorphous silicon is desirably formed by the decomposition of disilane at temperatures between 400-525.degree. C. The amorphous silicon exhibits less pits than what is produced by conventional processes. The absence of pits contributes to eventual substrate integrity.

Abstract: A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.

Abstract: A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.

Abstract: A new polysilicon-buffered field isolation process provides reduced stress during field oxidation and reduced bird's beak. Prior to forming the LOCOS masking stack conventionally used for field isolation, a polysilicon buffer layer is first formed on the semiconductor wafer. The polysilicon buffer layer relieves stress between the masking stack and semiconductor wafer similar to conventional Poly-buffered LOCOS processes, but additionally provides sacrificial silicon into which the bird's beak region extends. Subsequent deprocessing of mask and buffer layers removes a significant portion of the bird's beak region, thereby providing active areas having improved physical and electrical characteristics.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer (12) on a semiconductor substrate (10), and forming an oxidation masking layer (14) on the pad layer, wherein the pad layer relives stress from the oxidation masking layer. Next, the oxidation masking layer and the pad layer are patterned and etched to expose a portion of the substrate. After laterally removing the pad layer to form at least one undercut under the oxidation masking layer, a doped layer (16) is conformably formed on the oxidation masking layer, the pad layer, and the substrate, thereby refilling the undercut with the doped layer. Finally, the doped layer is anisotropically etched to form spacers (16A) on sidewalls of the oxidation masking layer and the pad layer, and the substrate is then thermally oxidized to form the isolation region (18) in the substrate, wherein doping atoms in the doped layer will diffuse into the substrate.

Abstract: Field isolation regions are formed using oxidation-resistant spacers or plugs that completely fill trenches within a semiconductor substrate prior to forming the field isolation regions. The spacers or plugs help to reduce encroachment of the field isolation regions under the spacers or plugs. The structure used as an oxidation mask for the field isolation process may include a silicon-containing member that is thicker than an overlying oxidation-resistant member. The thicker silicon-containing member may be capable of tolerating higher stress before defects in an underlying pad layer or substrate are formed.

Abstract: The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate comprising an multiple layer of films (105, 107, 109). These films include an oxide layer (105) overlying the substrate, a polysilicon layer (107) overlying the oxide layer, and a nitride layer (109) overlying the polysilicon layer. The invention also uses a step of removing a first portion of the nitride layer and a first portion of the polysilicon layer defined underlying the first portion of the nitride layer and removing a second portion of the nitride layer and a second portion of the polysilicon layer defined underlying the second portion of the nitride layer. This sequence of steps provides a partially completed semiconductor structure that defines isolation regions before forming well regions for active devices.

Abstract: An element isolation region is formed in a silicon substrate by initially depositing an insulating film and first nitride film thereon, forming an opening therethrough exposing the substrate, and etching the substrate to form a groove. A polysilicon film and second nitride film are successively deposited, and the second nitride film is anisotropically etched to expose the polysilicon film at the bottom of the groove. The silicon substrate is then thermally oxidized using the first and second nitride films as a mask to form the element isolation region. In other embodiments, an oxide film is formed at the bottom of the groove prior or subsequent to deposition of the polysilicon film.

Abstract: A semiconductor device manufacturing method capable of realizing a fine device isolation by stably suppressing the narrow channel effect and the reverse narrow channel effect in an N-channel MOS transistor. A patterned silicon nitride film 102 is formed, and after a P-type ion implanted layer 103 is formed, a field oxide film 105a is formed. In this process, re-distribution of the P-type impurity is caused by segregation, so that a P-type impurity concentration adjusting region 104a is formed at the surface of a P-type silicon substrate 101 in the proximity of a bird's beak of the field oxide film 105a.

Abstract: A method of forming an isolation region exerts no adverse influence upon steps after forming the isolation region and is, besides, capable of forming the isolation region having a narrow isolation width. After a mask has been formed of an oxidationproof material such as Si.sub.3 N.sub.4 on a silicon substrate, a field oxide is formed by effecting selective oxidation in a high-pressure dry oxygen atmosphere. Thereafter, a portion, protruded from the silicon substrate, of the formed field oxide is removed, thereby forming the isolation region.

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.

Abstract: Semiconductor integrated circuit processing is facilitated by an etch process illustratively applied to polysilicon and silicon nitride removal. The etch process illustratively comprises of the use of phosphoric acid with metal-containing additives to bring about an enhanced silicon etch rate effect.

Abstract: Disclosed is a device isolation technology for defining active region of a semiconductor device. An oxide is formed on a semiconductor substrate in a first reaction chamber where a first gas containing silicon and a purge gas exist therein. Afterwards, the first temperature of the first reaction chamber is changed to second temperature by injection of a purge gas. A buffer film is formed on the oxide film in the first reaction chamber at the second temperature by injection of a silicon gas. Thereafter, a silicon nitride layer is formed on the buffer film in a second reaction chamber by injecting a second gas containing silicon. Lastly, field oxides are formed by a LOCOS technique through pattering of the three layers and thermal oxidation of exposed portions.

Abstract: A semiconductor processing method of forming field oxide regions on a semiconductor substrate includes, i) providing an oxidation resistant mask over a layer of oxide over a desired active area region on a semiconductor substrate, the mask having a central region and opposed sidewall edges, the oxide layer being thinner in the central region than at the sidewall edges; and ii) oxidizing portions of the substrate unmasked by the mask to form field oxide regions on the substrate. The oxidation resistant mask can be provided by depositing and patterning a nitride layer atop a pad oxide layer. Substrate area not covered the mask is oxidized to produce an oxide layer outside of the mask which is thicker than the pad oxide layer. A thin layer of nitride can then be deposited, and anisotropically etched to produce masking spacers which cover the thicker oxide adjacent the original mask. Mask lifting during subsequent oxidation is restricted, thus minimizing bird's beak encroachment and substrate defects.

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

Abstract: A method for fabricating an isolation layer in a semiconductor device, includes the steps of forming a pad oxide layer on a substrate and sequentially forming a first thin nitride layer, a polysilicon layer and a second nitride layer on the pad oxide layer; selectively and sequentially dry-etching the second nitride layer, polysilicon layer, first nitride layer and pad oxide layer to expose a portion of the substrate corresponding to a field region and to form an active region pattern; growing an oxide layer on the exposed portion of the substrate in the field region; carrying out nitridation onto the polysilicon layer to form a nitride layer on the side of the active region pattern; and performing field oxidation to form a field oxide layer in the field region.

Abstract: A method for forming a field oxide film includes the steps of: (i) laminating a gate insulating film, a polysilicon layer and a first silicon nitride film over the entire surface of a semiconductor substrate in this order; (ii) patterning the gate insulating film, the polysilicon layer and the first silicon nitride film to a desired shape; (iii) forming a sidewall spacer of a second silicon nitride film on a side wall of the gate insulating film, the polysilicon layer and the first silicon nitride film; (iv) selectively etching a portion of the semiconductor substrate with the first silicon nitride film and the sidewall spacer used as a mask; and (v) forming a field oxide film on the etched portion of the semiconductor substrate in a self-aligned manner relative to the polysilicon layer. According to the invention, lifting up of the polysilicon layer caused by the bird's beak of the field oxide film coming under the polysilicon layer can be reduced.

Abstract: A method for fabrication of modified poly-buffered LOCOS without positive charges trapping at the beak of the field oxide. The method employs DIW (Deionized Water) to be sprayed onto the wafer before gate electrode forming to eliminate the trapping of positive charges and reduce the undesired charge breakdown thereby increasing the yield of devices not containing this defect.

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxi

Abstract: A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropically etched to form spacers on the side of the nitride layer portions, which are also in contact with the silicon substrate, the etching continuing into the silicon substrate. Field oxidation is then undertaken, with the polysilicon spacers being oxidized, as is a portion of the silicon substrate, the spacers causing initial oxidation during field oxide growth to be removed from the sides of the nitride layer portions, so that encroachment of the oxide under the nitride layer portions is avoided.

Abstract: There is disclosed a method for making a field oxide, by which wafer warpage is minimized when a local oxidation of silicon process is applied for a large wafer. A material layer having a compressive stress and a nitride are laminated over the back side of a wafer, so that the compressive stress of the material layer complementarily interacts with the tensile stress of the nitride.

Abstract: Methods of forming field oxide isolation regions in a semiconductor substrate include the steps of exposing residual polysilicon defects contained within preliminary field oxide isolation regions and then performing a cleaning step to etch and reduce the size of the exposed defects (or eliminate the defects altogether). The preliminary field oxide isolation regions are then oxidized to preferably convert any remaining polysilicon defects into silicon dioxide and then a final oxide etching step is performed to define the shapes of the final field oxide isolation regions. Preferably, a pad oxide layer is formed on a face of a semiconductor substrate and then a masking layer is formed on the pad oxide layer, opposite the face of the substrate. The masking layer is then patterned to define an opening therein which exposes an upper surface of the pad oxide layer.

Abstract: A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a portion of the masking stack on the bottom surface prior to forming isolation regions on the top surface of the semiconductor wafer. In one embodiment, silicon nitride is formed on the top and the bottom surface of a silicon wafer. The silicon nitride is then patterned and etched on the top surface of the wafer to expose regions of the underlying silicon for field oxide formation. Prior to the field oxidation formation on the top side of the wafer, the silicon nitride layer on the bottom side of the wafer is removed so that a layer of silicon dioxide is formed on the bottom surface of the wafer during field oxidation formation.

Abstract: A method for forming an integrated circuit isolation layer includes the steps of forming a patterned masking layer of a semiconductor substrate, forming an oxygen diffusing layer on the patterned masking layer and the exposed portion of the semiconductor substrate, and forming an isolation layer on the exposed portion of the substrate. In particular, the oxygen diffusing layer can be a layer of SiON, and the oxygen diffusing layer can have a thickness in the range of 30 .ANG. to 150 .ANG.. The oxygen diffusing layer and the mask layer can then be removed completing the isolation layer.

Abstract: Disclosed is a method for the isolation between active regions of a semiconductor device. The method provides an poly buffered local oxidation of silicon(PBLOCOS) technology. In this method, a non-doped polysilicon layer and the overlying amorphous silicon layer are used as a buffer layer. To form a field oxide region for isolation between semiconductor devices, first a pad oxide film, the buffer layer, silicon nitride layer are formed on a semiconductor substrate. Thereafter, patterning is performed to expose the pad oxide film at a selected region. Lastly, thermal oxidation is performed, thereby the exposed pad oxide is grown to form the field oxide.

Abstract: An improved local oxidation of silicon (LOCOS) method with recessed silicon substrate and double polysilicon/silicon nitride spacer is disclosed. The present invention includes forming a pad oxide layer on a semiconductor substrate and then forming a first silicon nitride layer on the pad oxide layer. An active region is defined by patterning and etching the pad oxide layer and the first silicon nitride layer using a photoresist mask. Thereafter, a silicon oxide layer and a second silicon nitride layer is formed. Next, a polysilicon layer is deposited over the second silicon nitride layer. The polysilicon layer, the second silicon nitride layer, and the silicon oxide layer are etched back to form a double polysilicon/silicon nitride spacer. Finally, an isolation region in the substrate is formed.

Abstract: In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.

Abstract: A method for forming wells of a semiconductor device, being capable of removing the topology between n- and p-well regions. The method of the present invention provides a twin well structure wherein the n-well region has a higher level than the p-well region. This method includes the steps of sequentially forming a buffering film and an oxidizable film over a semiconductor substrate, forming an anti-oxidation film over the oxidizable film, removing a portion of the anti-oxidation film disposed at a first well region of the semiconductor substrate, implanting impurity ions in the first well region of the semiconductor substrate and annealing the resulting structure, thereby forming a first well in the substrate, removing the anti-oxide film and the oxidizable film both disposed at a second well region of the substrate, and implanting impurity ions in the second well region of the semiconductor substrate and annealing the resulting structure, thereby forming a second well in the substrate.

Abstract: A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a polysilicon layer is deposited on a laminate comprising a substrate having thereon a pad oxide, and the stacked layers on the pad oxide. An overhang layer is deposited on the polysilicon layer, and a photo-resist mask which masks the active regions is then applied so as to remove the unmasked overhang layer and the unmasked polysilicon layer. The resultant structure is isotropically etched to partially undercut the vertical portions of the polysilicon layer under the overhang layer so as to form an overhang. The photo-resist is stripped, and the stacked layers not covered by the overhang layer are etched anisotropically. The channel-stop ions are implanted, and the overhang layer is removed.

Abstract: According to this method, before a silicon nitride (Si.sub.3 N.sub.4) layer having a thickness of about 200 nm and serving as a field oxidation (selective oxidation) mask is formed, nitrogen-doped amorphous silicon is deposited to form a silicon layer having a thickness of about 50 nm and serving as an underlying layer of the silicon nitride layer.

Abstract: A semiconductor processing method of forming a field oxide region on a semiconductor substrate includes, a) providing a patterned first masking layer over a desired active area region of a semiconductor substrate, the first masking layer having at least one side edge; b) providing a silicon sidewall spacer over the side edge of the patterned first masking layer, the silicon sidewall spacer having a laterally outward projecting foot portion; c) oxidizing the substrate and the silicon sidewall spacer to form a field oxide region on the substrate; d) stripping the first masking layer from the substrate; and e) providing a gate oxide layer over the substrate. The invention enables taking advantage of process techniques which minimize the size of field oxide bird's beaks without sacrificing upper field oxide topography.

Abstract: In a method of manufacturing a semiconductor device, after forming a poly silicon film 54 on a surface of a silicon substrate 51, a silicon nitride film 55 is formed in accordance with a desired pattern and a local oxidation process is carried out to form a field oxide film 56 having a large thickness. Then, after removing the silicon nitride film 55, the poly silicon film 54 is fully converted in to a silicon oxide film 58 and then the thus converted silicon oxide film is removed by wet etching to expose a clean surface of the silicon substrate 51. The poly silicon film does not constitute an oxygen source, so that during the local oxidation, a lateral diffusion of oxygen is prevented and a generation of bird's beak can be suppressed. Further, the poly silicon film serves as a buffer, no stress remains in the surface of the silicon substrate.