Abstract: A flexible substrate includes a first part and a second part at a side surface of the first part which is perpendicular to a plane in which the first part extends. An elastic modulus of the first part is less than an elastic modulus of the second part, and holes are distributed in the flexible substrate.

Abstract: A thin film transistor includes a substrate, a gate electrode, a buffer layer, a gate insulating layer, an active layer, an etching stop layer, a source electrode and a drain electrode. The gate electrode is formed on the substrate. The buffer layer partially covers both side portions of the gate electrode. The gate insulating layer covers the gate electrode and the buffer layer. The active layer is formed on the gate insulating layer. The etching stop layer is formed on the active layer, and has a first opening and a second opening on the active layer. The source electrode is formed on the etching stop layer, and contacts with the active layer through the first opening. The drain electrode is formed on the etching stop layer, and is contacted with the active layer through the second opening.

Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.

Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: In a specific embodiment, the present invention provides an integrated circuit device. The device includes a base substrate having a surface region and an interlayer dielectric material overlying the surface region. The device also has a thickness of single crystal silicon material overlying the interlayer dielectric material. In one or more embodiments, the thickness of single crystal silicon material has a front region and a backside region. The front region faces the interlayer dielectric material. In a preferred embodiment, the device has a plurality of transistor devices spatially arranged in the thickness of silicon crystal silicon material. Each of the transistor devices has a gate structure within a region of the interlayer dielectric material. The device also has an enclosure housing configured to form a cavity between the backside region of the thickness of silicon material and an upper inside region of the enclosure housing.

Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: Provided is a method of implanting dopant ions to an integrated circuit. The method includes forming a first pixel and a second pixel in a substrate, forming an etch stop layer over the substrate, forming a hard mask layer over the etch stop layer, patterning the hard mask layer to include an opening between the first pixel and the second pixel, and implanting a plurality of dopants through the opening to form an isolation feature.

Abstract: A semiconductor device is manufactured by defining a groove in a semiconductor substrate, where the groove includes an upper portion and a lower portion, among other steps. A sacrificial layer is then formed to selectively fill the lower portion of the groove. Impurity ions are implanted into the semiconductor substrate while the lower portion of the groove is filled with the sacrificial layer. The sacrificial layer is then removed, and a gate is formed on the groove. In the method for manufacturing the semiconductor device, impurities can be doped at a uniform concentration in the channel area of the semiconductor device.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the device, which suppresses off-current by improving the problem of leakage current due to hump characteristics, making it possible to maximize the reliability of the device. Embodiments relate to a method for manufacturing a semiconductor device including forming a well having two ends in a semiconductor substrate. A shallow trench isolation (STI) is formed by etching both ends of the well and the semiconductor substrate adjacent both ends of the well. A gate oxide film and a photoresist film are formed over the upper surface of the semiconductor substrate including the STI. The photoresist film is patterned for an impurity ion implant into one side area including the edge of the side wall of the STI. A barrier area is formed by implanting an impurity ion into one side area including the side wall edge of the STI using the patterned photoresist film as a mask.

Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

Abstract: A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A method is presented describing in situ preparation of the titania-based sol-gel PDMS coating and its immobilization on the inner surface of a fused silica microextraction capillary. Sol-gel titania-poly (dimethylsiloxane) (TiO2-PDMS) coating was developed for capillary microextraction (CME) to perform on-line preconcentration and HPLC analysis of trace impurities in aqueous samples. The sol-gel titania-based coatings demonstrated strong pH stability and enhanced extraction capability over other commercially availble GC coatings. Extraction characteristics of a sol-gel titania-PDMS capillary remained practically unchanged after continuous rinsing with a 0.1 M NaOH solution (pH=13) for 12 hours.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device has a channel termination region for using a trench (30) filled with field oxide (32) and a channel stopper ring (18) which extends from the first major surface (8) through p-well (6) along the outer edge (36) of the trench (30), under the trench and extends passed the inner edge (34) of the trench. This asymmetric channel stopper ring provides an effective termination to the channel (10) which can extend as far as the trench (30).

Abstract: A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding the central region on the surface of the wafer. Subsequently, the coating material layer positioned in the bevel region is removed according to the reference pattern.

Abstract: Disclosed is a semiconductor device, and more particularly, a manufacturing method of a high voltage semiconductor device. The method includes: forming a semiconductor substrate having a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage device; forming an oxide film on the substrate; and forming an insulating film on the oxide film. After removing the insulating film, the method includes forming a plurality of shallow trench isolations (STI's) in the areas of the substrate; forming a nitride layer on the substrate and on STIs; sequentially forming a plurality of wells and drift areas by implanting an impurity ion into the high voltage area; and sequentially forming the plurality of wells and the drift areas by implanting an impurity ion into the low voltage area. A system on chip (SOC) process may thus be simplified.

Abstract: A method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby, in which the method includes forming an isolation layer defining first and second active regions in a semiconductor substrate. A passivation layer is formed on the substrate having the isolation layer. A first patterning process is carried out that etches the passivation layer on the first active region to form a first opening exposing the first active region, and a first dielectric layer is formed in the exposed first active region. A second patterning process is carried out, which etches the passivation layer on the second active region to form a second opening exposing the second active region, and a second dielectric layer is formed in the exposed second active region.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying doped region. The drift region is located in the substrate under the field isolation layer and connects with the channel region and the at least one doped region. The modifying doped region is at the periphery of the at least one doped region.

Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

Abstract: An object of the present invention is to provide a method of transferring an object to be peeled onto a transferring member in a short time without imparting damage to the object to be peeled within a laminate. Also, another object of the present invention is to provide a method of manufacturing a semiconductor device in which a semiconductor element manufactured on a substrate is transferred onto a transferring member, typically, a plastic substrate. The methods are characterized by including: forming a peeling layer and an object to be peeled on a substrate; bonding the object to be peeled and a support through a two-sided tape; peeling the object to be peeled from the peeling layer by using a physical method, and then bonding the object to be peeled onto a transferring member; and peeling the support and the two-sided tape from the object to be peeled.

Abstract: A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon substrate and trenches of required dimensions are etched into silicon. After forming an oxide liner on trench surfaces, boron ions are implanted in areas around the trenches such that heavily doped p+ regions are formed. The oxide liner is anisotropically etched with a reactive ion etching process such that only the silicon surface at trench bottom is exposed, leaving the oxide liner on trench walls. Epitaxial silicon is then deposited selectively on exposed single crystal silicon surface so as to fill the trenches. After removing the hard mask, trenches are masked with photo-resist pattern and the wafer is anodically etched in an aqueous bath of HF to form a buried porous silicon layer under and around the trenches. After removing the mask, the porous silicon is then oxidized.

Abstract: One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth within the semiconductor substrate forms a local oxide region within the semiconductor substrate. A portion of the substrate forms a semiconductor layer over the local oxide region. In various embodiments, the semiconductor layer is an ultra-thin semiconductor layer having a thickness of approximately 300 ? or less. The oxide growth strains the semiconductor layer. An active region, including the body region, of the transistor is formed in the strained semiconductor layer. Other aspects are provided herein.

Abstract: Disclosed is a method of manufacturing a high voltage transistor in a flash memory device. The method can prohibit a punch leakage current of an isolation film while satisfying active characteristics of the high voltage transistor without the need for a mask process for field stop of the high voltage transistor ion implantation process and a mask removal process.

Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

Abstract: Within a method for forming an isolation region within a semiconductor substrate, there is, prior to forming the isolation region within an isolation trench formed adjoining an active region of a semiconductor substrate, implanted a dopant into a corner of the active region. The corner of the active region is uncovered by laterally etching an isolation trench mask to form a laterally etched isolation trench mask which serves as an ion implantation mask layer when implanting the dopant into the corner of the active region. The method provides for enhanced performance, and minimal affect of a semiconductor device formed within the active region of the semiconductor substrate.

Abstract: The present invention is generally directed to various methods of controlling Vss implants on memory devices, and a system for performing same. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate, measuring at least one physical characteristic of at least one of the trenches and determining at least one parameter of a VSS implant process to be performed on the substrate based upon the measured at least one physical characteristic of at least one trench.

Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

Abstract: An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.

Abstract: A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circuit; forming the memory cells; exposing a surface of diffusion regions in the peripheral circuit after forming the memory cells; and forming a covering conductive layer on the exposed region of the diffusion regions in peripheral circuit. A semiconductor memory device produced by such a process has memory area having a good data retention due to a low junction leakage in the diffusion regions of the memory cells, whereas it has a high processing speed peripheral circuit due to a low resistance of the diffusion regions of the peripheral circuit.

Abstract: A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is substantially blocked from the second transistor area (302). The angled implant forms pocket regions in the first transistor area (304). The same masking layer (214) may then be used to implant source and drain extension regions in both the first and second transistor areas (304, 302).

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.

Abstract: A method of fabricating a feature on a substrate is disclosed. In a described embodiment the feature is the gate electrode of an MOS transistor. In this embodiment a polysilicon layer is formed on the substrate. Next, an edge definition layer of silicon nitride is formed on the feature layer. Then, a patterned edge definition layer of silicon dioxide is formed on the first edge definition layer. Then, a silicon nitride spacer is formed adjacent to an edge of the patterned second edge definition layer. Finally, the polysilicon layer is etched, forming the transistor gate electrode from the polysilicon that remains under the spacer.

Abstract: An ion implantation method which can accurately control the effective dose amount even in ion implantation at a very low energy. This ion implantation method comprises the steps of carrying out preamorphization ion implantation for a semiconductor substrate in an ion implantation apparatus; then cleaning the surface of semiconductor substrate in a cleaning apparatus so as to eliminate an oxidized film; and thereafter carrying out ion implantation again in the ion implantation apparatus under a low implantation energy so as to form a shallow junction in the semiconductor substrate. As a consequence, the influence of the oxidized film formed by preamorphization ion implantation can be suppressed, whereby the effective dose can be controlled accurately.

Abstract: Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.

Abstract: This invention concerns a process of forming a polarizable layer in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. This process comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5-50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25-300 degrees Celsius. After implantation, an annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Abstract: A method of forming a SOI type semiconductor device comprises forming a first trench in a SOI layer forming a portion of an isolation layer region between an element region and a ground region by etching the SOI layer of a SOI type substrate using an etch stop layer pattern as an etch mask, forming an impurity layer in or on a bottom surface of the first trench, forming a second trench exposing a buried oxide layer in the SOI layer in the remainder of the isolation layer region except the portion thereof between the element region and the ground region, and forming an isolation layer by depositing an insulation layer over the SOI substrate having the first and second trenches. The impurity layer can be formed by depositing a SiGe single crystal layer in the bottom surface of the first trench. Also, the impurity layer can be formed by implanting ions in the bottom surface of the first trench.

Abstract: A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.

Abstract: A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, sometimes denoted a bird's beak region. Wherein the transition region is implanted with germanium and boron, to prevent formation of leakage paths between active devices, or within an active device. The implanted area can be further limited to that area of the transition region that is adapted to be covered by a gate material, such as polysilicon.

Abstract: A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

Abstract: The present invention provides a manufacturing environment (110) for a wafer fab, and an SPC environment (112) for setting control limits and acquiring metrology data of production runs. A computation environment (114) processes the SPC data, which are then analyzed in an analysis environment (116). An MES environment (118) evaluates the analysis and automatically executes a process intervention if the process is outside the control limits. Additionally, the present invention provides for an electrical power management system, a spare parts inventory and scheduling system and a wafer fab efficiency system. These systems employ algorithms (735, 1135 and 1335).

Abstract: The formation of the isolating region includes ion implantation in the voluminal part, followed by annealing of said implanted voluminal part (7) of the substrate (1).

Abstract: A semiconductor wafer on which elements have been formed is diced and a rear surface of the semiconductor wafer is ground by a dicing before grinding method to form discrete semiconductor chips. The discrete semiconductor chips are adhered to an adhesive film and then the surface of the adhesive film is removably affixed to a dicing tape. After this, any excess portions of the adhesive film disposed between the respective semiconductor chips are removed.