Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: An improved method for forming a triple well of a semiconductor device which is capable of more simply and easily forming a triple well without removing an anti-oxidation film.

Abstract: A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An active pattern is formed in the cell region and a first field ion-implanted region in a first conductive well of the cell region. Side wall spacers are formed on each side wall of the active pattern in the cell region. An active pattern is formed in the peri region by selectively etching the first anti-oxidation film and the insulation film so as to expose a certain surface portion of the peri region substrate therethrough. A first field ion-implanting region is formed in a first conductive well of the peri region by ion-implanting highly concentrated first conductive impurities through the exposed substrate and a second field ion-implanted region in a second conductive well of the peri region.

Abstract: Short channel MOS semiconductor devices are produced by implanting impurity ions through gate electrode and gate oxide layers, before patterning the gate electrode, using a composite mask of silicon oxide and silicon nitride, to form a shallow channel region in the substrate for adjusting the threshold voltage and a deeper well region for preventing punch through. In another embodiment, impurity ions are implanted to form lightly doped and heavily doped source/drain regions in a single ion implantation step using a thermally grown oxide region having bird's beaks as a mask. Self-aligned lightly doped regions are formed under the bird's beaks.

Abstract: The present invention relates to a high voltage transistor of a semiconductor memory device, and more particularly to a high voltage transistor which improves element isolation and breakdown voltage characteristics thereof.

Abstract: This invention discloses a method of manufacturing a semiconductor device, especially a method of forming field isolation, in which a portion of an active region around a field oxide film is highly-doped with the same type impurities as channel-stop impurity ions so that it changes a low-doped channel-stop region which results from a high temperature of field oxidation to a high-doped channel-stop region to prevent field inversion in device operation.

Abstract: Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by implanting first conductivity type impurities at a first dose level into a face of a semiconductor substrate and then forming respective field oxide isolation regions at the locations where the first channel-stop isolation regions have been implanted. A conductive layer, which contacts active regions of the substrate and covers the field oxide isolation regions, is then patterned over the field oxide isolation regions to expose central portions of the upper surfaces of the field oxide isolation regions.

Abstract: A method for forming wells of a semiconductor device, being capable of removing the topology between n- and p-well regions. The method of the present invention provides a twin well structure wherein the n-well region has a higher level than the p-well region. This method includes the steps of sequentially forming a buffering film and an oxidizable film over a semiconductor substrate, forming an anti-oxidation film over the oxidizable film, removing a portion of the anti-oxidation film disposed at a first well region of the semiconductor substrate, implanting impurity ions in the first well region of the semiconductor substrate and annealing the resulting structure, thereby forming a first well in the substrate, removing the anti-oxide film and the oxidizable film both disposed at a second well region of the substrate, and implanting impurity ions in the second well region of the semiconductor substrate and annealing the resulting structure, thereby forming a second well in the substrate.

Abstract: A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a polysilicon layer is deposited on a laminate comprising a substrate having thereon a pad oxide, and the stacked layers on the pad oxide. An overhang layer is deposited on the polysilicon layer, and a photo-resist mask which masks the active regions is then applied so as to remove the unmasked overhang layer and the unmasked polysilicon layer. The resultant structure is isotropically etched to partially undercut the vertical portions of the polysilicon layer under the overhang layer so as to form an overhang. The photo-resist is stripped, and the stacked layers not covered by the overhang layer are etched anisotropically. The channel-stop ions are implanted, and the overhang layer is removed.

Abstract: A process for fabricating double well regions for a semiconductor device having a first well region of a first type and a second well region of a second type on the substrate is disclosed. The process comprises the steps of first implanting impurities of the first type into the substrate. Then a shielding layer covering the location designated for the first well region of the first type on the substrate is formed. Impurities of the second type are then implanted into the substrate at locations not covered by the shielding layer and designated for the formation of the second well region of the second type. Finally, the impurities of both the first and the second type are driven into a designated depth of the substrate by a heating process to form the first well region of the first type and the second well region of the second type.