Having Enclosed Cavity Patents (Class 438/456)
  • Patent number: 10159975
    Abstract: A microfluidic device includes a first substrate made of a first polymer material and a second substrate made of a second polymer material, the first and second substrates having respective bonding surfaces, at least one of the bonding surfaces having channel formations so that, when the bonding surfaces are bonded by surface deformation to one another, the bonded first and second substrates and the channel formations form at least part of a microfluidic channel network comprising a plurality of microfluidic channels, wherein one or more indicator pits, separate to the channel formations defining the microfluidic channel network, are formed in at least one of the bonding surfaces, so that surface deformation caused by the bonding process causes a change of configuration of the one or more indicator pits.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 25, 2018
    Assignee: STRATEC CONSUMABLES GMBH
    Inventors: Gottfried Reiter, Dario Borovic
  • Patent number: 9969614
    Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 9653312
    Abstract: A method of forming a sealing structure for a bonded wafer is provided. The method includes providing the lower wafer and the upper wafer, forming a sealing material layer on each of the lower wafer and the upper wafer, forming a mask layer on the sealing material layer on each of the lower wafer and the upper wafer, etching the sealing material layer using the mask layer as an etch mask, so as to form a first protrusion at an edge of the lower wafer and a second protrusion at an edge of the upper wafer, and bonding the first protrusion and the second protrusion together to form the sealing structure. The sealing structure encloses a gap between the lower wafer and the upper wafer at an edge of the bonded wafer, so as to form a hermetically sealed cavity at the edge of the bonded wafer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 16, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yuankun Hou, Kuanchieh Yu, Yu Hua, Yuelin Zhao
  • Patent number: 9613926
    Abstract: Bonded structures and method of forming the same are provided. A conductive layer is formed on a first surface of a bonded structure, the bonded structure including a first substrate bonded to a second substrate, the first surface of the bonded structure being an exposed surface of the first substrate. A patterned mask having first openings and second openings is formed on the conductive layer, the first openings and the second openings exposing portions of the conductive layer. First portions of first bonding connectors are formed in the first openings and first portions of second bonding connectors are formed in the second openings. The conductive layer is patterned to form second portions of the first bonding connectors and second portions of the second bonding connectors. The bonded structure is bonded to a third substrate using the first bonding connectors and the second bonding connectors.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai
  • Patent number: 9484885
    Abstract: A method for manufacturing an elastic wave device includes a step of preparing a supporting substrate, a step of forming a high-acoustic-velocity film on the supporting substrate and in which an acoustic velocity of a bulk wave propagating therein is higher than an acoustic velocity of an elastic wave propagating in a piezoelectric film, a step of forming a low-acoustic-velocity film on the high-acoustic-velocity film and in which an acoustic velocity of a bulk wave propagating therein is lower than an acoustic velocity of a bulk wave propagating in the piezoelectric film, a step of forming the piezoelectric film on the low-acoustic-velocity film, and a step of forming an IDT electrode on a surface of the piezoelectric film.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: November 1, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Munehisa Watanabe, Hideki Iwamoto, Hajime Kando, Syunsuke Kido
  • Patent number: 9368389
    Abstract: A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 14, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 9362139
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: June 7, 2016
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Tomas Bauer
  • Patent number: 9318461
    Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 19, 2016
    Assignee: XINTEC INC.
    Inventors: Chun-Wei Chang, Kuei-Wei Chen, Chia-Ming Cheng, Chia-Sheng Lin, Chien-Hui Chen, Tsang-Yu Liu
  • Patent number: 9040355
    Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Philip H. Bowles, Paige M. Holm, Stephen R. Hooper, Raymond M. Roop
  • Patent number: 9040386
    Abstract: A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 26, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Xuejun Ying, Li Li, Amit S. Kelkar, Brian S. Poarch
  • Patent number: 9034729
    Abstract: An object of the invention is to provide a smaller semiconductor device of which the manufacturing process is simplified and the manufacturing cost is reduced and a method of manufacturing the same. Furthermore, an object of the invention is to provide a semiconductor device having a cavity. A first supporting body 5 having a penetration hole 6 penetrating it from the front surface to the back surface is attached to a front surface of a semiconductor substrate 2 with an adhesive layer 4 being interposed therebetween. A device element 1 and wiring layers 3 are formed on the front surface of the semiconductor substrate 2. A second supporting body 7 is attached to the first supporting body 5 with an adhesive layer 8 being interposed therebetween so as to cover the penetration hole 6. The device element 1 is sealed in a cavity 9 surrounded by the semiconductor substrate 2, the first supporting body 5 and the second supporting body 7.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hiroshi Yamada, Katsuhiko Kitagawa, Kazuo Okada, Yuichi Morita, Hiroyuki Shinogi, Shinzo Ishibe, Yoshinori Seki, Takashi Noma
  • Patent number: 9006878
    Abstract: A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: April 14, 2015
    Assignee: Miradia Inc.
    Inventors: Xiao “Charles” Yang, Dongmin Chen, Philip Chen
  • Patent number: 9006015
    Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Kai-Chih Liang, Chung-Hsien Lin, Chun-wen Cheng
  • Patent number: 8993409
    Abstract: A method for fabricating air media layer within the semiconductor optical device is provided. The step of method includes a substrate is provided, a GaN thin film is formed on the substrate, a sacrificial layer is formed on the GaN thin film, and a nitride-containing semiconductor layer is formed on the sacrificial layer. The semiconductor optical device is immersed with an acidic solution to remove the portion of sacrificial layer to form an air media layer around the residual sacrificial layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: March 31, 2015
    Assignee: National Chiao Tung University
    Inventors: Tien-Chang Lu, Huei-Min Huang, Hao-Chung Kuo, Shing-Chung Wang
  • Patent number: 8993379
    Abstract: A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Evan G. Colgan, Jae-Woong Nah
  • Publication number: 20150076667
    Abstract: A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall.
    Type: Application
    Filed: February 10, 2014
    Publication date: March 19, 2015
    Applicant: Hamilton Sundstrand Corporation
    Inventor: Scott R. Bouras
  • Patent number: 8980669
    Abstract: The present invention discloses an adhesive-free method for preparation of micro electro-mechanical structure, comprising forming a micro electro-mechanical structure on a first substrate, forming an enclosing space for immersing liquid on the first or second substrate, and applying pressure to fix the first and second substrate. Before applying the pressure, the assembly including the two substrates is flipped, to make the contact surface immersed by the immersing liquid.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Sagatek Co., Ltd.
    Inventors: Jung-Hsiang Chen, Cheng-Szu Chen, Bo-Ting Chen
  • Patent number: 8975105
    Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 10, 2015
    Assignee: Raytheon Company
    Inventor: Cody B. Moody
  • Patent number: 8975092
    Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventors: Chihiro Uchibori, Michael G. Lee
  • Patent number: 8956951
    Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 17, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Masahiro Kato, Masayuki Imai
  • Patent number: 8941442
    Abstract: A method of fabricating one or more vapor cells comprises forming one or more vapor cell dies in a first wafer having a first diameter, and anodically bonding a second wafer to a first side of the first wafer over the vapor cell dies, the second wafer having a second diameter. A third wafer is positioned over the vapor cell dies on a second side of the first wafer opposite from the second wafer, with the third wafer having a third diameter. A sacrificial wafer is placed over the third wafer, with the sacrificial wafer having a diameter that is larger than the first, second and third diameters. A metallized bond plate is located over the sacrificial wafer. The third wafer is anodically bonded to the second side of the first wafer when a voltage is applied to the metallized bond plate while the sacrificial wafer is in place.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: January 27, 2015
    Assignee: Honeywell International Inc.
    Inventors: Daniel W. Youngner, Jeff A. Ridley, Son T. Lu
  • Patent number: 8936998
    Abstract: A device is provided with: a first substrate mainly containing silicon dioxide; a second substrate mainly containing silicon, compound semiconductor, silicon dioxide or fluoride; and a bonding functional intermediate layer arranged between the first substrate and the second substrate. The first substrate is bonded to the second substrate thorough room temperature bonding in which a sputtered first surface of the first substrate is contacted with a sputtered second surface of the second substrate via the bonding functional intermediate layer. Here, the material of the bonding functional intermediate layer is selected from among optically transparent materials which are oxide, fluoride, or nitride, the materials being different from the main component of the first substrate and different from the main component of the second substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 20, 2015
    Assignees: Mitsubishi Heavy Industries, Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Jun Utsumi, Takayuki Goto, Kensuke Ide, Hideki Takagi, Masahiro Funayama
  • Patent number: 8927391
    Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Sheng-Yu Wu, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chih-Wei Lin, Wen-Hsiung Lu, Hsiu-Jen Lin, Bor-Ping Jang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8921203
    Abstract: A method for forming a semiconductor device includes providing a substrate having a first major surface and a second major surface, removing a first portion of the substrate to form a cavity at the first major surface of the substrate, bonding the first major surface of the substrate to a carrier substrate after forming the cavity, and reducing a thickness of the substrate. The method further includes forming a first accelerometer device at the second major surface such that at least a portion of the first accelerometer device is over the cavity and forming a second accelerometer device at the second major surface such that the second accelerometer device is not disposed over the cavity.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lisa H. Karlin, Hemant D. Desai, Kemiao Jia
  • Patent number: 8912098
    Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Publication number: 20140342479
    Abstract: A method of fabricating a composite semiconductor structure includes providing a first substrate comprising a first material and having a first surface and forming a plurality of pedestals extending to a predetermined height in a direction normal to the first surface. The method also includes attaching a plurality of elements comprising a second material to each of the plurality of pedestals, providing a second substrate having one or more structures disposed thereon, and aligning the first substrate and the second substrate. The method further includes joining the first substrate and the second substrate to form the composite substrate structure and removing at least a portion of the first substrate from the composite substrate structure.
    Type: Application
    Filed: April 24, 2014
    Publication date: November 20, 2014
    Applicant: Skorpios Technologies, Inc.
    Inventor: Elton Marchena
  • Patent number: 8887382
    Abstract: The invention relates to a pendulous accelerometer including a pendulous electrode formed in a substrate, at least one counter electrode, and an encapsulation cover. The at least one counter electrode is formed under the cover, and spacers are positioned between the cover and the substrate.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: November 18, 2014
    Assignee: MEMSCAP
    Inventors: Béatrice Wenk, Jean-Francois Veneau, Greg Hames
  • Patent number: 8877609
    Abstract: A method for manufacturing a bonded substrate that has an insulator layer in part of the bonded substrate includes: partially forming a porous layer or forming a porous layer whose thickness partially varies on a bonding surface of the base substrate; performing a heat treatment to the base substrate having the porous layer formed thereon to change the porous layer into the insulator layer, and thereby forming the insulator layer whose thickness partially varies on the bonding surface of the base substrate; removing the insulator layer whose thickness varies by an amount corresponding to a thickness of a small-thickness portion by etching; bonding the bonding surface of the base substrate on which an unetched remaining insulator layer is exposed to a bond substrate; and reducing a thickness of the bonded bond substrate and thereby forming a thin film layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 4, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tsuyoshi Ohtsuki, Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Kyoko Mitani
  • Patent number: 8871588
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8871607
    Abstract: A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 28, 2014
    Assignees: S.O.I. TEC Silicon on Insulator Technologies, Commissariat a l'Energie Atomique
    Inventors: Thomas Signamarcheix, Franck Fournel, Hubert Moriceau
  • Patent number: 8871551
    Abstract: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ wafer bonding encapsulation techniques.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: October 28, 2014
    Assignee: SiTime Corporation
    Inventors: Aaron Partridge, Markus Lutz, Pavan Gupta
  • Patent number: 8865564
    Abstract: A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 21, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Audrey Berthelot, Jean-Philippe Polizzi
  • Patent number: 8866238
    Abstract: Hybrid integrated components including an MEMS element and an ASIC element are described, whose capacitor system allows both signal detection with comparatively high sensitivity and sensitive activation of the micromechanical structure of the MEMS element. The hybrid integrated component includes an MEMS element having a micromechanical structure which extends over the entire thickness of the MEMS substrate. At least one structural element of this micromechanical structure is deflectable and is operationally linked to at least one capacitor system, which includes at least one movable electrode and at least one stationary electrode. Furthermore, the component includes an ASIC element having at least one electrode of the capacitor system. The MEMS element is mounted on the ASIC element, so that there is a gap between the micromechanical structure and the surface of the ASIC element.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 21, 2014
    Assignee: Robert Bosch GmbH
    Inventor: Johannes Classen
  • Patent number: 8865521
    Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Kim Hong Chen, Shang-Yun Hou, Chao-Wen Shih, Cheng-Chieh Hsieh, Chen-Hua Yu
  • Patent number: 8841201
    Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Hsin-Ting Huang, Lin-Min Hung, Yao-Te Huang, Chin-Yi Cho
  • Publication number: 20140264759
    Abstract: A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Christopher R. KOONTZ, Tse E. WONG, Jason G. MILNE
  • Patent number: 8835281
    Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 16, 2014
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Chris Brindle, Michael A. Stuber, Stuart B. Molin
  • Patent number: 8835227
    Abstract: A semiconductor device is manufactured by forming a first dielectric film on a substrate, forming an aperture in the first dielectric film, mounting a semiconductor chip in the aperture, forming a second dielectric film on the first dielectric film and the semiconductor chip, and forming an interconnection wiring structure on the second dielectric film. The second dielectric film secures the semiconductor chip without the need to etch the substrate or use an adhesive die attachment film.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: September 16, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hirokazu Saito
  • Patent number: 8822251
    Abstract: The present invention provides a MEMS and a sensor having the MEMS which can be formed without a process of etching a sacrifice layer. The MEMS and the sensor having the MEMS are formed by forming an interspace using a spacer layer. In the MEMS in which an interspace is formed using a spacer layer, a process for forming a sacrifice layer and an etching process of the sacrifice layer are not required. As a result, there is no restriction on the etching time, and thus the yield can be improved.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi, Fuminori Tateishi
  • Publication number: 20140231967
    Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Co., Ltd.
  • Publication number: 20140231995
    Abstract: A device including a first substrate in which a functional element and an electrode are formed; a second substrate in which a through electrode is formed; a joining material that joins the first substrate and the second substrate while reserving a predetermined space between the functional element and the second substrate; and a conductive material that electrically connects the electrode to the through electrode. Here, the joining material is harder than the conductive material, and the joining material is electrically less conductive than the conductive material.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 21, 2014
    Inventors: Yuichi ANDO, Yukito Sato, Katsunori Mae
  • Patent number: 8802542
    Abstract: The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: August 12, 2014
    Inventor: Erich Thallner
  • Patent number: 8765578
    Abstract: A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. La Tulipe, Jr., Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Patent number: 8765579
    Abstract: A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 1, 2014
    Assignee: Disco Corporation
    Inventors: Youngsuk Kim, Shigenori Harada
  • Patent number: 8741693
    Abstract: A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: June 3, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-An Huang, Hsin-Yi Liao, Shih-Kuang Chiu
  • Patent number: 8735260
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Hung-Hua Lin, Ming-Tung Wu, Ping-Yin Liu, Yao-Te Huang, Yuan-Chih Hsieh
  • Patent number: 8722502
    Abstract: A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 13, 2014
    Inventor: Shiro Uchiyama
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8711897
    Abstract: A split ring-resonator includes a substrate, an inner-trench or cavity formed into the substrate, the inner trench or cavity including a split, and an outer trench or cavity formed into the substrate around the inner trench or cavity, the outer trench or cavity including another split disposed at an opposite end of the split in the inner trench or cavity, wherein the inner trench or cavity and the outer trench or cavity are configured to receive an electrically conductive gas and/or plasma to form a split-ring resonator.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: April 29, 2014
    Assignee: Miles Technologies, LLC
    Inventor: Patrick Allen Miles
  • Patent number: 8698131
    Abstract: Provided is an organic EL apparatus including: an organic EL panel including organic EL devices; a heat releasing member; and a pair of film sheets of which at least one is transparent, wherein the organic EL panel and the heat releasing member overlap and are interposed and encapsulated by the pair of film sheets in a state where a portion of the heat releasing member is exposed outside the pair of film sheets.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Kozo Gyoda