Abstract: A sensor and method for fabricating a sensor is disclosed that in one embodiment bonds an etched semiconductor substrate wafer to an etched device wafer comprising a silicon on insulator wafer to create a suspended structure, the flexure of which is determined by an embedded sensing element to measure absolute pressure. Interconnect channels embedded in the sensor facilitate streamlined packaging of the device while accommodating interconnectivity with other devices.

Abstract: Methods of forming packaged microelectromechanical resonators include forming a first isolation trench in a first surface of a capping substrate, with the first isolation trench encircling a first portion of the capping substrate. The first isolation trench is filled with an electrically insulating material. The first surface of the capping substrate is bonded to a device substrate, which includes the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator. A second surface of the capping substrate is planarized for a sufficient duration to thereby expose the electrically insulating material and the first portion of the capping substrate encircled by the first isolation trench. The exposed first portion of the capping substrate is selectively etched to thereby define a through-substrate opening therein, which exposes a first portion of the first electrically conductive line.

Abstract: An industrial-scale high throughput wafer bonding apparatus includes a wafer bonder chamber extending along a main axis and comprising a plurality of chamber zones, a plurality of heater/isolator plates, a guide rod system extending along the main axis, a pair of parallel track rods extending along the main axis, and first pressure means. The chamber zones are separated from each other and thermally isolated from each other by the heater/isolator plates. The heater/isolator plates are oriented perpendicular to the main axis, are movably supported and guided by the guide rod system and are configured to move along the direction of the main axis. Each of the chamber zones is dimensioned to accommodate an aligned wafer pair and the wafer pairs are configured to be supported by the parallel track rods. The first pressure means is configured to apply a first force perpendicular to a first end heater/isolator plate.

Abstract: A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer.

Abstract: Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.

Abstract: A method for making a structure including at least the steps of: making at least one first portion of at least one getter material against a first substrate or a second substrate, making at least one second portion of at least one getter material against the second substrate when the first portion of getter material is placed against the first substrate, or against the first substrate when the first portion of getter material is placed against the second substrate, and attaching the second substrate to the first substrate by thermocompression of a first part of the first portion of getter material against at least one part of the second portion of getter material, forming at least one cavity delimited by the first substrate and the second substrate, a second part of the first portion of getter material being placed in the cavity.

Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.

Abstract: A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane.

Abstract: A method of making a complex microelectronic structure by assembling two substrates through two respective linking surfaces, the structure being designed to be dissociated at a separation zone. Prior to assembly, in producing a state difference in the tangential stresses between the two surfaces to be assembled, the state difference is selected so as to produce in the assembled structure a predetermined stress state at the time of dissociation.

Abstract: A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal.

Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.

Abstract: A workpiece machining method includes attaching a workpiece to a workpiece support with the aid of joining means. The workpiece and the workpiece support are joined to one another by an annular joining means. The composite produced is machined. The machined workpiece is separated from the workpiece support.

Abstract: The invention pertains to a combination of a substrate (6) and a wafer (15), wherein the substrate (6) and the wafer (15) are arranged parallel to one another and bonded together with the aid of an adhesive layer (8) situated between the substrate (6) and the wafer (15), and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer (8) is only applied annularly between the substrate (6) and the wafer (15) in the edge region of the wafer (15).

Abstract: A semiconductor substrate is provided by a method suitable for mass production. Further, a semiconductor substrate having an excellent characteristic with effective use of resources is provided.

Abstract: A method for forming through features in a substrate uses a seed layer deposited over a first substrate, and a second substrate bonded to the seed layer. The features may be formed in the first substrate, by plating a conductive filler material onto the seed layer. The first substrate and the second substrate may then be bonded to a third substrate, and the second substrate is removed, leaving through features and first substrate adhered to the third substrate. The through features may provide at least one of electrical access and motion to a plurality of devices formed on the third substrate, or may impart movement to a moveable feature on the first substrate, wherein the third substrate supports the first substrate after removal of the second substrate.

Abstract: In a method of manufacturing a semiconductor thin film piece device, a plurality of semiconductor thin film pieces (14) are selected from among the semiconductor thin film pieces (14) formed on a first substrate (35), and bonded to a first set of predetermined area on a second substrate (12). Subsequently, a plurality of semiconductor thin film pieces are selected from the remaining semiconductor thin film pieces (14), and bonded to a second set of predetermined area.

Abstract: An LED package and a fabrication method thereof are provided. The LED package includes an upper metal plate having an LED-receiving hole therein; a lower metal plate disposed under the upper metal plate; and an insulator which the upper metal plate and the lower metal plate from each other. A portion of the lower metal plate is exposed via the LED-receiving hole and an LED is mounted on the exposed portion of the lower metal plate and is electrically connected to both of the upper and lower metal plates. A protective cover encloses and protects exposed surfaces of the upper and lower metal plates.

Abstract: A stretchable electronic circuit that includes a stretchable base substrate having a plurality of stretchable conductors formed onto a surface thereof, with both the stretchable base substrate and conductors being bendable together about two orthogonal axes. The stretchable circuit also includes a stretchable sensor layer attached to the base substrate with a cavity formed therein which has a contact point exposing one of the plurality of stretchable conductors. The stretchable electronic circuit further includes a surface mount device (SMD) package with a conductor contact protrusion installed into the cavity, and wherein a substantially constant electrical connection is established between the conductor contact protrusion and the stretchable conductor at the contact point by tensile forces interacting between the stretchable base substrate and the stretchable sensor layer.

Abstract: A method for producing a capping wafer for a sensor having at least one cap includes: production of a contacting via extending through the wafer, and, temporally subsequent thereto, filling of the contacting via with an electrically conductive material.

Abstract: A method for producing a Group III nitride compound semiconductor element includes growing an epitaxial layer containing a Group III nitride compound semiconductor using a different kind of substrate as an epitaxial growth substrate, adhering a supporting substrate to the top surface of the epitaxial growth layer through a conductive layer, and then removing the epitaxial growth substrate by laser lift-off. Before adhesion of the epitaxial layer and the supporting substrate, a first groove that at least reaches an interface between the bottom surface of the epitaxial layer and the epitaxial growth substrate from the top surface of the epitaxial layer formed on the epitaxial growth substrate and acts as an air vent communicating with the outside of a wafer when the epitaxial layer and the supporting substrate are joined to each other.

Abstract: A method of manufacturing an optical sensor includes the steps of providing a semiconductor wafer having a plurality of pixel areas; forming a grid-like rib enclosing each pixel area on the semiconductor wafer, the grid-like rib having a predetermined width and being formed from a fixing member; providing a light-transmissive substrate having a gap portion on a main surface thereof, the gap portion having at least one of a groove having a width smaller than the grid-like rib and a plurality of through-holes; fixing the semiconductor wafer and the light-transmissive substrate such that the grid-like rib and the gap portion face each other; and cutting the fixed semiconductor wafer and light-transmissive substrate into pieces such that each piece includes one pixel area.

Abstract: An integrated component having a substrate, the substrate having a cavity which surrounds a mechanical structure. The cavity is filled by a fluid of a specific composition under a specific pressure, and the mechanical properties of the mechanical structure are influenced by the fluid.

Abstract: A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines.

Abstract: The invention relates to a process for fabricating a multilayer structure comprising: bonding a first wafer onto a second wafer, at least the first wafer having a chamfered edge; and thinning the first wafer so as to form in a transferred layer, the thinning comprising a grinding step and a chemical etching step. After the grinding step and before the chemical etching step, a trimming step of the edge of the first wafer is carried out using a grinding wheel, the working surface of which comprises grit particles having an average size of less than or equal to 800-mesh or greater than or equal to 18 microns, the trimming step being carried out to a defined depth in the first wafer so as to leave a thickness of the first wafer of less than or equal to 35 ?m in the trimmed region.

Abstract: A method of fabricating vapor cells comprises forming a plurality of vapor cell dies in a first wafer having an interior surface region and a perimeter, and forming a plurality of interconnected vent channels in the first wafer. The vent channels provide at least one pathway for gas from each vapor cell die to travel outside of the perimeter of the first wafer. The method further comprises anodically bonding a second wafer to one side of the first wafer, and anodically bonding a third wafer to an opposing side of the first wafer. The vent channels allow gas toward the interior surface region of the first wafer to be in substantially continuous pressure-equilibrium with gas outside of the perimeter of the first wafer during the anodic bonding of the second and third wafers to the first wafer.

Abstract: The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer situated between the substrate and the wafer, and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer is only applied annularly between the substrate and the wafer in the edge region of the wafer.

Abstract: Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.

Abstract: Systems, devices, and methods are presented that facilitate electronic manipulation and detection of submicron particles. A particle manipulation device contains a plurality of electrodes formed on an active semiconductor layer of an integrated circuit chip, where the electrodes and gap spacing between adjacent electrodes is submicron in size. The chip is oriented with its substrate face up, and at least a portion of the substrate is removed from the chip so the electrodes are in close proximity to a fluid chamber(s) placed over the chip, to facilitate manipulation of particles, contained in a buffer solution in the fluid chamber(s), to form a defined pattern. Innovative macro-scale optical detection is employed to detect the submicron particles, where a light beam is applied to the defined pattern, and interaction of the defined pattern with the light beam is detected and evaluated to facilitate detecting the particles.

Abstract: The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to form a pressurized sealed cavity between the carrier and the substrate. The method may also include thinning the substrate attached to the carrier and forming a redistribution layer on the thinned substrate in electrical communication with the via, the redistribution layer including a conductive layer formed through atmospheric pressure chemical vapor deposition. Additional methods, devices, and systems are devices, systems, and methods are also disclosed.

Abstract: A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer.

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.

Abstract: One aspect of the invention relates to a semiconductor component with cavity structure and a method for producing the same. The semiconductor component has an active semiconductor chip with the microelectromechanical structure and a wiring structure on its top side. The microelectromechanical structure is surrounded by walls of at least one cavity. A covering, which covers the cavity, is arranged on the walls. The walls have a photolithographically patterned polymer. The covering has a layer with a polymer of identical type. In one case, the molecular chains of the polymer of the walls are crosslinked with the molecular chains of the polymer layer of the covering layer to form a dimensionally stable cavity housing.

Abstract: The present teachings provide a detection cell for a biological material and methods for detecting biological material including a photosensitive material optically coupled to an interior volume containing the biological material so to avoid optical components or an external light source.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallization region is formed on the machined second surface of the semiconductor wafer.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: The invention pertains to a combination of a substrate (6) and a wafer (15), wherein the substrate (6) and the wafer (15) are arranged parallel to one another and bonded together with the aid of an adhesive layer (8) situated between the substrate (6) and the wafer (15), and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer (8) is only applied annularly between the substrate (6) and the wafer (15) in the edge region of the wafer (15).

Abstract: A method of forming a device is provided. A substrate having a component is provided and a sacrificial layer is formed over the component. The sacrificial layer includes a cavity portion disposed about the component and a tunnel portion adjacent to the cavity portion. In addition, an encapsulation layer having a cover portion and a perimeter portion is formed over the sacrificial layer. The cover portion encapsulates the cavity portion such that the cavity portion forms a cavity within the cover portion. The perimeter portion is disposed over the tunnel portion. Moreover, an access hole is formed in the perimeter portion of the encapsulation layer.

Abstract: A method of manufacturing an array type semiconductor laser device. The method includes forming first and second electrodes on lower and upper surfaces of a wafer comprising a plurality of semiconductor laser arrays having a plurality of laser emission regions, and forming a metal bonding layer on the second electrode of the wafer. The method also includes dicing the wafer into the semiconductor laser arrays and mounting each of the individually separated semiconductor laser arrays on a base with the surface of the metal bonding layer in contact with the base. The method further includes melting the metal bonding layer to fix the mounted semiconductor laser array on the base.

Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.

Abstract: A light-emitting diode and a method for manufacturing the same are described. The light-emitting diode includes a bonding substrate, a first conductivity type electrode, a bonding layer, an epitaxial structure, a second conductivity type electrode, a growth substrate and an encapsulant layer. The first conductivity type electrode and the bonding layer are respectively disposed on two surfaces of the bonding substrate. The epitaxial structure includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer. A trench is set around the epitaxial structure and extends from the second conductivity type semiconductor layer to the first conductivity type semiconductor layer. The second conductivity type electrode is electrically connected to the second conductivity type semiconductor layer. The growth substrate is disposed on the epitaxial structure and includes a cavity exposing the epitaxial structure and the trench.

Abstract: The invention relates to a process for and an arrangement of the connection of processed semiconductor wafers (1, 2) wherein, in addition to the firm connection, there is an electric connection (5) between the semiconductor wafers and/or the electronic structures (3) supporting them. For this purpose, low-melting structured intermediate glass layers (6; 6a) are used as insulating layers and as an electric connection in the form of electrically conductive solder (5) on a glass basis in order to achieve a firm connection.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: A method for making a structure for thermal management of circuit devices. The method provides a first substrate and a second substrate where at least one of the first and second substrates includes a circuit element. The method forms in at least one of the first substrate and the second substrate an entrance through-hole extending through a thickness of the first substrate or the second substrate, forms in at least one of the first substrate and the second substrate an exit through-hole extending through a thickness of the first substrate or the second substrate, forms respective bonding elements on at least one of the first and second substrates, and bonds the first and second substrates at the respective bonding elements to form a seal between the first and second substrates and to form a first coolant channel in between the first and second substrates.

Abstract: A method for making an optical device with integrated optoelectronic components, including a) making a protective structure including a support in which at least one blind hole is made, an optical element being positioned in the blind hole, b) attaching the support to a substrate including the integrated optoelectronic components, the blind hole forming a cavity in which the optical element faces one of the optoelectronic components, c) achieving thinning of the substrate and making electric connections through the substrate, and d) making an aperture through the bottom wall of the blind hole, uncovering at least one portion of the optical field of the optical element.

Abstract: A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising an undiced semiconductor wafer having a multitude of microchips. The multitude of microchips on the wafer forming a plurality of independently functioning computers, each computer having independent communication capabilities.

Abstract: A flexible electronic circuit member formed of a plurality of dielectric layers includes a plurality of thinned semiconductor chips embedded within the circuit member for increased levels of integration and component density. The thinned semiconductor chips may include various integrated circuits thereon. They may be formed on various substrates and using various technologies and the embedded, thinned semiconductor chips are interconnected by a patterned interconnect that extends between and through the respective dielectric layers. A method for forming the flexible circuit member includes joining semiconductor chips to a mounting apparatus using a releasable bonding layer then forming thinned semiconductor chips that are joined to respective dielectric layers that combine to form the flexible electronic circuit member. The releasable bonding layer is removed after the thinned semiconductor chips are joined to the respective dielectric layers used in combination to form the electronic circuit member.