Bonding Of Plural Semiconductor Substrates Patents (Class 438/455)
  • Patent number: 11183420
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 23, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Qingmin Liu
  • Patent number: 11158598
    Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.
    Type: Grant
    Filed: July 11, 2021
    Date of Patent: October 26, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11158764
    Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Calvin Wade Sheen
  • Patent number: 11156520
    Abstract: A physical quantity sensor includes a first substrate, an electrode provided on the first substrate, a diaphragm made of semiconductor material, a second substrate fixed to the first substrate, a dielectric film provided on the diaphragm, and a wall provided between the dielectric film and the electrode. The second substrate supports the diaphragm such that the diaphragm has an opposing surface facing the electrode across a space. The dielectric film is provided on the opposing surface of the diaphragm. The dielectric film has a surface facing the electrode across the space. The wall includes a first protrusion and a second protrusion. The first protrusion protrudes toward the electrode from the surface of the dielectric film. The second protrusion protrudes toward the electrode from the first protrusion, and contacts the electrode. The second protrusion is made of material which is different from material of the dielectric film.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 26, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hisanori Siroisi, Jun Ogihara, Naoki Ushiyama
  • Patent number: 11148938
    Abstract: According to one embodiment, a controller is configured to calculate a matching rate of grid shapes between each semiconductor wafer of a first semiconductor wafer group and each semiconductor wafer of a second semiconductor wafer group, and generate pairing information, into which combinations of semiconductor wafers used in calculation of matching rates are registered when the matching rates fall within a predetermined range. Further, the controller is configured to select a first semiconductor wafer to be held by a first semiconductor wafer holder from the first semiconductor wafer group, and select a second semiconductor wafer from semiconductor wafers of the second semiconductor wafer group, which are paired with the first semiconductor wafer, with reference to the pairing information.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Sho Kawadahara
  • Patent number: 11127776
    Abstract: A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 21, 2021
    Assignee: LFOUNDRY S.R.L.
    Inventors: Giovanni De Amicis, Andrea Del Monte, Onorato Di Cola
  • Patent number: 11127718
    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: September 21, 2021
    Assignee: XILINX, INC.
    Inventors: Anil Kumar Kandala, Vijay Kumar Koganti, Santosh Yachareni
  • Patent number: 11100378
    Abstract: A packaging paperboard is provided that includes two or more layers with an antenna pattern printed on one layer of the two or more layers, and an RFIC element adhered to the other layer of the two or more layers. In a laminate having the layers stuck together, the RFIC element and the antenna pattern are interposed between the layers to configure an RFIC device in which the RFIC element and the antenna pattern are electrically connected.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 24, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noboru Kato, Teppei Miura
  • Patent number: 11101195
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Liang Shao, Wen-Lin Shih, Su-Chun Yang, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 11086155
    Abstract: A method of manufacturing the flexible device includes: forming a photosensitive film on a hard base substrate, the photosensitive film including a photosensitive resin material containing azide; forming a base including an inorganic material on the photosensitive film; forming an electronic device functional layer on the base; forming an encapsulation layer on the electronic device functional layer; irradiating the photosensitive film at a side of the base substrate away from the encapsulation layer; and peeling off an entire structure including the base, and the electronic device functional layer and the encapsulation layer that have been formed on the base from the photosensitive film.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 10, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jianguo Wang
  • Patent number: 11079359
    Abstract: A system includes a structure bonding layer and a sensor. The structure bonding layer is disposed on a structure. The structure bonding layer is a metallic alloy. The sensor includes a non-metallic wafer and a sensor bonding layer disposed on a surface of the non-metallic wafer. The sensor bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 3, 2021
    Assignee: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Patent number: 11062915
    Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11063080
    Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalk form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalk and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Jhy-Jyi Sze, Dun-Nian Yaung, Chen-Jong Wang, Yimin Huang, Yuichiro Yamashita
  • Patent number: 11049873
    Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 29, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Chenming Hu, Wu-Yi Henry Chien, Eli Harari
  • Patent number: 11000911
    Abstract: The present invention provides a method for manufacturing a backlight source. The method for manufacturing a backlight source according to the present invention forms a plurality of tin soldering pattern groups on a substrate. Each tin soldering pattern group includes tin soldering patterns spaced from one another, and the tin soldering patterns are in a closed ring shape. The Mini-LEDs are disposed on the tin soldering pattern groups respectively. The substrate is placed in the space having a varying magnetic field. The circuit of the tin soldering patterns in the tin soldering pattern groups generates the induced current for rapid heating and melting, to solder the Mini-LEDs on the substrate. The soldering speed is improved, the process efficiency is high, the process cost is low, and the light effect of the backlight source is effectively ensured.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 11, 2021
    Inventor: Yong Yang
  • Patent number: 11004967
    Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: May 11, 2021
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 11004833
    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Anil Kumar Kandala, Vijay Kumar Koganti, Santosh Yachareni, Sundeep Ram Gopal Agarwal
  • Patent number: 10964769
    Abstract: A stretchable display device includes a stretchable substrate including a plurality of island areas that are separated from each other and a hinge area connecting the plurality of island areas, a plurality of display units respectively located in each of the plurality of island areas, a wiring part connecting the plurality of display units and located at the hinge area, and an insulating layer between the stretchable substrate and the plurality of display units. The insulating layer includes an opening overlapping the hinge area.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwui-Hyun Park, Chul Won Park, Pil Soon Hong, Bo Geon Jeon
  • Patent number: 10964664
    Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 30, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Chandrasekhar Mandalapu, Gaius Gillman Fountain, Jr., Guilian Gao
  • Patent number: 10957539
    Abstract: A process includes the successive steps of: a) providing first and second substrates, each including a first surface and an opposite, second surface, lateral edges connecting the first and second surfaces, b) bonding the first substrate to the second substrate by direct bonding with the first surfaces of the first and second substrates so as to form a bonding interface (IC), and making the lateral edges of the first and second substrates hydrophobic on either side of the bonding interface (IC).
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 23, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Frank Fournel, Vincent Larrey, Christophe Morales, Marwan Tedjini
  • Patent number: 10950631
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Liang Liu, Yeur-Luen Tu
  • Patent number: 10943810
    Abstract: A device for bonding of a second substrate onto a first substrate, comprising a receiving apparatus for receiving the first substrate which has been coated with a bond layer and the second substrate which is held on the bond layer, and an action apparatus for applying a bond force to the second substrate on one action side of the second substrate, which side faces away from the bond layer proceeding from an initial zone A, which lies within an edge zone R of the action side as far as action on the entire action side. Furthermore, this invention relates to a corresponding method.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: March 9, 2021
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Jurgen Burggraf
  • Patent number: 10923452
    Abstract: A substrate bonding apparatus for bonding a first substrate to a second substrate includes: a first bonding chuck including: a first base; a first deformable plate provided on the first base to support the first substrate; and a first pneumatic adjustor configured to deform the first deformable plate by adjusting a first pressure in a first cavity formed between the first deformable plate and the first base; and a second bonding chuck including: a second base; a second deformable plate provided on the second base to support the second substrate; and a second pneumatic adjustor configured to deform the second deformable plate by adjusting a second pressure in a second cavity formed between the second deformable plate and the second base.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ilyoung Han, Taeyeong Kim, Jihoon Kang, Nohsung Kwak, Seokho Kim, Hoechul Kim, Ilhyoung Lee, Hakjun Lee
  • Patent number: 10906288
    Abstract: A method for manufacturing a display device is disclosed, the method at least includes the following step: Firstly, a temporary substrate is provided, a hydrogen containing structure is formed on the temporary substrate, a polymer film is formed on the hydrogen containing structure, and a display element is formed on the polymer film. Afterwards, a laser beam process is performed, to focus a laser beam on the hydrogen containing structure, and the temporary substrate is then removed.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 2, 2021
    Assignee: InnoLux Corporation
    Inventors: Wen-Chien Lin, Kuo-Jung Fan
  • Patent number: 10903078
    Abstract: A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Guenter Denifl, Mihai Draghici, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Wolfgang Lehnert, Roland Rupp, Werner Schustereder
  • Patent number: 10896847
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Il-Seok Son, Colin T. Carver, Paul B. Fischer, Patrick Morrow, Kimin Jun
  • Patent number: 10886063
    Abstract: An electronic-component manufacturing method is for simultaneously manufacturing a plurality of electronic components each including an element body and a conductor. The electronic-component manufacturing method includes the steps of forming laminates to be the plurality of electronic components on a plurality of regions set apart from each other on a surface of a first substrate, releasing the laminates from the plurality of regions, and performing heat treatment to the laminates. The forming the laminates includes a first step of forming element-body patterns on the plurality of regions and a second step of forming conductor patterns on the plurality of regions. The element-body patterns contain a constituent material of the element bodies and are patterned for the plurality of regions. The conductor patterns contain a constituent material of the conductors and are patterned for the plurality of regions.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 5, 2021
    Assignee: TDK CORPORATION
    Inventors: Yuya Ishima, Shunji Aoki, Shinichi Kondo, Yasushi Matsuyama, Hajime Azuma, Yusuke Onezawa
  • Patent number: 10886163
    Abstract: A bonded wafer including an ion implantation step using a batch processing ion implanter, wherein the ion implantation step is performed by irradiating a bond wafer with a light element ion beam without forming an insulator film on the bond wafer surface or through an insulator film having a thickness of 50 nm or less formed on the bond wafer surface at an implantation angle inclined from a crystal axis of the bond wafer; and the bond wafer surface is irradiated with the center of the light element ion beam shining at a position on the bond wafer surface shifted from the center of the bond wafer parallel to the center of a rotor by a predetermined amount providing a bonded wafer to prevent degradation of the radial uniformity of ion implantation depth and manufacture a bonded wafer with excellent radial uniformity of thickness of a thin film after delamination.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 5, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Isao Yokokawa
  • Patent number: 10872873
    Abstract: A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chih Chen, Tsung-Yi Yang, Chung-I Hung, Mu-Han Cheng, Tzu-Shin Chen, Su-Yu Yeh
  • Patent number: 10872802
    Abstract: In a method of debonding a carrier substrate from a device substrate, an ultraviolet (UV) light may be irradiated to an adhesive tape through the carrier substrate, which may be attached to a first surface of the device substrate having a connection post using the adhesive tape, to weaken an adhesive force of the adhesive tape. An outskirt portion of the carrier substrate may be masked to concentrate the UV light on the adhesive tape.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gun-Ho Chang, Myung-Kee Chung
  • Patent number: 10859981
    Abstract: In a general aspect, a vapor cell is presented that includes a dielectric body. The dielectric body has a surface that defines an opening to a cavity in the dielectric body. The vapor cell also includes a vapor or a source of the vapor in the cavity of the dielectric body. An optical window covers the opening of the cavity and has a surface bonded to the surface of the dielectric body to form a seal around the opening. The seal includes metal-oxygen bonds formed by reacting a first plurality of hydroxyl ligands on the surface of the dielectric body with a second plurality of hydroxyl ligands on the surface of the optical window.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 8, 2020
    Assignee: Quantum Valley Ideas Laboratories
    Inventors: Jaime Ramirez-Serrano, Hadi Amarloo, James P. Shaffer
  • Patent number: 10863658
    Abstract: Methods and apparatus for use in the manufacture of a display element. Some embodiments include a method for selective pick up of a subset of a plurality of electronic devices adhered to a handle layer. The method comprises modifying a level of adhesion between one or more electronic devices of the plurality of electronic devices adhered to the handle layer, such that the subset of the plurality of electronic devices has a level of adhesion to the handle layer that is less than a force applied by a pick up tool, PUT. This enables selective pick up of the subset of the plurality of electronic devices from the handle layer by the PUT.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 8, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Allan Pourchet, William Padraic Henry, Patrick Joseph Hughes, Joseph O'Keeffe
  • Patent number: 10844515
    Abstract: A semiconductor wafer comprising single-crystal silicon has defined concentrations of oxygen, nitrogen and hydrogen; the semiconductor wafer further contains BMD seeds having a density averaged over the radius of not less than 1×105 cm?3 and not more than 1×107 cm?3; surface defects having a density averaged over the radius of not less than 1100 cm?2; and BMDs, whose density is not lower than a lower limit of 5×108/cm3. The semiconductor wafers are produced by a process which enables obtention of the required ranges of concentrations of oxygen, nitrogen, hydrogen, BMD seeds, and BMD's.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: November 24, 2020
    Assignee: SILTRONIC AG
    Inventors: Timo Mueller, Walter Heuwieser, Michael Skrobanek, Gudrun Kissinger
  • Patent number: 10840222
    Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a trap-rich layer disposed between the first level and the second level; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the plurality of connection paths includes vertical connections connecting from the first interconnections to the second interconnections, where the third layer includes crystalline silicon, and where the second level is bonded to the first level.
    Type: Grant
    Filed: April 11, 2020
    Date of Patent: November 17, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 10836140
    Abstract: A composite includes a component and a glass or glass ceramic material. The component has a first coefficient of expansion ?1 and the glass or the glass ceramic material has a second coefficient of expansion ?2. The glass or the glass ceramic material has a surface with a thickness and thickness differences (TTV) within the surface, and thickness fluctuations (LTV). The composite has a residual stress in the glass or the glass ceramic material (WARP), and a geometric and material-physical degree of compatibility KG?4.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: November 17, 2020
    Assignee: Schott AG
    Inventors: Matthias Jotz, Marten Walther, Florian Resch, Thomas Wiegel
  • Patent number: 10819381
    Abstract: An electronic device according to certain embodiments includes a housing, a first glass plate coupled to the housing and defining an inner space, the first glass plate including a peripheral portion including: a first, second, third, fourth, and fifth surface forming an edge of the glass plate, the first and fifth surfaces being substantially parallel and the third surface being substantially perpendicular to the first and fifth surfaces, a decorative layer formed of a first material, disposed on a first area of the fifth surface such that a second area disposed between the fourth surface and the first area is uncovered by the decorative layer, and a protective layer formed of a second material, covering the second surface, the third surface, the fourth surface, the second area of the fifth surface, and a part of the decorative layer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangbong Lee, Namhyung Kim, Taekon Kim, Kiyul Lim, Jaehoon Lee
  • Patent number: 10811315
    Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Stefaan Van Huylenbroeck, Geert Van der Plas
  • Patent number: 10800947
    Abstract: Various embodiments disclosed related to a release layer including at least one fluorosilicon compound, and to related aspects such as methods for display device substrate processing. In various embodiments is a method of processing a display device substrate. The method can include securing the display device substrate to a carrier substrate with an adhesive delamination layer and a release layer between the adhesive delamination layer and the display device substrate. The release layer includes a cured product of a precursor release layer composition. The precursor release layer composition includes at least one fluorosilicon compound.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 13, 2020
    Assignee: Dow Silicones Corporation
    Inventors: Ginam Kim, Junying Liu
  • Patent number: 10796627
    Abstract: Integrated laser arrays based devices and systems and methods of forming the integrated laser arrays based devices and systems are provided. In one aspect, an integrated display includes a semiconductor substrate including a first side and a second side, an array of active-matrix light-emitting pixels, each of the pixels including one or more light-emitting elements formed on the first side and at least one non-volatile memory coupled to the one or more light-emitting elements, each of the light-emitting elements including a lasing structure that has an optical resonator and one or more semiconductor layers in the optical resonator and is operable to emit a laser light, one or more integrated circuits formed on the second side, and conductive interconnects penetrating from the second side through the semiconductor substrate and conductively coupling the one or more integrated circuits to the light-emitting elements.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 6, 2020
    Inventor: Shaoher Pan
  • Patent number: 10784927
    Abstract: An RFID tag is provided that transmits and receives a communication signal. The RFID tag includes a base material, antenna patterns provided on the base material, an RFIC package that is a feeding circuit connected to the antenna patterns, and an ignition protection member provided on the base material or the antenna patterns. Moreover, the ignition protection member contains moisture, such that ignition and combustion can be prevented even in a situation where the RFID tag is subjected to high-frequency power for heating a food item while attached to the food item or the like.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 22, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirokazu Yazaki, Noriyuki Ueki, Noboru Kato
  • Patent number: 10777447
    Abstract: A method for determining a suitable implanting energy of at least two atomic species in a donor substrate to create a weakened zone defining a monocrystalline semiconductor layer to be transferred onto a receiver substrate, comprises the following steps: (i) forming a dielectric layer on at least one of the donor substrate and the receiver substrate; (ii) co-implanting the species in the donor substrate; (iii) bonding the donor substrate on the receiver substrate; (iv) detaching the donor substrate along the weakened zone to transfer the monocrystalline semiconductor layer and recover the remainder of the donor substrate; (v) inspecting the peripheral crown of the remainder of the donor substrate, or of the receiver substrate on which the monocrystalline semiconductor layer was transferred at step (iv); (vi) if the crown exhibits zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is too high; (vii) if said the crown does not exhibit zones transferred on
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 15, 2020
    Assignee: Soitec
    Inventors: Ludovic Ecarnot, Nadia Ben Mohammed, Carine Duret
  • Patent number: 10777533
    Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 15, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain
  • Patent number: 10763130
    Abstract: Systems and methods are provided for producing an integrated circuit package, e.g., an SOIC package, having reduced or eliminated lead delamination caused by epoxy outgassing resulting from the die attach process in which an integrated circuit die is attached to a lead frame by an epoxy. The epoxy outgassing may be reduced by heating the epoxy during or otherwise in association with the die attach process, e.g. using a heating device provided at the die attach unit. Heating the epoxy may achieve additional cross-linking in the epoxy reaction, which may thereby reduce outgassing from the epoxy, which may in turn reduce or eliminate subsequent lead delamination. A heating device located at or near the die attach site may be used to heat the epoxy to a temperature of 55° C.±5° C. during or otherwise in association with the die attach process.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 1, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Taweesak Laevohan, Philbert Reyes, Jaggrit Vilairat, Sutee Thanaisawn, Janpen Phimphuang, Somsak Chunpangam
  • Patent number: 10747101
    Abstract: The present specification relates to a photomask, a laminate including the photomask, a method for manufacturing the photomask and a method for forming a pattern using the photomask.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 18, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Yong Goo Son, Kiseok Lee, Seung Heon Lee
  • Patent number: 10749089
    Abstract: A light emitting device package according to an embodiment includes: a package body; a light emitting device disposed on the package body; and an adhesive disposed between the package body and the light emitting device. The package body includes first and second openings passing through the package body on an upper surface of the package body and a recess provided to concave in a direction of a lower surface of the package body from the upper surface of the package body. The light emitting device includes a first bonding part disposed on the first opening and a second bonding part disposed on the second opening. The adhesive is provided at the recess.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 18, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sung Lee, Won Jung Kim, June O Song, Chang Man Lim
  • Patent number: 10734533
    Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 4, 2020
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 10727205
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10720396
    Abstract: A semiconductor chip including a substrate including a plurality of chip areas and a line-shaped scribe area defining the chip areas, an integrated circuit (IC) structure on the chip area, the IC structure including a plurality of transistors and a plurality of stacked wiring structures connected to the transistors, and a warpage protector in the line-shaped scribe area and corresponding to the stacked wiring structures, the warpage protector supporting at least one side of the IC structure may be provided.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Hyun Roh
  • Patent number: 10707258
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Patent number: 10692826
    Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen