Bonding Of Plural Semiconductor Substrates Patents (Class 438/455)
  • Patent number: 12237318
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.
    Type: Grant
    Filed: October 11, 2023
    Date of Patent: February 25, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 12217963
    Abstract: A bonding apparatus configured to bond a first substrate and a second substrate includes: a first holder configured to hold the first substrate; a second holder disposed to face the first holder in a vertical direction, and configured to hold the second substrate; a processing vessel accommodating the first holder and the second holder therein; and a horizontal position adjuster provided outside the processing vessel and connected to the first holder via a support supporting the first holder, the horizontal position adjuster being configured to adjust a horizontal position of the first holder.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 4, 2025
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yutaka Yamasaki, Takashi Terada
  • Patent number: 12217957
    Abstract: A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 4, 2025
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 12211831
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: January 28, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 12205933
    Abstract: A light emitting device including first, second, and third light emitting stacks each including first and second conductivity type semiconductor layers, a first lower contact electrode in ohmic contact with the first light emitting stack, and second and third lower contact electrodes respectively in ohmic contact with the second conductivity type semiconductor layers of the second and third light emitting stacks, in which the first lower contact electrode is disposed between the first and second light emitting stacks, the second and third lower contact electrodes are disposed between the second and third light emitting stacks, and the first, second, and third lower contact electrodes include transparent conductive oxide layers.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: January 21, 2025
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Min Jang, Chang Yeon Kim
  • Patent number: 12207534
    Abstract: A flexible display panel and a manufacturing method thereof are disclosed. The method includes: forming a photodeformable layer on a carrier board; forming a flexible substrate on a side of the photodeformable layer away from the carrier board; forming a light-emitting device layer on a side of the flexible substrate away from the photodeformable layer; and irradiating the photodeformable layer with light having a predetermined wavelength until the photodeformable layer is deformed and is separated from the carrier board, thereby obtaining the flexible display panel.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: January 21, 2025
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Kunsong Ma
  • Patent number: 12199018
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Han Wui Then, Kimin Jun, Aleksandar Aleksov, Mohammad Enamul Kabir, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Patent number: 12185521
    Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 31, 2024
    Assignee: ICLEAGUE TECHNOLOGY CO., LTD.
    Inventors: Wenyu Hua, Fandong Liu, Xiao Ding
  • Patent number: 12183741
    Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: December 31, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungmin Kim, Daewon Ha
  • Patent number: 12168603
    Abstract: A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device monolithically after CMOS processing. For example, the MEMS sensors are formed over a BEOL dielectric of a CMOS device. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: December 17, 2024
    Assignee: Meridian Innovation Pte Ltd
    Inventors: Wan Chia Ang, Piotr Kropelnicki, Ilker Ender Ocak
  • Patent number: 12169679
    Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Lun Chien, Pin-Dai Sue, Li-Chun Tien, Ting-Wei Chiang, Ting Yu Chen
  • Patent number: 12164277
    Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
    Type: Grant
    Filed: October 9, 2023
    Date of Patent: December 10, 2024
    Assignee: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Patent number: 12165922
    Abstract: The present invention relates to the epitaxial lift-off of thin-films allowing the reuse of the expensive semiconductor substrates. In particular, it describes a structure and a method for epitaxial lift-off of several thin films from a single substrate (100) using a plurality of dissimilar sacrificial layers (101), strained layers (102, 104), and/or device or component layers (103). The properties of the sacrificial layers (101) and the strained layers (102,104) can be used (i) to facilitate the lift off process, (ii) to control the point of time of release of each released thin film individually and (iii) to aid in separation and sorting of the released thin films. The released device or component layers can comprise various useful structures, such as optoelectronic devices photonic components.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: December 10, 2024
    Inventors: Jani Oksanen, Tuomas Haggrén
  • Patent number: 12167694
    Abstract: A method for transferring a piezoelectric layer onto a support substrate comprises: —providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate, —forming a weakened zone in the piezoelectric substrate, so as to delimit the piezoelectric layer to be transferred, —providing the support substrate, —forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate, —bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and—fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: December 10, 2024
    Assignee: SOITEC
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 12158551
    Abstract: A method of manufacturing a radiation imaging apparatus includes electrically connecting a first surface of a flexible insulating layer to a conductive portion of a circuit substrate, covering an exposed portion of the conductive portion with a protection layer, and separating the flexible insulating layer from a substrate in contact with a second surface of the flexible insulating layer. The circuit substrate includes an integrated circuit mounted on the circuit substrate. The flexible insulating layer includes, on the first surface, a plurality of pixels arranged in a two-dimensional matrix to convert radiation into an electrical signal. The second surface of the flexible insulating layer is opposite to the first surface of the flexible insulating layer. The flexible insulating layer is separated from the substrate by irradiating the second surface with light transmitting through the substrate.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: December 3, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Ofuji, Yoshito Sasaki, Masato Inoue, Takamasa Ishii
  • Patent number: 12154858
    Abstract: Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: November 26, 2024
    Assignee: Invensas LLC
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 12152304
    Abstract: A film forming method for forming an object film on a substrate including: providing the substrate including an oxide layer of a first material formed on a layer of the first material formed on a surface of a first area, and a layer of a second material formed on a surface of a second area, the second material being different from the first material; reducing the oxide layer; oxidizing a surface of the layer of the first material after reducing the oxide layer; and forming a self-assembled monolayer on the surface of the layer of the first material by supplying a raw material gas of the self-assembled monolayer after oxidizing the surface of the layer of the first material.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 26, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shuji Azumo, Shinichi Ike, Yumiko Kawano
  • Patent number: 12148666
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: November 19, 2024
    Assignee: Kioxia Corporation
    Inventors: Hidekazu Hayashi, Mie Matsuo
  • Patent number: 12134555
    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 12136604
    Abstract: The present invention includes: a position detection unit (55) detecting positions of semiconductor chips and storing each detected position in a position database (56); a position correction unit (57) outputting a corrected bonding position; and a bonding control unit (58) performing bonding of the semiconductor chips based on the corrected bonding position input from the position correction unit (57). The position correction unit (57) calculates position shift amounts between the semiconductor chips of respective stages and an accumulated position shift amount, and when the accumulated position shift amount is greater than or equal to a predetermined threshold value, corrects the position of the semiconductor chip by the accumulated position shift amount and outputs it as the corrected bonding position, and the bonding control unit (58) performs bonding of the semiconductor chip of the next stage at the corrected bonding position input from the position correction unit.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 5, 2024
    Assignee: SHINKAWA LTD.
    Inventor: Hideharu Nihei
  • Patent number: 12131907
    Abstract: A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: October 29, 2024
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Thomas Plach, Jurgen Markus Suss
  • Patent number: 12125818
    Abstract: Technologies for plasma oxidation protection during hybrid bonding of semiconductor devices includes forming a blocking layer on a metallic bonding pad formed in a bonding surface of a semiconductor device to be bonded and performing a surface treatment on the bonding surface to increase the bonding strength of the bonding surface and contemporaneously remove the blocking layer from the metallic bonding pad. In an illustrative embodiment, the blocking layer is embodied as a self-assembled monolayer (SAM), and the surface treatment is embodied as a surface activation plasma (SAP) treatment. A diffusion barrier layer, such as a silicon carbon nitride layer, may form the bonding surface in some embodiments to reduce diffusion of the metallic bonding pad during an annealing treatment of the bonding process.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: October 22, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Jack Rogers, Satohiko Hoshino, Nathan Antonovich
  • Patent number: 12094965
    Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer—which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth m
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: September 17, 2024
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 12094704
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a device wafer and a carrier wafer, the device wafer including an SOI substrate comprising, stacked from the bottom upward, a lower substrate, a buried insulator layer and a semiconductor layer; bonding the device wafer at a front side thereof to the carrier wafer; removing at least the lower substrate through thinning the device wafer from a backside thereof, wherein the backside of the device wafer opposes the front side thereof; and providing a high-resistance substrate and bonding the device wafer at the backside thereof to the high-resistance substrate, the high-resistance substrate having a resistivity higher than that of the lower substrate. With the present disclosure, lower signal loss and improved signal linearity can be achieved while avoiding a significant cost increase.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 17, 2024
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Le Li, Jun Zhou, Sheng Hu
  • Patent number: 12094759
    Abstract: A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: September 17, 2024
    Assignee: Soitec
    Inventors: Didier Landru, Bruno Ghyselen
  • Patent number: 12087631
    Abstract: A method for producing a composite structure comprises providing a donor substrate including a single-crystal material, and a support substrate having a first alignment pattern on a face or edge of the support substrate. A heat treatment is applied at least to the donor substrate to bring about a surface reorganization on at least one face of the donor substrate. The surface reorganization results in formation of first steps of nanometric amplitude, which are parallel to a first main axis. The donor substrate and the support substrate are optically aligned, to better than ±0.1° between a locating mark indicating the first main axis on the donor substrate and at least one alignment pattern of the support substrate. The donor substrate and the support substrate are then assembled together, and a thin layer is transferred from the donor substrate onto the support substrate.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 10, 2024
    Assignee: SOITEC
    Inventor: Gweltaz Gaudin
  • Patent number: 12077686
    Abstract: A temporary adhesive has excellent spin coating properties of a circuit side of a wafer and a support, and excellent heat resistance when the circuit side of the wafer or the support is attached to an adhesion layer or a rear surface of the wafer is processed, and is capable of easily separating the circuit side of the wafer from the support after polishing the rear surface of the wafer, and simply removing an adhesive attached to the wafer or the support after the separation. The adhesive contains a component (A) to be cured by a hydrosilylation reaction, and a component (B) containing an epoxy-modified polyorganosiloxane at a ratio in % by mass of the component (A) to the component (B) of 99.995:0.005 to 30:70. The component (B) is an epoxy-modified polyorganosiloxane having an epoxy value of 0.1 to 5.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 3, 2024
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Kazuhiro Sawada, Tetsuya Shinjo, Hiroshi Ogino, Satoshi Kamibayashi, Shunsuke Moriya
  • Patent number: 12082470
    Abstract: A stretchable display device includes a stretchable substrate including a plurality of island areas that are separated from each other and a hinge area connecting the plurality of island areas, a plurality of display units respectively located in each of the plurality of island areas, a wiring part connecting the plurality of display units and located at the hinge area, and an insulating layer between the stretchable substrate and the plurality of display units. The insulating layer includes an opening overlapping the hinge area.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: September 3, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwui-Hyun Park, Chul Won Park, Pil Soon Hong, Bo Geon Jeon
  • Patent number: 12080802
    Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: September 3, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 12080672
    Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 3, 2024
    Assignee: ADEIA Semiconductor Bonding Technologies Inc.
    Inventors: Belgacem Haba, Laura Wills Mirkarimi, Javier A. DeLaCruz, Rajesh Katkar, Cyprian Emeka Uzoh, Guilian Gao, Thomas Workman
  • Patent number: 12071706
    Abstract: A process for producing a monocrystalline layer of AlN material comprises the transfer of a monocrystalline seed layer of SiC-6H material to a carrier substrate of silicon material, followed by the epitaxial growth of the monocrystalline layer of AlN material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 27, 2024
    Assignee: SOITEC
    Inventor: Bruno Ghyselen
  • Patent number: 12051621
    Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: July 30, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Patent number: 12051674
    Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: July 30, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12051601
    Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: July 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-hyung Kim, Sung-hyup Kim, Tae-yeong Kim
  • Patent number: 12046571
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: July 23, 2024
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Liang Wang, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • Patent number: 12040437
    Abstract: A micro light-emitting component, a micro light-emitting structure and a display device are disclosed. The micro light-emitting component has a micro light-emitting chip and a buffer element. The micro light-emitting chip has a first surface, a second surface opposite to the first surface and a plurality of outer sidewalls. The buffer element is disposed on the outer sidewalls or the first surface of the micro light-emitting chip. The buffer element has an inner surface and an outer surface. An angle is defined between the inner surface and the first surface or an extended surface of the first surface. The angle is greater than or equal to 90 degrees and less than or equal to 180 degrees. Therefore, the buffer element prevents the first surface of the micro light-emitting chip from damaging by collision when the micro light-emitting chip is dropped with the first surface facing down during a transferring procedure.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 16, 2024
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Bo-Wei Wu, Yu-Yun Lo, Shiang-Ning Yang
  • Patent number: 12041791
    Abstract: A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: July 16, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 12040241
    Abstract: This disclosure provides a package structure for a semiconductor device, comprising a three-layer film consisting of a first SiO2 film, a Si3N4 film and a second SiO2 film stacked in this order, wherein the first SiO2 film is formed by a thermal oxidation process, the Si3N4 film is formed by a low pressure chemical vapor deposition process, and the second SiO2 film is formed by a low temperature atomic layer deposition process. This disclosure also provides a method for preparing the package structure for a semiconductor device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 16, 2024
    Assignee: XIDIAN UNIVERSITY
    Inventors: Chen Liu, Yuming Zhang, Hongliang Lv
  • Patent number: 12034105
    Abstract: An image display element provides an image display element including a plurality of micro light-emitting elements arrayed in an array manner, and a semiconductor layer at which a drive circuit is disposed, the drive circuit being configured to supply a current to each of the plurality of micro light-emitting elements to cause light to be emitted, in which a transistor that constitutes the drive circuit and a wiring layer are disposed at a first surface of the semiconductor layer, the plurality of micro light-emitting elements are disposed at a second surface of the semiconductor layer that is an opposite side of the first surface, and the transistor and the wiring layer are electrically coupled to the micro light-emitting elements through a through substrate via that extends through the semiconductor layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 9, 2024
    Assignee: Sharp Fukuyama Laser Co., Ltd.
    Inventors: Katsuji Iguchi, Hidenori Kawanishi, Shinsuke Anzai
  • Patent number: 12033969
    Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 12033980
    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Michel Koopmans
  • Patent number: 12030238
    Abstract: A method of 3D printing to achieve a desired surface quality on at least one surface of a 3D printed object comprising selecting a base surface having the desired surface quality; and printing the 3D printed object on the base surface, so that the desired surface quality is imparted to one surface of the 3D printed object during printing. The surface quality may be glassiness, roughness, smoothness and texture in general. Objects may thus be manufactured in which electronic components are integrated in or under a glass-like surface.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 9, 2024
    Assignee: Stratasys Ltd.
    Inventors: Guy Menchik, Yaniv Shitrit, Boris Belocon, Yehoshua Sheinman, Daniel Dikovsky
  • Patent number: 12020936
    Abstract: A substrate processing apparatus configured to process a substrate includes a holder configured to hold, in a combined substrate in which a first substrate and a second substrate are bonded to each other, the second substrate; and a modifying device configured to form, to an inside of the first substrate held by the holder, a peripheral modification layer by radiating laser light for periphery along a boundary between a peripheral portion of the first substrate as a removing target and a central portion thereof, and, also, configured to form an internal modification layer by radiating laser light for internal surface along a plane direction of the first substrate. The modifying device switches the laser light for periphery and the laser light for internal surface by adjusting at least a shape or a number of the laser light for periphery and the laser light for internal surface.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 25, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Hirotoshi Mori, Takeshi Tamura
  • Patent number: 12009337
    Abstract: A bonding tool and a bonding method are provided. The method includes attaching a semiconductor die to a bonding tool having a first surface, wherein the bonding tool comprises a bending member movably arranged in a trench of the bonding tool, and the bending member protrudes from the first surface and bends the semiconductor die; moving the semiconductor die toward a semiconductor wafer to cause a retraction of the bending member and a partial bonding at a portion of the semiconductor die and the semiconductor wafer; and causing a full bonding between the semiconductor die and the semiconductor wafer subsequent to the partial bonding.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yuan Chiu, Shih-Yen Chen, Chi-Chun Peng, Hong-Kun Chen, Hui-Ting Lin
  • Patent number: 12009231
    Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: June 11, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-hyung Kim, Sung-hyup Kim, Tae-yeong Kim
  • Patent number: 12009325
    Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 11, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Jiwon Kim, Jaeho Ahn, Joon-Sung Lim, Sukkang Sung
  • Patent number: 12002813
    Abstract: A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Ching I Li, Chia-Shiung Tsai
  • Patent number: 11996285
    Abstract: Silicon carbide on insulator is provided by bonding bulk silicon carbide to a substrate with an oxide-oxide fusion bond, followed by thinning the bulk silicon carbide as needed. A doping-selective etch for silicon carbide is used to improve thickness uniformity of the silicon carbide layer(s).
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: May 28, 2024
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Daniil M. Lukin, Jelena Vuckovic
  • Patent number: 11990447
    Abstract: A first alignment resin (4) is formed in an annular shape on an electrode (3) of an insulating substrate (1). First plate solder (5) having a thickness thinner than that of the first alignment resin (4) is arranged on the electrode (3) on an inner side of the annular shape of the first alignment resin (4). A semiconductor chip (6) is arranged on the first plate solder (5). The first plate solder (5) is made to melt to bond a lower surface of the semiconductor chip (6) to the electrode (3).
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 21, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Isao Oshima
  • Patent number: RE50124
    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: September 10, 2024
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie