Abstract: A microelectromechanical system (MEMS) device and method of fabrication are provided. The MEMS devices includes a silicon substrate. The silicon substrate includes a top surface. An interconnect is machined from the silicon substrate. The interconnect includes at a spring body that has least two spring arms. Each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and a single turn of a constant curvature. Each spring arm is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.

Abstract: A flexible display includes: a first layer structure and a second layer structure, where the first layer structure includes a first structure located at a same layer as the second layer structure and a second structure stacked on the second layer structure; a third layer structure, where the third layer structure covers the second structure and a first part of the first structure; a fourth layer structure, where the fourth layer structure is disposed at a same layer as the third layer structure, and covers a second part of the first structure; and a fifth layer structure, where the fifth layer structure covers the third layer structure and the fourth layer structure, and is fixedly connected to the third layer structure and the fourth layer structure.

Abstract: The present description concerns a method of manufacturing a device comprising at least one radio frequency component on a semiconductor substrate comprising: a) a laser anneal of a first thickness of the substrate on the upper surface side of the substrate; b) the forming of an insulating layer on the upper surface of the substrate; and c) the forming of said at least one radio frequency component on the insulating layer.

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

Abstract: Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InxAl1-xN), InxGa1-xN, AlxGa1-xN, InxAlyGa1-x-yN, where (0<x?1, 0<y?1, 0<x+y?1).

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

Abstract: A bonding apparatus configured to bond a first substrate and a second substrate includes: a first holder configured to hold the first substrate; a second holder disposed to face the first holder in a vertical direction, and configured to hold the second substrate; a processing vessel accommodating the first holder and the second holder therein; and a horizontal position adjuster provided outside the processing vessel and connected to the first holder via a support supporting the first holder, the horizontal position adjuster being configured to adjust a horizontal position of the first holder.

Abstract: A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

Abstract: A flexible display panel and a manufacturing method thereof are disclosed. The method includes: forming a photodeformable layer on a carrier board; forming a flexible substrate on a side of the photodeformable layer away from the carrier board; forming a light-emitting device layer on a side of the flexible substrate away from the photodeformable layer; and irradiating the photodeformable layer with light having a predetermined wavelength until the photodeformable layer is deformed and is separated from the carrier board, thereby obtaining the flexible display panel.

Abstract: A light emitting device including first, second, and third light emitting stacks each including first and second conductivity type semiconductor layers, a first lower contact electrode in ohmic contact with the first light emitting stack, and second and third lower contact electrodes respectively in ohmic contact with the second conductivity type semiconductor layers of the second and third light emitting stacks, in which the first lower contact electrode is disposed between the first and second light emitting stacks, the second and third lower contact electrodes are disposed between the second and third light emitting stacks, and the first, second, and third lower contact electrodes include transparent conductive oxide layers.

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.

Abstract: A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device monolithically after CMOS processing. For example, the MEMS sensors are formed over a BEOL dielectric of a CMOS device. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

Abstract: A method for transferring a piezoelectric layer onto a support substrate comprises: —providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate, —forming a weakened zone in the piezoelectric substrate, so as to delimit the piezoelectric layer to be transferred, —providing the support substrate, —forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate, —bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and—fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.

Abstract: The present invention relates to the epitaxial lift-off of thin-films allowing the reuse of the expensive semiconductor substrates. In particular, it describes a structure and a method for epitaxial lift-off of several thin films from a single substrate (100) using a plurality of dissimilar sacrificial layers (101), strained layers (102, 104), and/or device or component layers (103). The properties of the sacrificial layers (101) and the strained layers (102,104) can be used (i) to facilitate the lift off process, (ii) to control the point of time of release of each released thin film individually and (iii) to aid in separation and sorting of the released thin films. The released device or component layers can comprise various useful structures, such as optoelectronic devices photonic components.

Abstract: A method of manufacturing a radiation imaging apparatus includes electrically connecting a first surface of a flexible insulating layer to a conductive portion of a circuit substrate, covering an exposed portion of the conductive portion with a protection layer, and separating the flexible insulating layer from a substrate in contact with a second surface of the flexible insulating layer. The circuit substrate includes an integrated circuit mounted on the circuit substrate. The flexible insulating layer includes, on the first surface, a plurality of pixels arranged in a two-dimensional matrix to convert radiation into an electrical signal. The second surface of the flexible insulating layer is opposite to the first surface of the flexible insulating layer. The flexible insulating layer is separated from the substrate by irradiating the second surface with light transmitting through the substrate.

Abstract: Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.

Abstract: A film forming method for forming an object film on a substrate including: providing the substrate including an oxide layer of a first material formed on a layer of the first material formed on a surface of a first area, and a layer of a second material formed on a surface of a second area, the second material being different from the first material; reducing the oxide layer; oxidizing a surface of the layer of the first material after reducing the oxide layer; and forming a self-assembled monolayer on the surface of the layer of the first material by supplying a raw material gas of the self-assembled monolayer after oxidizing the surface of the layer of the first material.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.

Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

Abstract: The present invention includes: a position detection unit (55) detecting positions of semiconductor chips and storing each detected position in a position database (56); a position correction unit (57) outputting a corrected bonding position; and a bonding control unit (58) performing bonding of the semiconductor chips based on the corrected bonding position input from the position correction unit (57). The position correction unit (57) calculates position shift amounts between the semiconductor chips of respective stages and an accumulated position shift amount, and when the accumulated position shift amount is greater than or equal to a predetermined threshold value, corrects the position of the semiconductor chip by the accumulated position shift amount and outputs it as the corrected bonding position, and the bonding control unit (58) performs bonding of the semiconductor chip of the next stage at the corrected bonding position input from the position correction unit.

Abstract: A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.

Abstract: Technologies for plasma oxidation protection during hybrid bonding of semiconductor devices includes forming a blocking layer on a metallic bonding pad formed in a bonding surface of a semiconductor device to be bonded and performing a surface treatment on the bonding surface to increase the bonding strength of the bonding surface and contemporaneously remove the blocking layer from the metallic bonding pad. In an illustrative embodiment, the blocking layer is embodied as a self-assembled monolayer (SAM), and the surface treatment is embodied as a surface activation plasma (SAP) treatment. A diffusion barrier layer, such as a silicon carbon nitride layer, may form the bonding surface in some embodiments to reduce diffusion of the metallic bonding pad during an annealing treatment of the bonding process.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes: providing a device wafer and a carrier wafer, the device wafer including an SOI substrate comprising, stacked from the bottom upward, a lower substrate, a buried insulator layer and a semiconductor layer; bonding the device wafer at a front side thereof to the carrier wafer; removing at least the lower substrate through thinning the device wafer from a backside thereof, wherein the backside of the device wafer opposes the front side thereof; and providing a high-resistance substrate and bonding the device wafer at the backside thereof to the high-resistance substrate, the high-resistance substrate having a resistivity higher than that of the lower substrate. With the present disclosure, lower signal loss and improved signal linearity can be achieved while avoiding a significant cost increase.

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer—which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth m

Abstract: A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.

Abstract: A method for producing a composite structure comprises providing a donor substrate including a single-crystal material, and a support substrate having a first alignment pattern on a face or edge of the support substrate. A heat treatment is applied at least to the donor substrate to bring about a surface reorganization on at least one face of the donor substrate. The surface reorganization results in formation of first steps of nanometric amplitude, which are parallel to a first main axis. The donor substrate and the support substrate are optically aligned, to better than ±0.1° between a locating mark indicating the first main axis on the donor substrate and at least one alignment pattern of the support substrate. The donor substrate and the support substrate are then assembled together, and a thin layer is transferred from the donor substrate onto the support substrate.

Abstract: A temporary adhesive has excellent spin coating properties of a circuit side of a wafer and a support, and excellent heat resistance when the circuit side of the wafer or the support is attached to an adhesion layer or a rear surface of the wafer is processed, and is capable of easily separating the circuit side of the wafer from the support after polishing the rear surface of the wafer, and simply removing an adhesive attached to the wafer or the support after the separation. The adhesive contains a component (A) to be cured by a hydrosilylation reaction, and a component (B) containing an epoxy-modified polyorganosiloxane at a ratio in % by mass of the component (A) to the component (B) of 99.995:0.005 to 30:70. The component (B) is an epoxy-modified polyorganosiloxane having an epoxy value of 0.1 to 5.

Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Abstract: A stretchable display device includes a stretchable substrate including a plurality of island areas that are separated from each other and a hinge area connecting the plurality of island areas, a plurality of display units respectively located in each of the plurality of island areas, a wiring part connecting the plurality of display units and located at the hinge area, and an insulating layer between the stretchable substrate and the plurality of display units. The insulating layer includes an opening overlapping the hinge area.

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

Abstract: A process for producing a monocrystalline layer of AlN material comprises the transfer of a monocrystalline seed layer of SiC-6H material to a carrier substrate of silicon material, followed by the epitaxial growth of the monocrystalline layer of AlN material.

Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.

Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Abstract: A micro light-emitting component, a micro light-emitting structure and a display device are disclosed. The micro light-emitting component has a micro light-emitting chip and a buffer element. The micro light-emitting chip has a first surface, a second surface opposite to the first surface and a plurality of outer sidewalls. The buffer element is disposed on the outer sidewalls or the first surface of the micro light-emitting chip. The buffer element has an inner surface and an outer surface. An angle is defined between the inner surface and the first surface or an extended surface of the first surface. The angle is greater than or equal to 90 degrees and less than or equal to 180 degrees. Therefore, the buffer element prevents the first surface of the micro light-emitting chip from damaging by collision when the micro light-emitting chip is dropped with the first surface facing down during a transferring procedure.

Abstract: A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.

Abstract: This disclosure provides a package structure for a semiconductor device, comprising a three-layer film consisting of a first SiO2 film, a Si3N4 film and a second SiO2 film stacked in this order, wherein the first SiO2 film is formed by a thermal oxidation process, the Si3N4 film is formed by a low pressure chemical vapor deposition process, and the second SiO2 film is formed by a low temperature atomic layer deposition process. This disclosure also provides a method for preparing the package structure for a semiconductor device.

Abstract: An image display element provides an image display element including a plurality of micro light-emitting elements arrayed in an array manner, and a semiconductor layer at which a drive circuit is disposed, the drive circuit being configured to supply a current to each of the plurality of micro light-emitting elements to cause light to be emitted, in which a transistor that constitutes the drive circuit and a wiring layer are disposed at a first surface of the semiconductor layer, the plurality of micro light-emitting elements are disposed at a second surface of the semiconductor layer that is an opposite side of the first surface, and the transistor and the wiring layer are electrically coupled to the micro light-emitting elements through a through substrate via that extends through the semiconductor layer.

Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

Abstract: A method of 3D printing to achieve a desired surface quality on at least one surface of a 3D printed object comprising selecting a base surface having the desired surface quality; and printing the 3D printed object on the base surface, so that the desired surface quality is imparted to one surface of the 3D printed object during printing. The surface quality may be glassiness, roughness, smoothness and texture in general. Objects may thus be manufactured in which electronic components are integrated in or under a glass-like surface.

Abstract: A substrate processing apparatus configured to process a substrate includes a holder configured to hold, in a combined substrate in which a first substrate and a second substrate are bonded to each other, the second substrate; and a modifying device configured to form, to an inside of the first substrate held by the holder, a peripheral modification layer by radiating laser light for periphery along a boundary between a peripheral portion of the first substrate as a removing target and a central portion thereof, and, also, configured to form an internal modification layer by radiating laser light for internal surface along a plane direction of the first substrate. The modifying device switches the laser light for periphery and the laser light for internal surface by adjusting at least a shape or a number of the laser light for periphery and the laser light for internal surface.

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.