Bonding Of Plural Semiconductor Substrates Patents (Class 438/455)
  • Patent number: 10811315
    Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Stefaan Van Huylenbroeck, Geert Van der Plas
  • Patent number: 10800947
    Abstract: Various embodiments disclosed related to a release layer including at least one fluorosilicon compound, and to related aspects such as methods for display device substrate processing. In various embodiments is a method of processing a display device substrate. The method can include securing the display device substrate to a carrier substrate with an adhesive delamination layer and a release layer between the adhesive delamination layer and the display device substrate. The release layer includes a cured product of a precursor release layer composition. The precursor release layer composition includes at least one fluorosilicon compound.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: October 13, 2020
    Assignee: Dow Silicones Corporation
    Inventors: Ginam Kim, Junying Liu
  • Patent number: 10796627
    Abstract: Integrated laser arrays based devices and systems and methods of forming the integrated laser arrays based devices and systems are provided. In one aspect, an integrated display includes a semiconductor substrate including a first side and a second side, an array of active-matrix light-emitting pixels, each of the pixels including one or more light-emitting elements formed on the first side and at least one non-volatile memory coupled to the one or more light-emitting elements, each of the light-emitting elements including a lasing structure that has an optical resonator and one or more semiconductor layers in the optical resonator and is operable to emit a laser light, one or more integrated circuits formed on the second side, and conductive interconnects penetrating from the second side through the semiconductor substrate and conductively coupling the one or more integrated circuits to the light-emitting elements.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 6, 2020
    Inventor: Shaoher Pan
  • Patent number: 10784927
    Abstract: An RFID tag is provided that transmits and receives a communication signal. The RFID tag includes a base material, antenna patterns provided on the base material, an RFIC package that is a feeding circuit connected to the antenna patterns, and an ignition protection member provided on the base material or the antenna patterns. Moreover, the ignition protection member contains moisture, such that ignition and combustion can be prevented even in a situation where the RFID tag is subjected to high-frequency power for heating a food item while attached to the food item or the like.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 22, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirokazu Yazaki, Noriyuki Ueki, Noboru Kato
  • Patent number: 10777533
    Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 15, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain
  • Patent number: 10777447
    Abstract: A method for determining a suitable implanting energy of at least two atomic species in a donor substrate to create a weakened zone defining a monocrystalline semiconductor layer to be transferred onto a receiver substrate, comprises the following steps: (i) forming a dielectric layer on at least one of the donor substrate and the receiver substrate; (ii) co-implanting the species in the donor substrate; (iii) bonding the donor substrate on the receiver substrate; (iv) detaching the donor substrate along the weakened zone to transfer the monocrystalline semiconductor layer and recover the remainder of the donor substrate; (v) inspecting the peripheral crown of the remainder of the donor substrate, or of the receiver substrate on which the monocrystalline semiconductor layer was transferred at step (iv); (vi) if the crown exhibits zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is too high; (vii) if said the crown does not exhibit zones transferred on
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 15, 2020
    Assignee: Soitec
    Inventors: Ludovic Ecarnot, Nadia Ben Mohammed, Carine Duret
  • Patent number: 10763130
    Abstract: Systems and methods are provided for producing an integrated circuit package, e.g., an SOIC package, having reduced or eliminated lead delamination caused by epoxy outgassing resulting from the die attach process in which an integrated circuit die is attached to a lead frame by an epoxy. The epoxy outgassing may be reduced by heating the epoxy during or otherwise in association with the die attach process, e.g. using a heating device provided at the die attach unit. Heating the epoxy may achieve additional cross-linking in the epoxy reaction, which may thereby reduce outgassing from the epoxy, which may in turn reduce or eliminate subsequent lead delamination. A heating device located at or near the die attach site may be used to heat the epoxy to a temperature of 55° C.±5° C. during or otherwise in association with the die attach process.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 1, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Taweesak Laevohan, Philbert Reyes, Jaggrit Vilairat, Sutee Thanaisawn, Janpen Phimphuang, Somsak Chunpangam
  • Patent number: 10747101
    Abstract: The present specification relates to a photomask, a laminate including the photomask, a method for manufacturing the photomask and a method for forming a pattern using the photomask.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 18, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Yong Goo Son, Kiseok Lee, Seung Heon Lee
  • Patent number: 10749089
    Abstract: A light emitting device package according to an embodiment includes: a package body; a light emitting device disposed on the package body; and an adhesive disposed between the package body and the light emitting device. The package body includes first and second openings passing through the package body on an upper surface of the package body and a recess provided to concave in a direction of a lower surface of the package body from the upper surface of the package body. The light emitting device includes a first bonding part disposed on the first opening and a second bonding part disposed on the second opening. The adhesive is provided at the recess.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 18, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sung Lee, Won Jung Kim, June O Song, Chang Man Lim
  • Patent number: 10734533
    Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 4, 2020
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 10727205
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • Patent number: 10720396
    Abstract: A semiconductor chip including a substrate including a plurality of chip areas and a line-shaped scribe area defining the chip areas, an integrated circuit (IC) structure on the chip area, the IC structure including a plurality of transistors and a plurality of stacked wiring structures connected to the transistors, and a warpage protector in the line-shaped scribe area and corresponding to the stacked wiring structures, the warpage protector supporting at least one side of the IC structure may be provided.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-Hyun Roh
  • Patent number: 10707258
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Patent number: 10692826
    Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 10679886
    Abstract: A workpiece treating method includes a step (1) of forming a stack including a support, a temporary fixing material and a workpiece wherein the material includes a layer containing a polymer (A) in a range of not less than 50 mass %, the polymer (A) including a structural unit represented by the formula (A1), and the workpiece is held on the material; a step (2) of processing the workpiece and/or transporting the stack; and a step (3) of applying a shear force to the material to thereby separate the workpiece from the support. R1 is a divalent organic group including at least one aromatic ring, each of two oxygen atoms bonded to R1 in (A1) is bonded to the aromatic ring, and, when R1 includes two or more aromatic rings, each of the two oxygen atoms is bonded to any one of the aromatic rings.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 9, 2020
    Assignee: JSR CORPORATION
    Inventors: Hiroyuki Ishii, Hitoshi Katou, Hiroki Ishikawa, Noriko Kitahama, Hirofumi Sasaki, Hikaru Mizuno
  • Patent number: 10679854
    Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shuai Guo, Jia Wen Wang, Tao Tao Ding, Rui Yuan Xing, Xiao Jin Wang, Jia You Wang, Chun Long Li
  • Patent number: 10672891
    Abstract: A method of forming a stacked gate all around MOSFET is provided. A stack of alternating layers of Si and SiGe are formed on a substrate. A number of holes are etched through the stack and Si anchors formed in the holes. The SiGe layers are removed. A number of dummy gates are formed on the substrate and a Low-K spacer material deposited around the dummy gates. A number of S/D recesses are etched through the Si layers, removing the Si anchors. The dummy gates and spacer material preserves sections of the Si layers during etching, forming stacks of Si channels. S/Ds are formed in the recesses. The dummy gates are then removed replaced with metal gate stacks.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Choonghyun Lee, Jingyun Zhang
  • Patent number: 10652967
    Abstract: A workstation assembly comprising an emissive surface assembly including a substantially contiguous emissive surface on which visual content may be presented, the emissive surface assembly including emissive surface sections including first and second substantially flat emissive surface sections wherein one of the first and second flat sections is substantially horizontal and the other of the first and second flat sections is at least somewhat vertical, first and second curved surface sections that are curved about first and second non-parallel axis, the first curved section positioned between and adjacent the first and second flat surface sections, the second curved section adjacent an edge of the first substantially flat emissive surface section, each of the curved and flat surface sections forming a portion of the substantially contiguous emissive surface, a support structure and a driver.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: May 12, 2020
    Assignee: STEELCASE INC.
    Inventor: Mark A. Baloga
  • Patent number: 10643848
    Abstract: A method for minimizing an average surface includes: forming an epitaxial layer on a growth substrate; forming the soft metal layer on the epitaxial layer in which the average surface roughness of a bonding surface of the soft metal layer is greater than a first value; forming a glue layer on a carrier substrate; placing a combination of the glue layer and the carrier substrate on the bonding surface in which the glue layer being in contact with the bonding surface of the soft metal layer; and applying an external pressure to compress the glue layer and the soft metal layer such that the average surface roughness of the bonding surface of the soft metal layer is reduced from the first value to a second value, wherein the second value is less than 80 nm.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 5, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10636774
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A first encapsulant is deposited over the first substrate and semiconductor die after forming the conductive pillar. A groove is formed in the first encapsulant around the conductive pillar. A first passive device is disposed over a second substrate. A second encapsulant is deposited over the first passive device and second substrate. The first substrate is mounted over the second substrate. A shielding layer is formed over the second encapsulant. A second passive device can be mounted over the second substrate opposite the first passive device and outside a footprint of the first substrate.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 28, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee
  • Patent number: 10629439
    Abstract: A method for minimizing an average surface includes: forming an epitaxial layer on a growth substrate; forming the soft metal layer on the epitaxial layer in which the average surface roughness of a bonding surface of the soft metal layer is greater than a first value; forming a glue layer on a carrier substrate; placing a combination of the glue layer and the carrier substrate on the bonding surface in which the glue layer being in contact with the bonding surface of the soft metal layer; and performing a laser lift-off process to separate the growth substrate from the epitaxial layer such that the average surface roughness of the bonding surface of the soft metal layer is reduced to be less than a second value. The second value is smaller than the first value, and the second value is less than 80 nm.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 21, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10629568
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Patent number: 10622327
    Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a first semiconductor workpiece; depositing a first film on a first surface of the semiconductor workpiece; depositing a second film on a substrate that is transmissive to light within a predetermined wavelength range; and bonding the first film to the second film under a predetermined bonding temperature and a predetermined bonding pressure.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 10622246
    Abstract: A substrate bonding method includes: preparing a first substrate having a first silicon oxide film with a film thickness of 50 nm or more arranged on the first substrate, and a second substrate having a second silicon oxide film arranged on the second substrate; bonding the first substrate and the second substrate together in a state where the first silicon oxide film and the second silicon oxide film face each other; and heating and bonding the first substrate and the second substrate. The preparing of the first substrate and the second substrate includes preparing the second substrate having the second silicon oxide film with a film thickness of 2.5 nm or less. The heating and bonding of the first substrate and the second substrate includes heating the first substrate and the second substrate at a temperature of 200° C. or more and 800° C. or less.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 14, 2020
    Assignee: DENSO CORPORATION
    Inventor: Masakazu Yatou
  • Patent number: 10607937
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 31, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Javier A. DeLaCruz
  • Patent number: 10582609
    Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 3, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Jonghae Kim, Xiaoju Yu, Mario Francisco Velez, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Matthew Michael Nowak, Christian Hoffmann, Rodrigo Pacher Fernandes, Manuel Hofer, Peter Bainschab, Edgar Schmidhammer, Stefan Leopold Hatzl
  • Patent number: 10580752
    Abstract: A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: March 3, 2020
    Assignee: BONDTECH CO., LTD.
    Inventor: Akira Yamauchi
  • Patent number: 10566288
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate and a conductive bond pad is separated from the substrate by the dielectric layer. A back-side through-substrate-via (BTSV) extends through the substrate and the dielectric layer. A conductive bump is arranged over the conductive bond pad. The conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump. A BTSV liner separates sidewalls of the BTSV from the substrate. The sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Patent number: 10541346
    Abstract: Improved high work function back contacts for solar cells are provided. In one aspect, a method of forming a solar cell includes: forming a completed solar cell having a substrate coated with an electrically conductive material, an absorber disposed on the electrically conductive material, a buffer layer disposed on the absorber, a transparent front contact disposed on the buffer layer, and a metal grid disposed on the transparent front contact; removing the substrate and the electrically conductive material using exfoliation, exposing a backside surface of the solar cell; depositing a high work function material onto the back side surface of the solar cell; and depositing a back contact onto the high work function material. A solar cell formed by the present techniques is also provided. Yield of the exfoliated device can be improved by removing bubbles from adhesive used for exfoliation and/or forming contact pads to access the metal grid.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Priscilla D. Antunez, Douglas M. Bishop, Gloria W. Fraczak, Oki Gunawan, Richard A. Haight
  • Patent number: 10522574
    Abstract: A method for manufacturing a display device is provided. The method includes a step of forming a first layer over a first substrate, a terminal electrode over the first layer, a display element over the first layer, and a peeling layer overlapping with the terminal electrode, a step of forming a second layer over a second substrate, a step of attaching the first substrate to the second substrate with a bonding layer therebetween, a step of separating the first substrate from the first layer, a step of attaching a third substrate to the first layer, a step of separating the second substrate from the second layer together with part of the bonding layer, and a step of attaching a fourth substrate to the second layer. At least one of the first layer and the second layer includes an organic film.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihiro Chida, Tatsuya Sakuishi, Daiki Nakamura, Tomoya Aoyama, Kohei Yokoyama, Daisuke Kubota
  • Patent number: 10522510
    Abstract: A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Jacob M. Jensen, Patrick Morrow, Paul B. Fischer
  • Patent number: 10510543
    Abstract: A semiconductor device includes an n?-type drift layer of an formed on an n+-type SiC substrate; a p-type layer provided on a surface opposite that facing the n+-type SiC substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n?-type drift layer and the n+-type SiC substrate, the n-type buffer layer having an impurity concentration higher than that of the n?-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 1×1012/cm3 or higher. The buffer layer promotes internal electron-hole recombination and without applying high energy to BPDs at an interface of the buffer layer and the SiC substrate, may reduce the amount of recombination near the interface even at a current density equivalent to that of a conventional structure and thereby, prevents characteristics degradation at the time of operation.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shinichiro Matsunaga
  • Patent number: 10510532
    Abstract: Disclosed is a method of fabricating a gallium nitride substrate using a plurality of ion implantation processes.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea Gun Park, Jae Hyoung Shim, Tae Hun Shim
  • Patent number: 10460925
    Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 29, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Hsu Ting, Kuang-Hsiu Chen, Chun-Wei Yu, Keng-Jen Lin, Yu-Ren Wang
  • Patent number: 10438920
    Abstract: There is provided a bonding apparatus for bonding substrates together, which includes: a first holding part configured to adsorptively hold a first substrate by vacuum-drawing the first substrate on a lower surface of the first substrate; a second holding part provided below the first holding part and configured to adsorptively hold a second substrate by vacuum-drawing the second substrate on an upper surface of the second substrate; a pressing member provided in the first holding part and configured to press a central portion of the first substrate; and a plurality of substrate detection parts provided in the first holding part and configured to detect a detachment of the first substrate from the first holding part.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 8, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshitaka Otsuka, Takashi Nakamitsu, Yosuke Omori, Kenji Sugakawa
  • Patent number: 10393796
    Abstract: In one aspect, a method comprises providing at least two identical front-end-of-line (FEOL) portions of an integrated circuit (IC) in a single wafer, with at least some of each FEOL portion comprising a plurality of circuit elements; building a design back-end-of-line (BEOL) portion of the IC on at least one of the FEOL portions to form a product chip, with the design BEOL portion configuring design-type interconnections of the same plurality of circuit elements for a first instantiation; building a test-only BEOL structure on at least one of the FEOL portions to form a sacrificial test device, with the test-only BEOL structure configuring test-type interconections of the same plurality of circuit elements for a second instantiation; and testing the sacrificial test device for at least one of functionality or reliability.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 27, 2019
    Assignee: Carnegie Mellon University
    Inventors: Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan
  • Patent number: 10388545
    Abstract: Device and method for alignment of a first contact surface of a first substrate with a second contact surface of a second substrate which can be held on a second platform. The device includes first X-Y positions of first alignment keys located along the first contact surface, and second X-Y positions of second alignment keys which correspond to the first alignment keys and which are located along the second contact surface, wherein the first contact surface can be aligned based on the first X-Y positions in the first alignment position and the second contact surface can be aligned based on the second X-Y positions in the second alignment position.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: August 20, 2019
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Daniel Figura
  • Patent number: 10376986
    Abstract: An apparatus, system and method for the processing of orifices in materials by laser filamentation that utilizes an optical configuration that focuses the incident laser light beam in a distributed manner along the longitudinal beam axis. This distributed focusing method enables the formation of filaments over distances, and the laser and focusing parameters are adjusted to determine the filament propagation and termination points so as to develop a single/double end stopped orifice, or a through orifice. Selected transparent substrates from a stacked or nested configuration may have orifices formed therein/therethrough without affecting the adjacent substrate. These distributed focusing methods support the formation filaments with lengths well beyond ten millimeters in borosilicate glass and similar brittle materials and semiconductors.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 13, 2019
    Assignee: ROFIN-SINAR TECHNOLOGIES LLC
    Inventor: S. Abbas Hosseini
  • Patent number: 10381261
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew Marquis Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Patent number: 10357942
    Abstract: A graphite-silicon composite, including: graphite; silicon; and an intermediate layer that is located between the graphite and the silicon, wherein the intermediate layer includes oxygen, carbon and silicon. Furthermore, provided is a method for producing a graphite-silicon composite, including: layering graphite and silicon; and heating the layered graphite and silicon while applying pressure to them, wherein, during heating the layered graphite and silicon while applying pressure to them, an oxygen concentration in the atmosphere is adjusted to 0.2 vol %, the applied pressure is adjusted to 24.5 MPa or higher, and the heating temperature is adjusted to 1260° C. or higher.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuhiro Nishikawa, Naomi Nishiki, Hidetoshi Kitaura, Atsushi Tanaka, Kimiaki Nakaya, Henrik Rønnow
  • Patent number: 10354907
    Abstract: A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 16, 2019
    Assignee: CHIP SOLUTIONS, LLC
    Inventor: Sukianto Rusli
  • Patent number: 10340249
    Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun Hui Yu
  • Patent number: 10325897
    Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
  • Patent number: 10319593
    Abstract: Disclosed herein is a wafer thinning method for thinning a wafer formed from an SiC substrate having a first surface and a second surface opposite to the first surface. The wafer thinning method includes an annular groove forming step of forming an annular groove on the second surface of the SiC substrate in an annular area corresponding to the boundary between a device area and a peripheral marginal area in the condition where a thickness corresponding to the finished thickness of the wafer after thinning is left, and a separation start point forming step of applying the laser beam to the second surface as relatively moving a focal point and the SiC substrate to thereby form a modified layer and cracks inside the SiC substrate at the predetermined depth.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 11, 2019
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Hiroshi Morikazu, Karl Priewasser
  • Patent number: 10204812
    Abstract: A method and corresponding device for the alignment of a first substrate comprising at least two first alignment marks with a second substrate comprising at least two second alignment marks. By means of a first assignment, the first alignment marks are assigned to at least two first characteristic alignment features of the first substrate in an X-direction and in a Y-direction. By means of a second assignment, the second alignment marks are assigned to at least two second characteristic alignment features of the second substrate in an X-direction and in a Y-direction, and by means of an alignment, the first and second alignment marks are aligned in relation to one another in an X- and Y-direction by means of the first and second characteristic alignment features.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 12, 2019
    Assignee: EV Group E. Thallner GmbH
    Inventor: Viorel Dragoi
  • Patent number: 10198890
    Abstract: A hybrid high-security document includes a document and one or more independent light-emitting modules disposed on or embedded in the document. Each module comprises an antenna with multiple turns, an electronic circuit, and a light emitter mounted and electrically connected on a substrate separate from the document. The electronic circuit is responsive to electrical power provided from the antenna to control the light emitter to emit light. The electronic circuit can include a memory storing information relevant to the hybrid high-security document or its use. The information can be accessed by external readers providing electromagnetic energy to the hybrid high-security document. The hybrid high-security document can be a hybrid banknote.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 5, 2019
    Assignee: X-Celeprint Limited
    Inventors: Robert R. Rotzoll, Christopher Bower, Ronald S. Cok
  • Patent number: 10177204
    Abstract: A method for manufacturing a display substrate, a display substrate and a display device are disclosed. The method includes: forming a thin-film transistor (TFT) array on a base substrate to form an array substrate; and forming a pixel define layer (PDL) on a non-pixel region of the array substrate by a patterning process. A photochromic material is uniformly distributed in the PDL; the PDL provided with the photochromic material can be converted from light-transmitting to light-shielding under action of light illumination; and the process that the PDL is converted from light-transmitting to light-shielding is irreversible.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 8, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wei Li, Youngsuk Song, Jingang Fang, Hongda Sun
  • Patent number: 10170447
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 10164219
    Abstract: To improve the yield in a peeling process and improve the yield in a manufacturing process of a flexible light-emitting device or the like, a peeling method includes a first step of forming a peeling layer over a first substrate, a second step of forming a layer to be peeled including a first layer in contact with the peeling layer over the peeling layer, a third step of curing a bonding layer in an overlapping manner with the peeling layer and the layer to be peeled, a fourth step of removing part of the first layer overlapping with the peeled layer and the bonding layer to form a peeling starting point, and a fifth step of separating the peeling layer and the layer to be peeled. The peeling starting point is preferably formed by laser light irradiation.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoya Aoyama, Akihiro Chida, Ryu Komatsu
  • Patent number: 10090424
    Abstract: A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The bonded substrate is then coated with a first precursor solution to provide a coated bonded substrate. Finally, the procedure de-bonds the coated bonded substrate to provide a first solar cell device and a second solar cell device. A system for fabricating the solar cell comprises a first precursor solution deposition system containing a first precursor solution for deposition on a substrate, a first heating element for heating the substrate after deposition of the first precursor solution, a second precursor solution deposition system containing a second precursor solution for deposition on the substrate, and a second heating element for heating the substrate after deposition of the second precursor solution.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 2, 2018
    Assignee: Magnolia Solar, Inc.
    Inventors: Gopal G. Pethuraja, Roger E. Welser, Ashok K. Sood