Bonding Of Plural Semiconductor Substrates Patents (Class 438/455)
  • Patent number: 11515413
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at lea
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: November 29, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventor: Zvi Or-Bach
  • Patent number: 11515373
    Abstract: The resent disclosure provides an OLED substrate, a photo mask, and a method of manufacturing the OLED substrate. In one embodiment, an OLED substrate includes: a base substrate; an anode layer on the base substrate; a pixel defining layer on the anode layer, the pixel defining layer having a pattern opening area, the pattern opening area including a plurality of pixel openings arranged in an array manner; and a light-emitting layer formed on the pixel defining layer by evaporation; wherein the pattern opening area has an inward contraction structure with respect to a regular pixel opening area structure in which a plurality of pixel openings are arranged in a manner of an regular array where rows in the regular array are equally spaced from each other and are parallel to each other and columns in the regular array are equally spaced from each other and are parallel to each other.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 29, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Bowen Yang, Fei Xie, Chengguo An, Yubin Song, Yudong Shang, Pengsha Ma, Xiaodong Yang, Junjiao Chen
  • Patent number: 11506922
    Abstract: A light modulating device including: a light transmissive plate having a curved surface; a light modulating cell; and an optically transparent adhesive film which is disposed between the curved surface of the light transmissive plate and the light modulating cell and attaches one side of the light modulating cell to the curved surface of the light transmissive plate.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: November 22, 2022
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Yusuke Hagiwara
  • Patent number: 11504958
    Abstract: The invention relates to a method for transferring at least one layer of material, comprising: producing first and second separating layers (108, 110), one against the other, on a first substrate (104); producing the layer to be transferred on the second separating layer (110); securing the layer to be transferred to a second substrate (106), forming a stack of different materials; and performing mechanical separation at the interface between the separating layers; in which the materials of the stack are such that the interface between the first and second separating layers has the weakest adhesion force, and the method comprises a step reducing an initial adhesion force of the interface between the first and second separating layers.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 22, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Gwenaël Le Rhun, Christel Dieppedale, Stéphane Fanget
  • Patent number: 11502162
    Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer overlapping the first semiconductor layer, and a wiring structure arranged between them. The second semiconductor layer is provided with p-type MIS transistor. A crystal structure of the first semiconductor layer has a first crystal orientation and a second crystal orientation in direction along a principal surface of the first semiconductor layer. A Young's modulus of the first semiconductor layer in a direction along the first crystal orientation is higher than that in a direction along the second crystal orientation. An angle formed by the first crystal orientation and a direction in which a source and a drain of the p-type MIS transistor are arranged is more than 30 degrees and less than 60 degrees, and an angle formed by the second crystal orientation and that direction is 0 degrees or more and 30 degrees or less.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Katsunori Hirota, Hiroaki Kobayashi
  • Patent number: 11488965
    Abstract: An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n?1; the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m?n+1.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 1, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Yi-Hsung Wei, Pei-Hsiu Tseng, Jia-You Lin
  • Patent number: 11483937
    Abstract: An example of a method of making a printed structure comprises providing a destination substrate, contact pads disposed on the destination substrate, and a layer of adhesive disposed on the destination substrate. A stamp with a component adhered to the stamp is provided. The component comprises a stamp side in contact with the stamp and a post side opposite the stamp side, a circuit, and connection posts extending from the post side. Each of the connection posts is electrically connected to the circuit. The component is pressed into contact with the adhesive layer to adhere the component to the destination substrate and to form a printed structure having a volume defined between the component and the destination substrate. The stamp is removed and the printed structure is processed to fill or reduce the volume.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 25, 2022
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Andrew Bower, Matthew Alexander Meitl, Brook Raymond, Salvatore Bonafede
  • Patent number: 11476111
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 11462453
    Abstract: The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 4, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tse-Yao Huang, Shing-Yih Shih
  • Patent number: 11462676
    Abstract: A method for adjusting the stress state of a piezoelectric film having a first stress state at room temperature includes a step of forming an assembly including a carrier having a thermal expansion coefficient, a compliant layer placed on the carrier, and the piezoelectric film placed on the compliant layer, the piezoelectric film having a thermal expansion coefficient different from that of the carrier. The method also includes a step of heat treating the assembly, in which the assembly is heated to a treatment temperature above the glass transition temperature of the compliant layer. The present disclosure also relates to a process for fabricating an acoustic wave device comprising the piezoelectric layer the stress state of which was adjusted as described herein.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 4, 2022
    Assignee: Soitec
    Inventors: Jean-Marc Bethoux, Yann Sinquin, Damien Radisson
  • Patent number: 11456263
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 11456169
    Abstract: A wafer structure and a trimming method thereof are provided. The trimming method includes the following steps. A first wafer having a first surface and a second surface opposite to the first surface is provided. A first pre-trimming mark is formed on the first surface of the first wafer, where forming the first pre-trimming mark includes forming a plurality of recesses arranged as a path along a periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Ning Chiang, Ming-Te Chuang
  • Patent number: 11456184
    Abstract: A method is provided. In the method, a substrate having a first region and a second region on a substrate surface is provided. A film deposition material to form a first chemical bond in the first region and a second chemical bond in the second region is supplied to the substrate surface. The second bond has a second bond energy lower than a first bond energy of the first chemical bond. A film is selectively formed in the first region by supplying an energy lower than the first bond energy of the first chemical bond and higher than the second bond energy of the second chemical bond.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 27, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Ryuichi Asako, Tatsuya Yamaguchi
  • Patent number: 11428673
    Abstract: Provided is an ultrasonic inspection device for inspecting a packaged semiconductor device, The ultrasonic inspection device including an ultrasonic transducer that is disposed to face the semiconductor device; a medium holding unit that is provided at an end of the ultrasonic transducer facing the semiconductor device and holds a medium through which ultrasonic waves are propagated; a stage that moves the position of the semiconductor device relative to the ultrasonic transducer; and an analysis unit that analyzes the reaction of the semiconductor device in accordance with input of the ultrasonic waves from the ultrasonic transducer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 30, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Toru Matsumoto
  • Patent number: 11430875
    Abstract: A first barrier layer, a channel layer, a second barrier layer, and a first bonding layer made of high-resistance AlGaN doped with Fe are formed on a first substrate. Thereafter, the first substrate and the second substrate are pasted in a state where the first bonding layer and a second bonding layer made of high-resistance GaN doped with Fe are opposed to each other.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 30, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Takuya Hoshi, Yuki Yoshiya, Hiroki Sugiyama, Hideaki Matsuzaki
  • Patent number: 11430728
    Abstract: A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 30, 2022
    Assignee: General Electric Company
    Inventors: Marco Francesco Aimi, Joseph Alfred Iannotti, Joleyn Eileen Brewer
  • Patent number: 11424174
    Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11424837
    Abstract: Methods and systems for large silicon photonic interposers by stitching are disclosed and may include, in an optical communication system including a silicon photonic interposer, where the interposer includes a plurality of reticle sections: communicating an optical signal between first and second reticle sections utilizing a waveguide. The waveguide may include a taper region at a boundary between the two reticle sections, the taper region expanding an optical mode of the communicated optical signal prior to the boundary and narrowing the optical mode after the boundary. A continuous wave (CW) optical signal may be received in a first of the reticle sections from an optical source external to the interposer. The CW optical signal may be received in the interposer from an optical source assembly coupled to a grating coupler in the first of the reticle sections in the silicon photonic interposer.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 23, 2022
    Assignee: Cisco Technology, INC
    Inventors: Peter De Dobbelaere, Attila Mekis, Gianlorenzo Masini
  • Patent number: 11417628
    Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: August 16, 2022
    Assignee: AP Memory Technology Corporation
    Inventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien An Yu, Chun Yi Lin
  • Patent number: 11407066
    Abstract: A method for creating a detachment zone in a solid includes: providing a solid which is to be processed; providing a laser light source; subjecting the solid to laser radiation from the laser light source so that laser beams penetrate into the solid via a surface of the solid portion that is to be cut off; applying the laser radiation in a defined manner to a predefined portion of the solid inside the solid such that a detachment zone or a plurality of partial detachment zones is formed; wherein a number of modifications are successively created in the crystal lattice by the applied laser radiation, and the crystal lattice fissures at least partially in the regions surrounding the modifications as a result of the modifications, the fissures in the region of the modifications predefining the detachment zone or the plurality of partial detachment zones.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: August 9, 2022
    Assignee: Siltectra GmbH
    Inventors: Jan Richter, Christian Beyer, Ralf Rieske
  • Patent number: 11404300
    Abstract: The present invention discloses a semiconductor-on-diamond-on-carrier substrate wafer. The semiconductor-on-diamond-on-carrier wafer comprises: a semiconductor-on-diamond wafer having a diamond side and semiconductor side; a carrier substrate disposed on the diamond side of the semiconductor-on-diamond wafer and including at least one layer having a lower coefficient of thermal expansion (CTE) than diamond; and an adhesive layer disposed between the diamond side of the semiconductor-on-diamond wafer and the carrier substrate to bond the carrier substrate to the semiconductor-on-diamond wafer. The semiconductor-on-diamond-on-carrier substrate wafer has the following characteristics: a total thickness variation of no more than 40 ?m; a wafer bow of no more than 100 ?m; and a wafer warp of no more than 40 ?m.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 2, 2022
    Inventors: Daniel Francis, Frank Yantis Lowe, Michael Ian Pearson
  • Patent number: 11404582
    Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 2, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Patent number: 11398479
    Abstract: An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Abhishek A. Sharma, Ravi Pillarisetty, Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang
  • Patent number: 11393869
    Abstract: An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 19, 2022
    Assignee: Raytheon Company
    Inventors: Jeffery H. Burkhart, Sean P. Kilcoyne, Eric Miller
  • Patent number: 11393712
    Abstract: The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: July 19, 2022
    Assignees: Zing Semiconductor Corporation, SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Xing Wei, Nan Gao, Zhongying Xue
  • Patent number: 11387205
    Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu, Sen-Bor Jan
  • Patent number: 11388525
    Abstract: A MEMS microphone and a manufacturing method thereof are provided. The MEMS microphone comprises a MEMS microphone chip and a housing with an acoustic port. The MEMS microphone chip is mounted in the housing, and a mesh plug is mounted in the acoustic port and made from a mesh material which has a mesh structure that is suitable for passage of sound.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 12, 2022
    Assignee: Weifang Goertek Microelectronics Co., Ltd.
    Inventor: Quanbo Zou
  • Patent number: 11385278
    Abstract: A bonded structure is disclosed. The bonded structure can include a first semiconductor element having a first front side and a first back side opposite the first front side. The bonded structure can include a second semiconductor element having a second front side and a second back side opposite the second front side, the first front side of the first semiconductor element directly bonded to the second front side of the second semiconductor element along a bond interface without an adhesive. The bonded structure can include security circuitry extending across the bond interface, the security circuitry electrically connected to the first and second semiconductor elements.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Guy Regev
  • Patent number: 11380550
    Abstract: A wafer processing method for processing a wafer of a two-layer structure having a second wafer laminated on a front surface of a first wafer includes a stepped part forming step of cutting from the second wafer side to a peripheral surplus region of the first wafer to a depth corresponding to a finished thickness of the first wafer, thereby removing a chamfered part formed at a peripheral end of the second wafer and forming an annular stepped part in the peripheral surplus region of the first wafer, and a second wafer griding step of, after the stepped part forming step is carried out, grinding an exposed surface of the second wafer to make the second wafer to have a predetermined thickness.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: July 5, 2022
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 11380576
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 5, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Patent number: 11361969
    Abstract: Provided are a device substrate with high thermal conductivity, with high heat dissipation, and with a small loss at high frequencies, and a method of manufacturing the device substrate. A device substrate 1 of the present invention can be manufactured by: provisionally bonding a Si device layer side of an SOI device substrate 10 to a support substrate 20 using a provisional bonding adhesive 31, the SOI device substrate including a Si base substrate 11, a buried layer 12 formed on the Si base substrate, having high thermal conductivity, and being an electrical insulator, and a Si device layer 13 formed on the buried layer; removing the Si base substrate 11 of the provisionally bonded SOI device substrate until the buried layer is exposed, thereby obtaining a thinned device wafer 10a; transfer-bonding the buried layer side of the thinned device wafer and a transfer substrate 40 to each other using a transfer adhesive 32 having a heat-resistant temperature of at least 150° C.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 14, 2022
    Inventors: Yoshihiro Kubota, Shigeru Konishi
  • Patent number: 11362288
    Abstract: The disclosure relates to the technical field of display, and provides a flexible display screen, a method for deformably driving the same, and a display device. The flexible display screen includes a flexible display panel and a deformable driver disposed on a back surface of the flexible display panel. The deformable driver drives the flexible display panel to deform based on the electrodeformation. The deformable driver includes a plurality of deformable units arranged in an array. The flexible display screen can achieve deformation with a variety of degrees of freedom, and can precisely control the deformation, thereby easy to achieve ultra-thin screen design.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 14, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Junhuan Liu, Tianxiao Zhao, Ruifeng Yang, Huaxu Yang, Tong Li
  • Patent number: 11355441
    Abstract: A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 7, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kazushiro Nomura, Mie Matsuo
  • Patent number: 11355382
    Abstract: To improve peelability, yield in a peeling step, and yield in manufacturing a flexible device. A peeling method is employed which includes a first step of forming a peeling layer containing tungsten over a support substrate; a second step of forming, over the peeling layer, a layer to be peeled formed of a stack including a first layer containing silicon oxynitride and a second layer containing silicon nitride in this order and forming an oxide layer containing tungsten oxide between the peeling layer and the layer to be peeled; a third step of forming a compound containing tungsten and nitrogen in the oxide layer by heat treatment; and a fourth step of peeling the peeling layer from the layer to be peeled at the oxide layer.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 7, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiji Yasumoto, Masataka Sato, Shingo Eguchi, Kunihiko Suzuki
  • Patent number: 11329059
    Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: May 10, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11320948
    Abstract: A film touch sensor in which a conductive pattern layer and a separation layer are sequentially disposed, and a base film is disposed on at least one surface of the conductive pattern layer and the separation layer, includes a capping layer which is disposed between the separation layer and the conductive pattern layer and includes SiOxNy (0?x?4, y=4?x), thereby it is possible to improve visibility of an image and reduce a resistance of the conductive pattern layer, and a method for fabricating the same.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 3, 2022
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Yong-Seok Choi, Seung Kook Kim, Jong Hee Kim, Min Seok Seo
  • Patent number: 11315789
    Abstract: Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 26, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kiyotaka Imai, Hirokazu Aizawa, Hiroshi Maeda, Kaoru Maekawa, Yuji Mimura, Harunobu Suenaga
  • Patent number: 11296045
    Abstract: A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joohee Jang, Seokho Kim, Hoonjoo Na, Jaehyung Park, Kyuha Lee
  • Patent number: 11282706
    Abstract: A method and a corresponding device for bonding a first substrate with a second substrate at mutually facing contact faces of the substrates. The method includes holding of the first substrate to a first holding surface of a first holding device and holding of the second substrate to a second holding surface of a second holding device. A change in curvature of the contact face of the first substrate and/or a change in curvature of the contact face of the second substrate are controlled during the bonding.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 22, 2022
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Thomas Plach, Jurgen Markus Suss
  • Patent number: 11271079
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 8, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, John J. Pekarik, Vibhor Jain, John J. Ellis-Monaghan
  • Patent number: 11264532
    Abstract: Provided a manufacturing method of a semiconductor light emitting device including forming a plurality of light emitting cells that are separated on a first substrate, forming a first planarization layer by providing an insulating material on the plurality of light emitting cells, forming a second planarization layer by providing a photoresist on the first planarization layer to have a flat upper surface, and soft baking the photoresist, and dry etching the second planarization layer to a predetermined depth to expose a portion of the first planarization layer provided on the plurality of light emitting cells, and a portion of the second planarization layer remaining between the plurality of light emitting cells on the first planarization layer, wherein forming the second planarization layer and dry etching are repeated at least once to remove the portion of the second planarization layer provided between the plurality of light emitting cells.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daeyeop Han, Kiwon Park, Jaeyoon Kim, Sungjoon Kim, Inho Kim
  • Patent number: 11251149
    Abstract: A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 15, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11230036
    Abstract: A method and apparatus for delaminating a polymer film from a carrier plate is disclosed. The carrier plate is at least partially transparent and has deposited on it a pixelated pattern layer of light-absorptive material, upon which is deposited a layer of light-reflective material. A polymer film, which is to be delaminated, is deposited on the light-reflecting material layer. Next, a pulsed light source is utilized to irradiate through the carrier plate from the side opposite the polymer film to heat the light-absorptive material layer. The heated areas of the light-absorptive material layer, in turn, heat the polymer film through conduction at the interface between the light-absorptive material layer and the polymer film, thereby generating gas from the polymer film by its thermal decomposition, which allows the polymer film to be released from the carrier plate.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: January 25, 2022
    Assignee: NCC NANO, LLC
    Inventors: Rob Jacob Hendriks, Kurt A. Schroder
  • Patent number: 11233159
    Abstract: In fabricating a semiconductor structure, a group IV substrate and a group III-V chiplet are provided. The group III-V chiplet is bonded to the group IV substrate, and patterned to produce a patterned group III-V device. A blanket dielectric layer is formed over the patterned group III-V device. A first contact hole is formed in the blanket dielectric layer over a first portion of the patterned group III-V device. A first liner stack and a first filler metal are subsequently formed in the first contact hole. A second contact hole is formed in the blanket dielectric layer over a second portion of the patterned group III-V device. A second liner stack and a second filler metal are subsequently formed in the second contact hole. A first bottom metal liner of the first liner stack can be different from a second bottom metal liner of the second liner stack.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 25, 2022
    Assignee: Newport Fab, LLC
    Inventors: Edward Preisler, Zhirong Tang
  • Patent number: 11228088
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes an antenna layer having a feeding region and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding region of the antenna layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11222824
    Abstract: A method for transferring a superficial layer from a detachable structure comprises the following steps: a) supplying the detachable structure comprising: •a support substrate, •a detachable layer arranged on the support substrate along a main plane and comprising a plurality of walls that are separated from one another, each wall having at least one side that is perpendicular to the main plane; •a superficial layer arranged on the detachable layer along the main plane; b) applying a mechanical force configured to cause said walls to bend, along a direction that is secant to said side, until causing the mechanical rupture of the walls, in order to detach the superficial layer from the support substrate.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: January 11, 2022
    Assignee: SOITEC
    Inventor: Michel Bruel
  • Patent number: 11220423
    Abstract: Provided herein is a method including forming a MEMS cap. A cavity is formed in the MEMS cap wafer, and a bond material is deposited on the MEMS cap wafer, wherein the bond material lines the cavity after the depositing. The MEMS cap wafer is bonded to a MEMS device wafer, wherein the bond material forms a bond between the MEMS cap wafer and the MEMS device wafer. A MEMS device is formed in the MEMS device wafer. The bond material is removed from the cavity.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: January 11, 2022
    Assignee: InvenSense, Inc.
    Inventors: Ian Flader, Dongyang Kang
  • Patent number: 11195711
    Abstract: A method of healing defects generated in a semiconducting layer by implantation of species made in a substrate to form therein an embrittlement plane separating a solid part of the substrate from the semiconducting layer, the semiconducting layer having a front face through which the implanted species pass. The method comprises local annealing of the substrate causing heating of the semiconducting layer, the intensity of which decreases from the front face towards the embrittlement plane. The local annealing may comprise a laser irradiation of a front surface of the substrate.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Pablo Acosta Alba, Frédéric Mazen, Sébastien Kerdiles, Sylvain Maitrejean
  • Patent number: 11193208
    Abstract: A wafer/support arrangement, including a wafer, a support system, which includes a support and an elastomer layer, and a connecting layer, wherein the connecting layer is a sol-gel layer. The invention further relates to a coated wafer for a wafer/support arrangement according to the invention, wherein a sol-gel layer is used as a connecting layer for a corresponding wafer/support assembly, and to a method for processing the back side of a wafer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 7, 2021
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventor: Phillipp Lorenz
  • Patent number: 11187940
    Abstract: A backlight module having a surface light source, a liquid crystal display panel, and a welding method of a light-emitting diode chip are provided. The backlight module having a surface light source including: a first pad and a second pad disposed on a substrate; a plurality of pad holes disposed in the first pad and the second pad; a magnetic film layer disposed in the plurality of pad holes; a solder paste disposed both on the first pad and the second pad; a light-emitting diode chip, wherein a plurality of pins disposed on two sides of the light-emitting diode chip are absorbed on the magnetic film layer and are connected to both the first pad and the second pad respectively by the solder paste.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 30, 2021
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yong Yang