Abstract: A method and apparatus for wafer bonding. The method includes that, a first position parameter of a first alignment mark on a first wafer is determined by using a optical beam; a second position parameter of a second alignment mark on a second wafer is determined with the optical beam, the optical beam has a property of transmitting through a wafer; a relative position between the first wafer and the second wafer is adjusted with the optical beam according to the first position parameter and the second position parameter until the relative position between the first alignment mark and the second alignment mark satisfies a predetermined bonding condition; and the first wafer is bonded to the second wafer.

Abstract: A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Abstract: A method of forming an optoelectronic semiconductor device involves providing an amorphous substrate. A transparent and conductive oxide layer is deposited on the amorphous substrate. The transparent and conductive oxide layer is annealed to form an annealed transparent and conductive oxide layer having a cubic-oriented and/or rhombohedral-oriented surface. A nanorod array is formed on the cubic-oriented and/or rhombohedral-oriented surface of the annealed transparent and conductive oxide layer. The annealing of the transparent conductive oxide layer and the formation of the nanorod array are performed using molecular beam epitaxy (MBE). The nanorods of the nanorod array comprise a group-III material and are non-polar.

Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: The present disclosure provides a semiconductor device package including a first substrate, a second substrate disposed over the first substrate, an electronic component disposed between the first substrate and the second substrate, a spacer disposed between the first substrate and the electronic component, and a supporting element disposed on the first substrate and configured to support the second substrate. The spacer is configured to control a distance between the first substrate and the second substrate through the electronic component. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A microsensor for detecting ions in a fluid, comprises: a field-effect transistor having a source, a drain, an active region between the source and the drain, and a gate disposed above the active region, an active layer, in which the active region is formed, a dielectric layer positioned beneath the active layer, a support substrate disposed under the dielectric layer and comprising at least one buried cavity located plumb with the gate of the field-effect transistor in order to receive the fluid.

Abstract: A bonding method includes attracting and holding a first substrate by using a first holder; attracting and holding a second substrate by using a second holder; and forming a combined substrate by moving the first holder and the second holder relative to each other to bring the first substrate and the second substrate into contact with each other. The bonding method includes heating the first substrate and the second substrate or the combined substrate; and cooling the heated combined substrate by using a cooling unit. In the cooling, bending of the combined substrate is controlled by forming a temperature difference in the combined substrate.

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop f

Abstract: A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

Abstract: A conveying unit for conveying a device chip onto a predetermined electrode of a board has a chip chuck that holds under suction one surface of the device chip, a support base to which the chip chuck is fixed in an inclinable manner, and a moving unit that moves the support base, in which a fixing mechanism that fixes the chip chuck to the support base has a plurality of leaf springs extending laterally radially from the chip chuck, the plurality of leaf springs are connected to the support base in the surroundings of the chip chuck, and the plurality of leaf springs are pulled one another, so that the chip chuck is supported in air in an inclinable manner.

Abstract: The present application makes public a magnetic memory and a reading/writing method thereof, which magnetic memory comprises at least one cell layer, and the cell layer includes a plurality of parallel second wires that are disposed in a second plane, the first plane being parallel to the second plane, and projections of the second wires onto the first plane intercrossing the first wires; a plurality of storage elements that are disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bi-directional gating components connected in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first wires, the bi-directional gating components being connected to the second wires, and the bi-directional gating components being configured to be conductive upon application of a threshold voltage and/or a threshold current.

Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

Abstract: A first regrowth layer and a second regrowth layer comprising GaAs having high resistance are regrown on a surface of an etching stop layer exposed to the bottom of a first groove and a second groove, and then n-type InGaAs is regrown on the first regrowth layer and the second regrowth layer, whereby a source region and a drain region configured to make contact with a channel layer are formed in the first groove and the second groove respectively.

Abstract: An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 ?m interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment.

Abstract: A method for bonding semiconductor devices is provided. The method may include several operations. A wafer and a chip are formed. The wafer and the chip are disposed in a low-pressure environment. A planar surface of the chip is moved toward a planar surface of the wafer. A void is formed between the planar surface of the chip and the planar surface of the wafer. The chip is bonded to the wafer. A bonded structure of the chip and the wafer is disposed under a standard atmosphere and a size of the void is reduced. A system for forming a semiconductor structure is also provided.

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

Abstract: A method for fabricating a device having a cavity, includes: obtaining a device wafer including a first substrate and a device structure formed on the first substrate, depositing a first dielectric layer on the device wafer, etching the first dielectric layer to expose at least a part of the device structure and a part of the first substrate, depositing, after the etching, a second dielectric layer on the device wafer and the first dielectric layer, performing a surface treatment on a surface of the second dielectric layer, obtaining a second substrate, and bonding the second substrate with the second dielectric layer on the device wafer, thereby forming the cavity between the second substrate and the device wafer.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: Provided is a semiconductor device manufacturing method in which semiconductor elements are formed into multiple layers through the lamination of wafers in which the semiconductor elements are fabricated, the method being suited for efficiently creating multiple layers of thin wafers while suppressing warping of a wafer laminate. The method of the present invention includes a preparation step, a thinning step, a bonding step, a removal step, and a multilayering step. In the preparation step, a reinforced wafer is prepared, the reinforced wafer having a laminated structure that includes: a wafer including an element forming surface and a back surface opposite from the element forming surface; a supporting substrate; and a temporary adhesive layer for forming temporary adhesion, the temporary adhesive layer being provided between the element forming surface side of the wafer and the supporting substrate.

Abstract: A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C.

Abstract: A highly thermal conductive substrate formed by bonding a device layer formed on a silicon on insulator (SOI) wafer and a buried oxide film to an insulator substrate having a thermal conductivity of 40 W/m·K or more via a low-stress adhesive, wherein a thickness of the buried oxide film is 50 to 500 nm and a thickness of the adhesive is 0.1 to 10 ?m.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Abstract: A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.

Abstract: A pressure sensor comprises a first sensing module comprising a first negative electrode and first support structures arranged at intervals on the first negative electrode. A first flexible insulating layer covers an upper surface of the first support structures and first positive electrodes are arranged at intervals on a lower surface of the first flexible insulating layer and distributed between the first support structures. A second sensing module comprises a second negative electrode disposed on the first flexible insulating layer and second support structures are arranged at intervals on the second negative electrode. A second flexible insulating layer covers an upper surface of the second support structures. Second positive electrodes are arranged on a lower surface of the second flexible insulating layer at intervals and distributed between the second support structures. The first support structures are offset from the second support structures.

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

Abstract: A device, a system and a method for bonding two substrates. A first substrate holder has a recess and an elevation.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: An example of a method of micro-transfer printing comprises providing a micro-transfer printable component source wafer, providing a stamp comprising a body and spaced-apart posts, and providing a light source for controllably irradiating each of the posts with light through the body. Each of the posts is contacted to a component to adhere the component thereto. The stamp with the adhered components is removed from the component source wafer. The selected posts are irradiated through the body with the light to detach selected components adhered to selected posts from the selected posts, leaving non-selected components adhered to non-selected posts. In some embodiments, using the stamp, the selected components are adhered to a provided destination substrate. In some embodiments, the selected components are discarded. An example micro-transfer printing system comprises a stamp comprising a body and spaced-apart posts and a light source for selectively irradiating each of the posts with light.

Abstract: The substrate joining method is a substrate joining method for joying two substrates, including a hydrophilic treatment step of hydrophilizing at least one of respective joint surfaces of the two substrates that are to be joined to each other and a joining step of joining the two substrates after the hydrophilic treatment step. The hydrophilic treatment step includes a step of performing a N2 RIE treatment to perform reactive ion etching using N2 gas on the joint surfaces of the substrates and a step of performing a N2 radical treatment to irradiate the joint surfaces of the substrates with N2 radicals after the step of performing the N2 RIE treatment.

Abstract: A process for producing a monocrystalline layer of LNO material comprises the transfer of a monocrystalline seed layer of YSZ material to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of LNO material.

Abstract: Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support.

Abstract: A method of manufacturing thin film transistor(s) includes: providing a monocrystalline silicon wafer, the monocrystalline silicon wafer including a first surface and a second surface that are opposite to each other; forming a bubble layer between the first surface and the second surface of the monocrystalline silicon wafer, the bubble layer dividing the monocrystalline silicon wafer into two portions arranged side by side in a direction perpendicular to the second surface, and a portion of the monocrystalline silicon wafer that is located between the bubble layer and the second surface being a monocrystalline silicon film having a target thickness; providing a substrate, and transferring the monocrystalline silicon film onto the substrate by breaking the monocrystalline silicon wafer at the bubble layer; and patterning the monocrystalline silicon film transferred to the substrate to form active layer(s) of the thin film transistor(s).

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

Abstract: A bonding system includes a first holder and a second holder arranged to be spaced apart from each other in a vertical direction; a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between a first substrate held by the first holder and a second substrate held by the second holder; a pressing unit configured to press the first substrate and the second substrate against each other; a measuring unit configured to measure a position deviation between an alignment mark on the first substrate and an alignment mark on the second substrate, the first substrate and the second substrate being bonded by the pressing unit; and a position adjustment controller configured to control the position adjustment in the horizontal direction in a currently-performed bonding processing based on the position deviation generated in a previously-performed bonding processing.

Abstract: A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.

Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

Abstract: According to various embodiments, provided is an electrical element transfer apparatus comprising: a fixing jig in which each of a plurality of electrical elements is arranged at a predetermined interval; a movement jig movably arranged at an upper part of the fixing jig, and including a plurality of first accommodating grooves for accommodating at least a part of each of the plurality of electrical elements; and an attraction device arranged around the movable jig and attaching each of the plurality of electrical elements through the movable jig to the first accommodating groove of the movable jig through magnetic force. Additional various embodiments are possible.

Abstract: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.

Abstract: A light emitting device including a substrate, a light emitting structure disposed on the substrate and having a first light emitting region, a second light emitting region, and a third light emitting region, and an insulation layer to block unintended electrical connection between the first light emitting region and the second light emitting region, or between the second light emitting region and the third light emitting region, in which each of the first light emitting region, the second light emitting region, and the third light emitting region comprises a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, and a center of the first light emitting region overlaps a center of the second light emitting region and a center of the third light emitting region.

Abstract: A method of co-manufacturing silicon waveguides, SiN waveguides, and semiconductor structures in a photonic integrated circuit. A silicon waveguide structure can be formed using a suitable process, after which it is buried in a cladding. The cladding is polished, and a silicon nitride layer is disposed to define a silicon nitride waveguide. The silicon nitride waveguide is buried in a cladding, and annealed. Thereafter, cladding above the silicon waveguide structure can be trenched through, and low-temperature operations can be performed to or with an exposed surface of the silicon waveguide structure.

Abstract: A stretchable display device includes a stretchable substrate including a plurality of island areas that are separated from each other and a hinge area connecting the plurality of island areas, a plurality of display units respectively located in each of the plurality of island areas, a wiring part connecting the plurality of display units and located at the hinge area, and an insulating layer between the stretchable substrate and the plurality of display units. The insulating layer includes an opening overlapping the hinge area.

Abstract: A method for manufacturing a semiconductor device and a semiconductor substrate are provided. A method for manufacturing a semiconductor device includes the steps of forming a bonding layer that bonds a semiconductor thin film to a bonding layer region on a portion of a first substrate with a force weaker than covalent bonding, forming the semiconductor thin film in the bonding layer region and a non-bonding layer region other than the bonding layer region, separating the semiconductor thin film from the first substrate by bonding an organic layer included in a pick-up substrate different from the first substrate to the semiconductor thin film, removing the bonding layer adhered to a peeled surface of the semiconductor thin film separated from the first substrate, and bonding the semiconductor thin film from which the bonding layer has been removed to a second substrate different from the first substrate.

Abstract: A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111>oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used.