Bonding Of Plural Semiconductor Substrates Patents (Class 438/455)
  • Patent number: 10381261
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew Marquis Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Patent number: 10376986
    Abstract: An apparatus, system and method for the processing of orifices in materials by laser filamentation that utilizes an optical configuration that focuses the incident laser light beam in a distributed manner along the longitudinal beam axis. This distributed focusing method enables the formation of filaments over distances, and the laser and focusing parameters are adjusted to determine the filament propagation and termination points so as to develop a single/double end stopped orifice, or a through orifice. Selected transparent substrates from a stacked or nested configuration may have orifices formed therein/therethrough without affecting the adjacent substrate. These distributed focusing methods support the formation filaments with lengths well beyond ten millimeters in borosilicate glass and similar brittle materials and semiconductors.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 13, 2019
    Assignee: ROFIN-SINAR TECHNOLOGIES LLC
    Inventor: S. Abbas Hosseini
  • Patent number: 10357942
    Abstract: A graphite-silicon composite, including: graphite; silicon; and an intermediate layer that is located between the graphite and the silicon, wherein the intermediate layer includes oxygen, carbon and silicon. Furthermore, provided is a method for producing a graphite-silicon composite, including: layering graphite and silicon; and heating the layered graphite and silicon while applying pressure to them, wherein, during heating the layered graphite and silicon while applying pressure to them, an oxygen concentration in the atmosphere is adjusted to 0.2 vol %, the applied pressure is adjusted to 24.5 MPa or higher, and the heating temperature is adjusted to 1260° C. or higher.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuhiro Nishikawa, Naomi Nishiki, Hidetoshi Kitaura, Atsushi Tanaka, Kimiaki Nakaya, Henrik Rønnow
  • Patent number: 10354907
    Abstract: A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 16, 2019
    Assignee: CHIP SOLUTIONS, LLC
    Inventor: Sukianto Rusli
  • Patent number: 10340249
    Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun Hui Yu
  • Patent number: 10325897
    Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
  • Patent number: 10319593
    Abstract: Disclosed herein is a wafer thinning method for thinning a wafer formed from an SiC substrate having a first surface and a second surface opposite to the first surface. The wafer thinning method includes an annular groove forming step of forming an annular groove on the second surface of the SiC substrate in an annular area corresponding to the boundary between a device area and a peripheral marginal area in the condition where a thickness corresponding to the finished thickness of the wafer after thinning is left, and a separation start point forming step of applying the laser beam to the second surface as relatively moving a focal point and the SiC substrate to thereby form a modified layer and cracks inside the SiC substrate at the predetermined depth.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 11, 2019
    Assignee: DISCO CORPORATION
    Inventors: Kazuya Hirata, Yoko Nishino, Hiroshi Morikazu, Karl Priewasser
  • Patent number: 10204812
    Abstract: A method and corresponding device for the alignment of a first substrate comprising at least two first alignment marks with a second substrate comprising at least two second alignment marks. By means of a first assignment, the first alignment marks are assigned to at least two first characteristic alignment features of the first substrate in an X-direction and in a Y-direction. By means of a second assignment, the second alignment marks are assigned to at least two second characteristic alignment features of the second substrate in an X-direction and in a Y-direction, and by means of an alignment, the first and second alignment marks are aligned in relation to one another in an X- and Y-direction by means of the first and second characteristic alignment features.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 12, 2019
    Assignee: EV Group E. Thallner GmbH
    Inventor: Viorel Dragoi
  • Patent number: 10198890
    Abstract: A hybrid high-security document includes a document and one or more independent light-emitting modules disposed on or embedded in the document. Each module comprises an antenna with multiple turns, an electronic circuit, and a light emitter mounted and electrically connected on a substrate separate from the document. The electronic circuit is responsive to electrical power provided from the antenna to control the light emitter to emit light. The electronic circuit can include a memory storing information relevant to the hybrid high-security document or its use. The information can be accessed by external readers providing electromagnetic energy to the hybrid high-security document. The hybrid high-security document can be a hybrid banknote.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 5, 2019
    Assignee: X-Celeprint Limited
    Inventors: Robert R. Rotzoll, Christopher Bower, Ronald S. Cok
  • Patent number: 10177204
    Abstract: A method for manufacturing a display substrate, a display substrate and a display device are disclosed. The method includes: forming a thin-film transistor (TFT) array on a base substrate to form an array substrate; and forming a pixel define layer (PDL) on a non-pixel region of the array substrate by a patterning process. A photochromic material is uniformly distributed in the PDL; the PDL provided with the photochromic material can be converted from light-transmitting to light-shielding under action of light illumination; and the process that the PDL is converted from light-transmitting to light-shielding is irreversible.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 8, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wei Li, Youngsuk Song, Jingang Fang, Hongda Sun
  • Patent number: 10170447
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 10164219
    Abstract: To improve the yield in a peeling process and improve the yield in a manufacturing process of a flexible light-emitting device or the like, a peeling method includes a first step of forming a peeling layer over a first substrate, a second step of forming a layer to be peeled including a first layer in contact with the peeling layer over the peeling layer, a third step of curing a bonding layer in an overlapping manner with the peeling layer and the layer to be peeled, a fourth step of removing part of the first layer overlapping with the peeled layer and the bonding layer to form a peeling starting point, and a fifth step of separating the peeling layer and the layer to be peeled. The peeling starting point is preferably formed by laser light irradiation.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoya Aoyama, Akihiro Chida, Ryu Komatsu
  • Patent number: 10090424
    Abstract: A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The bonded substrate is then coated with a first precursor solution to provide a coated bonded substrate. Finally, the procedure de-bonds the coated bonded substrate to provide a first solar cell device and a second solar cell device. A system for fabricating the solar cell comprises a first precursor solution deposition system containing a first precursor solution for deposition on a substrate, a first heating element for heating the substrate after deposition of the first precursor solution, a second precursor solution deposition system containing a second precursor solution for deposition on the substrate, and a second heating element for heating the substrate after deposition of the second precursor solution.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 2, 2018
    Assignee: Magnolia Solar, Inc.
    Inventors: Gopal G. Pethuraja, Roger E. Welser, Ashok K. Sood
  • Patent number: 10079171
    Abstract: The present invention relates to a method for the production of at least one three-dimensional layer of solid material, in particular for usage as wafer, and/or at least one tree-dimensional solid body.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: September 18, 2018
    Assignee: Siltectra, GmbH
    Inventor: Jan Richter
  • Patent number: 10036949
    Abstract: A mask is provided for vapor deposition. The mask includes a plurality of effective open areas each of which includes apertures formed therein and extending therethrough to define hollow openings through which a deposition material is allowed to pass. The mask also includes ineffective areas that include solid portions located around the effective open areas. The ineffective areas include recesses formed therein such that the ineffective areas that have the same surface area as that of the effective open areas are made to have substantially the same mass as that of the effective open areas.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: July 31, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Taipi Wu
  • Patent number: 10037903
    Abstract: Provided is a bonding device for bonding a substrate and an electronic part of an assembled body which is formed by mounting the electronic part on the substrate with a metal particle paste sandwiched therebetween. The bonding device is configured to bond the substrate and the electronic part to each other by heating a pressure applying unit having a first transfer member and a second transfer member which transfer pressure and heat to the assembled body n a state where the assembled body is sandwiched between the first transfer member and the second transfer member while applying pressure to the pressure applying unit. The bonding device further includes a heating mechanism part having a first heating part and a second heating part arranged at positions opposite to each other, a positioning mechanism part, and a pressure applying mechanism part.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 31, 2018
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Ryo Matsubayashi
  • Patent number: 10034378
    Abstract: A curved display device includes a semiconductor chip package including a base film, a plurality of driving chips on the base film, and an input wire unit and an output wire unit connected to the driving chips, a printed circuit board (PCB) connected to the input wire unit of the semiconductor chip package, and a display panel including a display unit and a pad unit connected to the output wire unit of the semiconductor chip package, wherein the display panel, the semiconductor chip package, and the PCB are bendable in a first direction, and the driving chips of the of the semiconductor chip package are separated from each other in the first direction.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Man Bok Jeon
  • Patent number: 10002882
    Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 19, 2018
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Frederic Allibert, Christophe Maleville
  • Patent number: 9978973
    Abstract: An organic light emitting display apparatus including a substrate including a plurality of pixel areas; a pixel electrode on the substrate; an opposite electrode on the pixel electrode, the opposite electrode transmitting light; an organic light emitting layer between the pixel electrode and the opposite electrode, the organic light emitting layer emitting a first light toward the opposite electrode; a light emitting layer on the opposite electrode, the light emitting layer absorbing a portion of the first light and emitting a second light; and a sealing layer on the light emitting layer, the sealing layer sealing the pixel electrode, the opposite electrode, the organic light emitting layer, and the light emitting layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chi-O Cho, Byungchoon Yang, Young-Jun Seo, Won Sang Park
  • Patent number: 9972603
    Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang
  • Patent number: 9962908
    Abstract: The present invention provides a method for firmly and inexpensively bonding at low temperature a polymer film to another polymer film or to a glass substrate without the use of an organic adhesive. A method for bonding a polymer film includes a step (S1) for forming a first inorganic material layer on part or all of a first polymer film; a step (S3) for forming a second inorganic material layer on part or all of a second polymer film; a step (S2) for surface-activating the surface of the first inorganic material layer by bombarding with particles having a predetermined kinetic energy; a step (S4) for surface-activating the surface of the second inorganic material layer by bombarding with particles having a predetermined kinetic energy; and a step (S5) for abutting the surface-activated surface of the first inorganic material layer against the surface-activated surface of the second inorganic material layer and bonding the first polymer film and second polymer film together.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: May 8, 2018
    Assignee: LAN TECHNICAL SERVICE CO., LTD.
    Inventors: Tadatomo Suga, Yoshiie Matsumoto
  • Patent number: 9947714
    Abstract: In a method of manufacturing an image sensor, photodiodes may be formed on a semiconductor layer in an active pixel region and a peripheral region. A structure including insulating interlayers and wiring structures may be formed on a first surface of the semiconductor layer in the active pixel region, the peripheral region and an input/output (I/O) region. The semiconductor layer and a first insulating interlayer of the insulating interlayers on the I/O region may be partially etched to form a via hole exposing a first wiring structure of the wiring structures. A first metal layer and a second metal layer may be formed on a second surface of the semiconductor layer and the via hole. The second metal layer may be patterned to form a second pad pattern on the semiconductor layer in the I/O region. An anti-reflective layer may be formed on the first metal layer and the second pad pattern.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Ho Lee, Hyun-Pil Noh
  • Patent number: 9941319
    Abstract: A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 10, 2018
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Patent number: 9922954
    Abstract: This method includes steps a) providing the first structure and second structure, the first structure including a surface on which a silicon layer is formed; b) bombarding the silicon layer by a beam (F) of species configured to reach the surface of the first structure, and to preserve a part of the silicon layer with a surface roughness of less than 1 nm RMS on completion of the bombardment; c) bonding the first structure and second structure by direct bonding between the part of the silicon layer preserved in step b) and the second structure, steps b) and c) being executed in the same chamber subjected to a vacuum of less than 10?2 mbar.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 20, 2018
    Assignee: COMMISARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Hubert Moriceau, Frank Fournel, Christophe Morales
  • Patent number: 9865545
    Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 9, 2018
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Maurice Rivoire, Viorel Balan
  • Patent number: 9859112
    Abstract: A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate. At least one implant species is implanted between the epitaxial layer and the first semiconductor substrate to form an ion-implanted layer. The epitaxial layer is bonded to a bonding oxide layer of a second semiconductor substrate. The first semiconductor substrate is separated from the ion-implanted layer.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Jing-Cheng Lin
  • Patent number: 9852903
    Abstract: A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 26, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 9837300
    Abstract: A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Kazutaka Kuriki
  • Patent number: 9837374
    Abstract: Provided is a device in which the metal content existing in a joining interface is controlled. A manufacturing method for the device comprises: a step in which the surfaces of a first substrate and a second substrate are activated using a FAB gun; a step in which a plurality of metals are discharged by using the FAB gun to sputter a discharged metal body comprising the plurality of metals, and the plurality of metals are affixed to the surfaces of the first substrate and the second substrate; a step in which the first substrate and the second substrate are joined at room temperature; and a step in which heating is performed at a temperature that is high in comparison to the agglomeration start temperature of the plurality of metals and of the elements that constitute the first substrate or the second substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 5, 2017
    Assignee: KYOCERA CORPORATION
    Inventors: Hideki Matsushita, Masanobu Kitada
  • Patent number: 9812371
    Abstract: The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 7, 2017
    Assignee: Soitec
    Inventor: Thierry Barge
  • Patent number: 9790088
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
  • Patent number: 9779982
    Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Frank Fournel
  • Patent number: 9772447
    Abstract: A method of producing a heterogeneous photonic integrated circuit includes integrating at least one III-V hybrid device on a source substrate having at least a top silicon layer, and transferring by transfer-printing or by flip-chip bonding the III-V hybrid device and at least part of the top silicon layer of the source substrate to a semiconductor-on-insulator or dielectric-on-insulator host substrate.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: September 26, 2017
    Assignees: IMEC VZW, Universiteit Gent
    Inventors: Shahram Keyvaninia, Dries Van Thourhout, Gunther Roelkens
  • Patent number: 9761542
    Abstract: Embodiments of the present invention provide an improved method and structure for flip chip implementation. The interconnections between the electronic circuit (e.g. silicon die) and the circuit board substrate are comprised of a metal alloy that becomes liquid at the operating temperature of the chip. This allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Sylvestre, Assane Ndieguene, Pierre Albert
  • Patent number: 9735398
    Abstract: To improve the yield in a peeling process and improve the yield in a manufacturing process of a flexible light-emitting device or the like, a peeling method includes a first step of forming a peeling layer over a first substrate, a second step of forming a layer to be peeled including a first layer in contact with the peeling layer over the peeling layer, a third step of curing a bonding layer in an overlapping manner with the peeling layer and the layer to be peeled, a fourth step of removing part of the first layer overlapping with the peeled layer and the bonding layer to form a peeling starting point, and a fifth step of separating the peeling layer and the layer to be peeled. The peeling starting point is preferably formed by laser light irradiation.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: August 15, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoya Aoyama, Akihiro Chida, Ryu Komatsu
  • Patent number: 9722072
    Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Kuen Chang, Chia-Min Hung, Shih-Yin Hsiao
  • Patent number: 9718261
    Abstract: A method for assembling two substrates by molecular adhesion comprises: a first step (a) of putting first and second substrates in close contact in order to form an assembly having an assembly interface; a second step (b) of reinforcing the degree of adhesion of the assembly beyond a threshold adhesion value at which water is no longer able to diffuse along the assembly interface. The method also comprises a step (c) of anhydrous treatment of the first and second substrates in a treatment atmosphere having a dew point below ?10° C., and control of the dew point of a working atmosphere to which the first and second substrates are exposed from the anhydrous treatment step (c) until the end of the second step (b) so as to limit or prevent the appearance of bonding defects at the assembly interface.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 1, 2017
    Assignees: SOITEC, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Landru, Capucine Delage, Franck Fournel, Elodie Beche
  • Patent number: 9713256
    Abstract: A curved display device includes a semiconductor chip package including a base film, a plurality of driving chips on the base film, and an input wire unit and an output wire unit connected to the driving chips, a printed circuit board (PCB) connected to the input wire unit of the semiconductor chip package, and a display panel including a display unit and a pad unit connected to the output wire unit of the semiconductor chip package, wherein the display panel, the semiconductor chip package, and the PCB are bendable in a first direction, and the driving chips of the of the semiconductor chip package are separated from each other in the first direction.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Man Bok Jeon
  • Patent number: 9673174
    Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsun Lee
  • Patent number: 9653623
    Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yi-Koan Hong, Yeun-Sang Park, Byung-Lyul Park, Joo-Hee Jang
  • Patent number: 9640418
    Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: May 2, 2017
    Assignee: SUSS MicroTec Lithography GmbH
    Inventors: Hale Johnson, Gregory George
  • Patent number: 9633903
    Abstract: A device manufacturing method according to an embodiment includes forming a film on the side of a second surface of a substrate having a first surface and the second surface, cutting the substrate, cutting the film, and injecting particles onto at least one of a first cut portion formed by the cutting of the substrate and a second cut portion formed by the cutting of the film, to process the at least one of the first cut portion or the second cut portion.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 25, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamune Takano
  • Patent number: 9633981
    Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: April 25, 2017
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Robert N. Chylak, Dominick A. DeAngelis
  • Patent number: 9633952
    Abstract: Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: April 25, 2017
    Assignee: MEMSEN ELECTRONICS INC.
    Inventor: Lianjun Liu
  • Patent number: 9627287
    Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Edward Fuergut, Hannes Eder
  • Patent number: 9627578
    Abstract: The present invention relates to an epitaxial wafer for a light-emitting diode wherein the peak emission wavelength is 655 nm or more, and it is possible to improve reliability. The epitaxial wafer for light-emitting diodes includes a GaAs substrate (1) and a pn-junction type light-emitting unit (2) provided on the GaAs substrate (1), wherein light-emitting unit (2) is formed as a multilayer structure in which a strained light-emitting layer and a barrier layer are alternately stacked, and the composition formula of the barrier layer is (AlXGa1-X)YIn1-YP (0.3?X?0.7, 0.51?Y?0.54).
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: April 18, 2017
    Assignee: SHOWA DENKO K.K.
    Inventors: Noriyoshi Seo, Atsushi Matsumura, Ryouichi Takeuchi
  • Patent number: 9627295
    Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Anurag Jindal, Jian He, Lalapet Rangan Vasudevan, Kyle K. Kirby, Hongqi Li
  • Patent number: 9620493
    Abstract: A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether each of the dies has a defect; storing a result of checking whether each of the dies has a defect and information regarding each of the multi-dies; forming virtual combined structures by combining and stacking all the multi-dies in a predetermined number of layers; forming 3D semiconductor groups by calculating yields of the combined structures based on the result of checking whether each of the dies has a defect and the information regarding each of the multi-dies, selecting a combined structure having a highest yield from among the combined structures, and stacking the multi-dies to have the same structure as the selected combined structure; and forming a 3D semiconductor chip by dividing the 3D semiconductor groups in units of dies.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 11, 2017
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Joonsung Yang, Soonkwan Kwon
  • Patent number: 9620481
    Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Patent number: 9612492
    Abstract: A display may have a thin-film transistor layer and color filter layer. The display may have an active area and an inactive border area. Light blocking structures in the inactive area may prevent stray backlight from a backlight light guide plate from leaking out of the display. The thin-film transistor layer may have a clear substrate, a patterned black masking layer on the clear substrate, a clear planarization layer on the black masking layer, and a layer of thin-film transistor circuitry on the clear planarization layer. The black masking layer may be formed from black photoimageable polyimide. The clear planarization layer may be formed from spin-on glass. The light blocking structures may include a first layer formed from a portion of the black masking layer and a second layer such as a layer of black tape on the underside of the color filter layer.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 4, 2017
    Assignee: Apple Inc.
    Inventors: Byung Duk Yang, Kyung-Wook Kim, Shih-Chang Chang, Hiroshi Osawa, Hirokazu Yamagata, Daisuke Nozu