Abstract: A first structure of a circuit configuration and a first alignment structure are produced in the region of a surface of a first substrate. The first alignment structure scatters electron beams differently than its surroundings. A second substrate, which is more transmissive to electron beams than the first alignment structure, is connected to the first substrate in such a way that the second substrate is disposed above the surface of the first substrate. In order to align a mask with respect to the first structure, a position of the first alignment structure is determined with the aid of electron beams. With the aid of the mask, at least one second structure of the circuit configuration is produced in the region of an uncovered upper surface of the second substrate. The first structure may be a metallic line encapsulated by insulating material. A contact may connect the first structure to the second structure.

Abstract: An improved method for making silicon-on-sapphire transducers including the steps of: forming a first silicon layer on a first side of a first sapphire wafer; bonding a second sapphire wafer to the first side of the first sapphire wafer such that the first silicon layer is interposed between the first and second sapphire wafers; reducing the thickness of the first sapphire wafer to a predetermined thickness; depositing a second silicon layer on a second surface of the first sapphire wafer, wherein the second surface of the first sapphire wafer is oppositely disposed from the first surface of the first sapphire wafer; bonding a silicon wafer to the second surface of the first sapphire wafer such that the second silicon layer is interposed between the first sapphire wafer and the silicon wafer, wherein the silicon wafer includes p+ regions indicative of a transducer structure and non-p+ regions; and, removing the non-p+ regions of the silicon wafer thus forming the transducer structure of p+

Abstract: The invention is to a device and the method of making circuit devices with side wall contacts produced on a semiconductor wafer (30) by forming grooves (33,34) partially through the wafer surface to provide a plurality of device elements (32) on a common base (31). After the groves are made in the semiconductor wafer, each device element has a top surface (36) and side surfaces (35a-35d). A semiconductor device or integrated circuit is then formed (32) in the top and side surfaces by well know techniques, including diffusing and deposition processes, to form a semiconductor device. Contact pads are formed on both the top and sides of the device to provide a greater density of contacts for the semiconductor device. The semiconductor devices are separated along the grooves (33,34) to provide individual devices.

Abstract: A method for making a microstructure assembly, the method including the steps of providing a first substrate and a second substrate; depositing an electrically conductive material on the second substrate; contacting the second substrate carrying the electrically conductive material with the first substrate; and then supplying current to the electrically conductive material to locally elevate the temperature of said electrically conductive material and cause formation of a bond between the first substrate and the second substrate.

Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer forming part of a dedicated SOI substrate presenting a first and second monocrystalline silicon wafer separated by an insulting layer having an air gap. A well is formed in the second wafer over the air gap and is subsequently trenched up to the air gap to release the monocrystalline silicon mass forming the movable mass of the sensor; the movable mass has two numbers of movable electrodes facing respective pluralities of fixed electrodes. In the idle condition, each movable electrode is separated by different distances from the two fixed electrodes facing the movable electrode.

Abstract: A compound die may be formed of two dies each having face and back sides, said dies being connected with said dies in face to face alignment. A radiation communication system may be used to assist in aligning the dies and in providing communications between the two dies. In this way, a composite structure may be produced which has advanced capabilities, a small footprint, and low impedance.

Abstract: There is disclosed a semiconductor sensor device comprising a semiconductor diaphragm member having a top surface coated with an oxide layer; P+ sensor elements fusion bonded to the oxide layer at a relatively central area of the diaphragm; P+ finger elements fusion bonded to the oxide layer extending from the sensors to an outer contact location of the diaphragm for each finger; and an external rim of P+ material fusion bonded to the oxide layer and surrounding the sensors and fingers. A first glass wafer member is electrostatically bonded at a bottom surface to the fingers and rim to hermetically seal the sensors and fingers of the diaphragm member.

Abstract: An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

Abstract: A process for the preparation of hermetically sealed electronically active microstructures involves the preparation of a plurality of microstructures and associated conductive paths and lead bond areas on a single wafer such that areas surrounding the microstructures are maintained in a planar condition. A second wafer having a plurality of microstructure-receiving cavities is placed atop the first wafer and fusion or anodically bonded. The microstructures are preferably connected to lead bond pads which lie outside the surround, the second wafer also having bond pad accessing through-holes to facilitate bonding electrical leads to the devices after sawing from the wafer. The lead-connected devices may be further encapsulated by injection molding, potting, or other conventional encapsulative packaging techniques.

Abstract: In a process for producing a semiconductor substrate, comprising sealing surface pores of a porous silicon layer and thereafter forming a single-crystal layer on the porous silicon layer by epitaxial growth, intermediate heat treatment is carried out after the sealing and before the epitaxial growth and at a temperature higher than the temperature at the time of the sealing. This process improves crystal quality of the semiconductor substrate having the single-crystal layer formed by epitaxial growth and improves smoothness at the bonding interface when applied to bonded wafers this process enables the detection of the smaller particles on the surface by a laser light scattering method.

Abstract: The method of the present invention provides a process for manufacturing MEMS devices having more precisely defined mechanical and/or electromechanical members. The method of the present invention begins by providing a partially sacrificial substrate and a support substrate. In order to space the mechanical and/or electromechanical members of the resulting MEMS device above the support substrate, mesas are formed on the support substrate. By forming the mesas on the support substrate instead of the partially sacrificial substrate, the mechanical and/or electromechanical members can be more precisely formed from the partially sacrificial substrate since the inner surface of the partially sacrificial substrate is not etched and therefore remains planar. As such, trenches can be precisely etched through the planar inner surface of the partially sacrificial substrate to define mechanical and/or electromechanical members of the MEMS device.

Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on IC chips with Al bonding sites. The UBM of the invention comprises a copper layer applied directly to the aluminum bonding sites. Reliable bonds are obtained if the Al surface is a nascent surface. Such a surface can be provided by back sputtering an aluminum bonding site, or by a freshly sputtered aluminum layer. The copper layer is deposited on the nascent aluminum surface in e.g. a cluster tool without breaking vacuum. The UBM can be patterned using subtractive techniques.

Abstract: The invention relates to a method for bonding two wafers, in which the wafers are placed over one another in such a way that a first surface of one wafer lies over a first surface of the other wafer. Trenches are introduced into at least one of the first surfaces. The trenches run in the plane of the surfaces. The wafers lying one on top of the other are then subjected to a heat treatment in an oxidizing atmosphere.

Abstract: A method for fabricating an interconnected multiple circuit chip structure by etching a first substrate to form protrusions on its surface. Then the protrusions are preferentially etched to produce a selected shape such as a tetragonal protrusion and an integrated circuit is then fabricated on the substrate. A second substrate is preferentially etched to form recesses having a selected shape that is the complement of the selected shape of the protrusions of the first substrate and then an integrated circuit is fabricated on the second substrate. The protrusions and recesses are coated with an electrically conductive metal such as aluminum. The first and second substrates are joined and aligned together such that the protrusions mate with the recesses and the structure is annealed such that the metal coatings thereon come into contact to electrically connect the integrated circuits on the substrates. The method can also be used to electrically connect multiple chips mounted back to front.

Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.

Abstract: A preparation method for an integrated assembly of a microchannel and an element is disclosed. In the preparation method of this invention, an element is prepared between a substrate and a sacrificial layer. Two protection layers, which are resistant to etchant for said substrate and said sacrificial layer, are prepared to isolate said element from its ambient environment. Said sacrificial layer defines an area to be etched off such that a microchannel may be formed. A coating layer with etching windows is then prepared on said sacrificial layer and the assembly is etched in an etchant to etch off said sacrificial layer and an area of said substrate beneath said sacrificial layer. An integrated assembly of a closed microchannel and an element is then accomplished. In the invented method, no bonding process is necessary and the integrated assembly so prepared has a planarization surface. This invention also disclosed a microchannel-element assembly prepared under the method of this invention.

Abstract: A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element.

Abstract: A palladium contact and a gasket are formed on a first wafer. The gasket and contact are simultaneously engaged with a silicon layer of a second wafer. The wafers are then heated to a temperature that both forms a bond between the palladium contact of the first wafer with the silicon layer of the second wafer and that fuses the gasket to the second wafer. Therefore, when the temperature is decreased, the palladium-silicon bond maintains the alignment of the two wafers with respect to one another, and the gasket hardens to form seal around a periphery of the two wafers. By placing the two wafers in a vacuum environment prior to engaging the two wafers, the space encompassed by the gasket and the two wafers forms a sealed vacuum during the heating process. Therefore, the heating process not only forms a palladium-silicon bond between the two wafers, but it also forms a vacuum seal around selected components included within either of the two wafers.

Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

Abstract: A method and device for verifying whether a cavity (16) enclosing a micromachined sensing structure (14) between a pair of wafers (10, 12) is hermetically sealed by detecting the presence of moisture within the cavity (16). The method entails forming a bare, unpassivated PN junction diode (20) in a semiconductor substrate, preferably a device wafer (10) with the sensing structure (14). The device wafer (10) is then bonded to a capping wafer (12) to enclose the PN junction diode (20) and micromachine (14) within a cavity (16) defined by and between the wafers (10, 12). The reverse diode characteristics of the PN junction diode (20) are then determined by causing a reverse current to flow through the diode (20). For this purpose, either a known voltage is applied across the diode (20) and the reverse leakage current measured, or a known reverse current is forced across the diode (20) and the voltage measured.

Abstract: A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafers to form a bond between the first and second wafers, and detaching a portion of the first wafer from the second wafer. Thus, a device, such as a back-plane for a semiconductor device, formed by the method includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.

Abstract: A method of fabricating a film of active devices is provided. First damaged regions are formed, in a substrate, underneath first areas of the substrate where active devices are to be formed. Active devices are formed onto the first areas. Second damaged regions are formed, in the substrate, between the first damaged regions. The film is caused to detach from a rest of the substrate at a location where the first and second damaged regions are formed.

Abstract: A method for fabricating a wafer-pair having at least one recess in one wafer and the recess formed into a chamber with the attaching of the other wafer which has a port plugged with a deposited layer on its external surface. The deposition of the layer may be performed in a very low pressure environment, thus assuring the same kind of environment in the sealed chamber. The chamber may enclose at least one device such as a thermoelectric sensor, bolometer, emitter or other kind of device. The wafer-pair typically will have numerous chambers, with devices, respectively, and may be divided into a multiplicity of chips.

Abstract: At a room temperature, cleaned glass substrates 8a, 8b are suitably positioned and placed one upon another. A hydrofluoric acid solution or alkaline solution 10 is dropped into the bonding interface between the glass substrates 8a, 8b. The hydrofluoric acid solution or alkaline solution thus dropped spreads along the bonding interface. At a room temperature, a load is then applied to the upper glass substrate 8a and allowed to stand for a suitable period of time, thus bonding the glass substrates to each other.

Abstract: A method for the releasable bonding of at least two wafers (10, 12), for example of two silicon wafers (silicon discs), or of a silicon wafer and a glass wafer, or of a semiconductor wafer and a cover wafer, by a wafer bonding method in which the surfaces to be brought into contact with one another are at least substantially optically smooth and flat. Prior to bringing the surfaces of the wafers (10, 12) into contact, one or more drops of a liquid are applied to at least one of the surfaces, and the wafer bonding method is carried out at least substantially at room temperature, or at a somewhat higher temperature, or optionally at a somewhat lower temperature. The wafers (10, 12) which are bonded together can easily be separated from one another in that at least the liquid enclosed between the wafers (10, 12), which are bonded to one another, is exposed to a temperature lying substantially above the bonding temperature at which the liquid vaporizes. A wafer structure is also disclosed.

Abstract: This invention relates to the manufacture of a strain gauge sensor using the piezoresistive effect, comprising a structure (1) made of a monocrystalline material acting as support to at least one strain gauge (2) made of a semiconducting material with a freely chosen doping type. The strain gauge (2) is an element made along a crystallographic plane determined to improve its piezoresistivity coefficient. The structure (1) is a structure etched along a crystallographic plane determined to improve its etching. The strain gauge (2) is fixed to the structure (1) by bonding means capable of obtaining said sensor.

Abstract: A method for packaging an integrated circuit device includes forming a dielectric support layer on the surface of a substrate wherein the dielectric support layer includes an opening therein exposing at least a portion of an active region of the substrate. A protective layer is provided on the dielectric support layer opposite the substrate wherein the protective layer covers the exposed portion of the active region of the substrate thereby defining a cavity between the protective layer and the active region. More particularly, the step of forming the dielectric support layer can include forming a continuous dielectric layer on the surface of the substrate including the active region, and removing portions of the continuous dielectric layer from the active region to provide the opening of the dielectric support layer. Related structures are also discussed.

Abstract: A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite.

Abstract: The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.

Abstract: A hermetically sealed sensor device having a glass member defining a mounting surface and base surface, the glass member including one or more pin apertures extending through the glass member from the mounting surface to the base surface. A metallic pin is disposed in each of the pin apertures, each pin having a portion extending above the mounting surface. The sensor device also includes a semiconductor sensor chip including a semiconductor device and a cover hermetically bonded and sealed to a surface of the semiconductor device, the cover protecting the semiconductor device from the external environment. The is chip hermetically bonded and sealed to the mounting surface of glass member. The semiconductor device has one or more contacts disposed on the surface thereof, for making electrical contact thereto, the cover having one or more contact apertures extending therethrough which exposes a portion of the contacts.

Abstract: A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrates are joined to each other by heating them at 800.degree. C. in a hydrogen atmosphere.

Abstract: A micromachined self-packaged circuit provides at least partial shielding of a circuit element. Preferably, all the elements comprising a circuit are completely shielded between a first wafer of semi-conductor material having a recess and receiving a metallized layer therebeneath and a second wafer of semi-conductor material having a groove in a bottom face against which is received a metallized layer. The first wafer metallized face is then adhesively bonded to the second wafer on a surface opposite the metallized layer to which a circuit is affixed. The second wafer metallized face and metallized grooves cooperate with the first wafer metallized face to provide a shielded circuit cavity therebetween. Alternatively, the first or second wafer can be used alone to partially shield a circuit element.

Abstract: The specification describes a gettering technique for bonded wafers. The handle wafer is provided with a phosphorus predeposition to getter impurities from the handle wafer. The surface to be bonded of the handle wafer is then polished to prepare the wafer for bonding. During polishing the top side phosphorus layer is removed, thereby eliminating the potential for updiffusion of phosphorus from the gettering layer into the device regions of the device layer. The phosphorus gettering layer on the backside of the handle wafer is retained for additional gettering during the bonding operation and during subsequent processing of the device wafer.

Abstract: Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: A method for forming an isolating layer in a semiconductor device includes the steps of forming a first material layer on an active layer having a major axis and a minor axis, forming a second material layer in a form of sidewall at sides of the first material layer in a direction of the major axis, and conducting field oxidation using the first and second material layers as masks to form the isolating layer.

Abstract: A process is provided for protecting, containing, and/or completing fragile microelectronic and microelectromechanical (MEM) structures on a low conductivity substrate during anodic wafer bonding of a covering wafer. The wafer includes raised areas that contact the substrate at selected bonding regions to support the wafer as a covering structure over the substrate. The covering wafer includes additional raised areas, such as pillars or posts, that contact selected electric circuit lines on the substrate to form temporary shorts through the wafer. During anodic bonding of the wafer to the substrate, the temporary shorts maintain the connected circuit lines and microstructures at nearly the same electric potential to prevent unwanted arcing and electrostatic forces that could damage the fragile structures. The pillars or posts can be formed at the same time as the raised bonding areas, but on unwanted and otherwise unused portions of the covering wafer.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally. Assembly of the enclosure is compatible with known batch fabrication techniques and is carried out at pressures required for optimal device operation. In a first embodiment, an intrinsic silicon shell is sealed to the substrate via electrostatic or anodic bonding with the leads diffusing into the shell. In a second embodiment, a thin interface layer of silicon or polysilicon is deposited on the substrate prior to electrostatic bonding a glass shell thereon. In a third embodiment, tunnels are formed between a lower peripheral edge of the shell and the substrate, allowing leads to pass thereunder. The tunnels are sealed by a dielectric material applied over the enclosure.

Abstract: A piezoelectric device is manufactured by: (1) mirror finishing surfaces of a first substrate and a second substrate made of a piezoelectric element; (2) forming grooves on at least one of the two surfaces of the first and second substrates; (3) joining the mirror-finished surfaces of the first substrate and the second substrate; (4) applying heat to the joined substrates and bonding them; (5) forming an opening on the first substrate so that a part of the exposed areas of the second substrate is exposed through the opening; (6) forming piezoelectric devices by forming electrodes on at least one of the second substrate through the opening and a corresponding area to the exposed area on the rear side of the second substrate; and (7) dividing the bonded substrates into portions each having one of the piezoelectric devices. Through this manufacturing method, piezoelectric devices with high yield ratios and high reliability can be obtained.

Abstract: A motion sensor including a sensing wafer with a bulk micromachined sensing element, and a capping wafer on which is formed the conditioning circuitry for the sensor. The sensing and capping wafers are configured such that, when bonded together, the capping wafer encloses the sensing element to form a monolithic sensor. The capping wafer is further configured to expose bond pads on the sensing wafer, and to enable singulation of the two-wafer stack into individual dies. Wire bonds can be made to both wafers, such that the sensor can be packaged in essentially any way desired.

Abstract: On a silicon wafer there is formed a movable gate MOS transistor (sensing element: functional element). A bonding frame consisting of a silicon thin film is patterned around an element formation region on the surface of the silicon wafer. On a cap forming silicon wafer there is projectively provided a leg portion on the bottom surface of which a bonding layer consisting of a gold film is formed. The cap forming silicon wafer is disposed on the silicon wafer, whereupon heating with respect thereto is performed at a temperature equal to higher than a gold/silicon eutectic temperature to thereby make bondage between the bonding frame of the silicon wafer and the bonding layer of the cap forming silicon wafer. Thereafter, the both wafers are diced in chip units.

Abstract: This invention relates to the area of microelectromechanical systems in which electronic circuits and mechanical devices are integrated on the same silicon chip. The method taught herein allows the fabrication of thin film structures in excess of 150 microns in height using thin film deposition processes. Wafers may be employed as reusable molds for efficient production of such structures.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method of processing wafers for power devices in which the wafer has a desired thickness less than the thickness necessary to provide mechanical support. A silicon wafer of the desired thickness is bonded to a carrier wafer until most, if not all, of the processing steps are completed, after which the silicon wafer is separated from its carrier wafer. The carrier wafer may serve as a diffusion source, and the areas of the bonding of the silicon wafer to the carrier wafer may be selected consistent with the devices or groups of devices to be formed by the separation of the two wafers. The carrier wafer may by bonded to the device wafer over nearly the full surface area and the carrier wafer remain a part of the final device.

Abstract: A gas flow type sensor with heat-wire bridge having an excellent performance which is attained by optimizing a sputtering process and a heat treatment process for forming a three-layer film (SiN-Pt-SiN) on a semiconductor substrate and improving interfacial adhesion of the three layers and, at the same time, effectively reducing any interfacial stress produced therein. The process comprises a film forming process for sequentially depositing by sputtering SiN, Pt and SiN in three layers on a semiconductor substrate and a heat treatment process for heat treatment of the coated films at a temperature up to 600.degree. C.

Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.

Abstract: A method of fabricating a pagewidth array of buttable printheads reduces end channel damage. The wafer containing a plurality of arrays of channels is provided with V-grooves. A V-groove is positioned between each array. When the wafer is secured to a wafer containing heater plates, wafers are diced along the V-shaped grooves to reduce damage to the end channels of the array to improve print quality.