Abstract: A method of separating a lamination body with high yield without damaging the lamination body is provided. Further, a method of manufacturing a lightweight, flexible semiconductor device, which is thin in total is provided. The method of manufacturing the semiconductor device includes: a first step of laminating a metal layer, an oxide layer, a layer containing no hydrogen element, and a lamination body on a first substrate; a second step of forming a photocatalytic layer on a transparent substrate; and a third step of attaching the photocatalytic layer to the surface of the lamination body by using a first adhesive material after the first and second steps, separating the metal layer from the oxide layer, and irradiating light from a side of the transparent substrate so that an interface between the photocatalytic layer and the first adhesive material is separated to remove the first adhesive material.

Abstract: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Abstract: Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned region of the wafer. One or more reinforcement structures may be defined on the wafer. Semiconductor wafers include one or more reinforcement structures that extend laterally along the wafer and project from at least one surface of the wafer. The wafers further include a plurality of at least partially formed semiconductor dice laterally within at least one region having a thickness that is less than a thickness of the reinforcement structures. The wafers may include a plurality of at least partially formed semiconductor dice laterally within each of a plurality of thin regions defined between a plurality of reinforcement structures. The thin regions may have an average thickness less than an average thickness of the reinforcement structures.

Abstract: A system and method bond wafers using localized induction heating. One or more induction micro-heaters are formed with a first substrate to be bonded. A second substrate is positioned in intimate contact with the induction micro-heaters. An alternating magnetic field is generated to induce a current in the induction micro-heaters, to form one or more bonds between the first substrate and the second substrate.

Abstract: The invention relates to a process for and an arrangement of the connection of processed semiconductor wafers (1, 2) wherein, in addition to the firm connection, there is an electric connection (5) between the semiconductor wafers and/or the electronic structures (3) supporting them. For this purpose, low-melting structured intermediate glass layers (6; 6a) are used as insulating layers and as an electric connection in the form of electrically conductive solder (5) on a glass basis in order to achieve a firm connection.

Abstract: Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.

Abstract: The present invention relates to the manufacture of a semiconductor switch for use in a variety of communication systems, and particularly to the manufacture of a RF micro-machined switch of pull-up type, wherein an electrostatic electrode is used so as to cause the contact pad involved in the operation of the switch to be pulled upward from below. The RF micro-machined switch of pull-up type according to the invention has a high isolation characteristic for shorting and opening the circuit and needs a low driving voltage, so that miniaturization of communication system is possible because a circuit for booting driving voltage is not required within the system. Further, the characteristic of switch is little changed after a long use because the metal composing the contact pad experiences little deformation during operation, whereby the semi-permanent use of switch is possible.

Abstract: Apparatus for housing a micromechanical structure, and a method for producing the housing. The apparatus has a substrate having a main side on which the micromechanical structure is formed, a photo-resist material structure surrounding the micromechanical structure to form a cavity together with the substrate between the substrate and the photo-resist material structure, wherein the cavity separates the micromechanical structure and the photo-resist material structure and has an opening, and a closure for closing the opening to close the cavity.

Abstract: A circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns provides a high-density mounting and interconnect structure for semiconductor packages that is manufacturable in volume. A dielectric film is laminated on one or both sides with a foil layer with a circuit pattern disposed on a surface of the foil. The circuit-on-foil layer can be made by laser-ablating a plating resist material and then plating metal atop a foil, or by laser-exposing a photo-sensitive plating resist material and then plating the circuit pattern atop the foil. After lamination, the metal foil is removed by etching or machining to leave only the dielectric and embedded conductors. Vias can be formed between layers of embedded conductors by laser-drilling holes either though the entire substrate or from one side through to at least the bottom of one of the embedded circuit layers, and then filling the hole with metal.

Abstract: A method is disclosed for making a wafer-level package for a plurality of MEMS devices. The method involves preparing a MEMS wafer and a lid wafer, each having respective bonding structures. The lid and MEMS wafers are then bonded together through the bonding structures. The wafers are substantially free of alkali metals and/or chlorine. IN a preferred embodiment, each wafer has a seed layer, a structural underlayer and an anti-oxidation layer. A solder layer, normally formed on the lid wafer, bonds the two wafers together.

Abstract: A MEMS article is made by forming a MEMS device on a first substrate, providing a second substrate, depositing a layer of etchable dielectric material, forming at least one lateral post-bond release-etch port by a damascene process using a sacrificial material, and bonding the two substrates together.

Abstract: A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum package that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Abstract: A method for bonding substrate structures. The method includes providing a transparent substrate structure, the transparent substrate structure comprising a face region and an incident light region, providing a spacer structure, the spacer structure comprising a selected thickness of material, the spacer structure having a spacer face region and a spacer device region, and providing a device substrate structure, the device substrate having a device face region and a device backside region. The method further includes applying a first glue material to the spacer face region and bonding the spacer face region to the face region of the transparent substrate structure. The method also includes applying a second glue material to the spacer device region and bonding the spacer device region to the device face region.

Abstract: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised surface region in relation to the surface planar region of reduced thickness, structuring the raised surface region of the semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside the raised surface regions, joining the structured surface of the semiconductor planar substrate with the glasslike planar substrate in such a manner that the glasslike planar substrate at least partially covers the surface planar region of reduced thickness, tempering the joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, the glasslike planar substrate covering the surface reg

Abstract: A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate semiconductor dice may be formed upon a surface thereof. At least one region of the semiconductor wafer may be thinned and at least one reinforcement structure for reinforcing the semiconductor wafer may be formed. A semiconductor wafer is disclosed comprising at least one thinned region and at least one reinforcement structure having a first portion and a second portion extending from respective thinned surfaces of the at least one thinned region. A method of designing a semiconductor wafer is disclosed wherein at least one region thereof is selected for thinning. Remaining unthinned regions of the semiconductor wafer may be selected for forming at least one reinforcement structure. At least one semiconductor die location may be selected within the at least one thinned region.

Abstract: A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; fabricating a patterned spacing layer on the flexible substrate; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate.

Abstract: A technique for manufacturing a micro-electro mechanical structure includes a number of steps. Initially, a cavity is formed into a first side of a handling wafer, with a sidewall of the cavity forming a first angle greater than about 54.7 degrees with respect to a first side of the handling wafer at an opening of the cavity. Then, a bulk etch is performed on the first side of the handling wafer to modify the sidewall of the cavity to a second angle greater than about 90 degrees, with respect to the first side of the handling wafer at the opening of the cavity. Next, a second side of a second wafer is bonded to the first side of the handling wafer.

Abstract: This invention relates to a method for making a thin layer starting from a wafer comprising a front face with a given relief, and a back face, comprising steps consisting of: a) obtaining a support handle with a face acting as a bonding face; b) preparing the front face of the wafer, this preparation including incomplete planarisation of the front face of the wafer, to obtain a bonding energy E0 between a first value corresponding to the minimum bonding energy compatible with the later thinning step, and a second value corresponding to the maximum bonding energy compatible with the subsequent desolidarisation operation, the bonding energy E0 being such that E0=?.

Abstract: A first wafer is provided, and a photosensitive masking-and-bonding pattern is formed on the surface of the first wafer. Then, an etching process using the photosensitive masking-and-bonding pattern as a hard mask is performed to form a wafer pattern on the surface of the first wafer. Finally, the first wafer is bonded to a second wafer with the photosensitive masking-and-bonding pattern.

Abstract: A method of bonding two components by depositing an amorphous and non-hydrogenated intermediate layer (2) on one of the components (1,4) and arranging the components (1,4) in spaced relationship with the intermediate layer (2) therebetween. The method further comprises heating one or both of the components (1,4) before bringing the components (1,4) into contact. Finally, a voltage is applied to the components (1,4) to create a permanent bond between the two components.

Abstract: A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon layer; depositing a dielectric layer on the wafer to cover a gate module of the IC device; smoothing the dielectric; implanting ions to form a defect layer; cutting the wafer into individual silicon dies; preparing a glass panel and the silicon dies for bonding; bonding the silicon dies onto the glass panel to form a bonded structure; annealing the bonded structure; splitting the bonded structure along the defect layer; removing the remaining silicon layer from the silicon substrate and relaxed SiGe layer on the silicon die on the glass panel; and completing the glass panel circuitry.

Abstract: A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.

Abstract: A method for forming device packages includes forming a perimeter comprising a reactive foil and a bonding material interposed between a first wafer and a second wafer, pressing the first and the second wafers against the reactive foil and the bonding material, initiating the reactive foil, wherein the reactive foil heating the bonding material to create a bond between the first and the second wafers, and singulating the first and the second wafers into the device packages.

Abstract: An active type tunable wavelength optical filter having a Fabry-Perot structure is disclosed. A tunable wavelength optical filter which comprises a lower mirror in which silicon films and oxide films are sequentially laminated in a multi-layer and the silicon film is laminated on the highest portion; an upper mirror in which silicon films and oxide films are sequentially laminated in a multi-layer and the silicon film is laminated on the highest portion and which is spaced away from the lower mirror by a predetermined distance; a connecting means for connecting and supporting the lower mirror and the upper mirror to a semiconductor substrate; and electrode pads for controlling the gap between the lower mirror and the upper mirror by an electrostatic force and the method of manufacturing the same are provided.

Abstract: A method for producing an electronic component is provided. The method includes providing at least one die on a wafer, the at least one die having at least one sensor-technologically active and/or emitting device on at least a first side; producing at least one patterned support having at least one structure which is functional for the at least one sensor-technologically active and/or emitting device; joining the wafer with the at least one patterned support so that the first side faces the at least one patterned support; and separating the at least one die from the wafer.

Abstract: The electronic device (100) comprises an electrical element (30), for instance a MEMS capacitor or a BAW filter in a cavity (37) that is protected from the environment by a cover (38). The cover (38) is a patterned layer which is mechanically embedded in isolating material (7) present beside the cavity (37) and may further include contact pads (41). The device (100) may be suitably manufactured from an accurately folded foil including a patterned layer and a sacrifice layer. After applying the foil to the cavity (37) the isolating material (7) is provided and the sacrifice layer is removed. The patterned layer, or part thereof, stays behind and forms the cover (38).

Abstract: A micromechanical component having a substrate beneath at least one structured layer, in the structured layer at least one functional structure being formed, a cap which covers the functional structure, between the cap and the functional structure at least one cavity being formed, and a connecting layer which connects the cap to structured layer, as well as a method for producing the micromechanical component. To obtain a compact and robust component, the connecting layer is formed from an anodically bondable glass, i.e. a bond glass, which has a thickness in the range of 300 nm to 100 ?m, which may in particular be in the range of 300 nm to 50 ?m.

Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.

Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.

Abstract: A method of processing a wafer, and particularly a cap wafer configured for mating with a device wafer in the production of a die package. Masking layers are deposited on oxide layers present on opposite surfaces of the wafer, after which the masking layers are etched to expose regions of the underlying oxide layers. Thereafter, an oxide mask is formed on the exposed regions of the oxide layers, but is prevented from forming on other regions of the oxide layers masked by the masking layers. The masking layers are then removed and the underlying regions of the oxide layers and the wafer are etched to simultaneously produce through-holes and recesses in the wafer. The oxide mask is then removed to allow mating of the cap wafer with a device wafer.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

Abstract: A vacuum or hermetic packaged micromachined or MEMS device and methods for manufacturing the device so that the device has at least one substantially vertical feedthrough are provided. In a first embodiment, the method includes: providing a MEMS device fabricated on a first side of a substrate and located within a vacuum or hermetic cavity; forming at least one hole completely through the substrate between first and second sides of the substrate after the step of providing; and forming a path of electrically conductive material connecting the MEMS device and the second side of the substrate through the at least one hole to form the at least one substantially vertical feedthrough.

Abstract: A transferring method including providing a substrate, forming a transferred layer over the substrate, joining a transfer member to the transferred layer, and removing the transferred layer from the substrate. The transferring method further includes transferring the transferred layer to the transfer member and reusing the substrate for another transfer. The transferring method may also include providing a substrate, forming a separation layer over the substrate, forming a transferred layer over the separation layer, and partly cleaving the separation layer such that a part of the transferred layer is transferred to a transfer member in a given pattern. The transferring method may also include joining a transfer member to the transferred layer, removing the transferred layer from the substrate and transferring the transferred layer to the transfer member, these of which constitute a transfer process, the transfer process being repeatedly performed.

Abstract: A liquid drop discharge head includes a chip (21) that is formed by separation of a silicon wafer (20). The silicon wafer (20) has a first direction and a second direction which are mutually intersected. The chip (21) is separated from the silicon wafer (20) by etching the wafer along a separation line (22) parallel to the first direction of the wafer and by dicing the wafer (20) along a separation line (23) parallel to the second direction of the wafer.

Abstract: A method of separating a lamination body with high yield without damaging the lamination body is provided. Further, a method of manufacturing a lightweight, flexible semiconductor device, which is thin in total is provided. The method of manufacturing the semiconductor device includes: a first step of laminating a metal layer, an oxide layer, a layer containing no hydrogen element, and a lamination body on a first substrate; a second step of forming a photocatalytic layer on a transparent substrate; and a third step of attaching the photocatalytic layer to the surface of the lamination body by using a first adhesive material after the first and second steps, separating the metal layer from the oxide layer, and irradiating light from a side of the transparent substrate so that an interface between the photocatalytic layer and the first adhesive material is separated to remove the first adhesive material.

Abstract: A system for in-situ plasma treatment. The system has a processing chamber, e.g., plasma chamber. The system has a first susceptor coupled within the chamber and a second susceptor facing the first susceptor and being within the chamber. The system has one or more power sources. Preferably, a first power source is characterized by a first frequency. The first power source is coupled to the first susceptor and the second susceptor. A second power source is characterized by a second frequency. The second power source is coupled to the first susceptor and the second susceptor. A switching device is coupled to the first power source and is coupled the second power source. The switching device is configured to selectively apply the first frequency to the first susceptor while the second frequency is applied to the second susceptor and is alternatively configured to selectively apply the first frequency to the second susceptor while the second frequency is applied to the first susceptor.

Abstract: The invention relates to a method for depositing thick III-V semiconductor layers on a non-III-V substrate, particularly a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor. The aim of the invention is to carry out the crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the occurrence of unfavorable lattice distortions. To this end, the invention provides that a thin intermediate layer is deposited at a reduced growth temperature between two III-V layers.

Abstract: Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points.

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: A smart card is laminated from at least two layers of paper or film as a mounting material. A first of the layers is fitted with a semiconductor chip and a second layer has connecting contacts as well as conductor tracks or external connecting surfaces. The contacts of the semiconductor chips are electrically conductively connected to the connecting contacts on the second layer. No chip modules are required to produce the smart cards. The mounting materials provided with ICs and contacts can be laminated in an endless roll format, in the same way as for paper production.

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching.

Abstract: A method for bonding a semiconductor die to a substrate is described. The method comprises arranging a semiconductor die, an interconnect, and a substrate in a suitable configuration and using induction heating to form the bond.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

Abstract: The invention relates to a film or a layer made of semi-conducting material with low defect density in the thin layer, and a SOI-disk with a thin silicon layer exhibiting low surface roughness, defect density and thickness variations. The invention also relates to a method for producing a film or a layer made of semi-conductive material. Said method comprises the following steps: a) producing structures from a semi-conductive material with periodically repeated recesses which have a given geometrical structure, b) thermally treating the surface structured material until a layer with periodically repeated hollow spaces is formed under a closed layer on the surface of the material, c) separating the closed layer on the surface along the layer of hollow spaces from the remainder of the semi-conductive material.

Abstract: A method of isolating semiconductor devices by wet etching of a semiconductor laminate structure formed on a substrate includes providing an etching stop layer having at least two layers between the substrate and the semiconductor laminate structure. The semiconductor laminate structure is etched to isolate the semiconductor devices, the substrate is then etched away, followed by sequentially etching away of the etching stop layer.

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching.

Abstract: A porous structure with high uniformity is provided even when evaluated at a high resolution (high evaluation standard) of several or several ten nm or less. By applying this porous structure to the manufacture of an SOI substrate, an SOI substrate which has an SOI layer with a small number of defects is provided. In a region at a depth of 5 to 10 nm from the surface of a porous Si layer, values of parameters such as porosity and the like which represent a porous structure are uniformed. The manufacture of an SOI substrate using this porous Si layer reduces recessed defects in an SOI layer.

Abstract: A method for fabricating a wafer-pair having at least one recess in one wafer and the recess formed into a chamber with the attaching of the other wafer which has a port plugged with a deposited layer on its external surface. The deposition of the layer may be performed in a very low pressure environment, thus assuring the same kind of environment in the sealed chamber. The chamber may enclose at least one device such as a thermoelectric sensor, bolometer, emitter or other kind of device. The wafer-pair typically will have numerous chambers, with devices, respectively, and may be divided into a multiplicity of chips.