Abstract: This invention comprises a process for fabricating a MEMS microstructure in a sealed cavity wherein the etchant entry holes are created as a by-product of the fabrication process without an additional step to etch holes in the cap layer. The process involves extending the layers of sacrificial material past the horizontal boundaries of the cap layer. The cap layer is supported by pillars formed by a deposition in holes etched through the sacrificial layers, and the etchant entry holes are formed when the excess sacrificial material is etched away, leaving voids between the pillars supporting the cap.

Abstract: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.

Abstract: Methods for making thin silicon layers suspended over recesses in glass wafers. One method includes providing a thin silicon-on-insulator (SOI) wafer, and a glass wafer. The SOI wafer can include a silicon oxide layer disposed between a first undoped or substantially undoped silicon layer and a second silicon layer. Recesses can be formed in the glass wafer surface and electrodes may be formed on the glass wafer surface. The first silicon layer of the SOI wafer is then bonded to the glass wafer surface having the recesses, and the second silicon layer is subsequently removed using the silicon oxide layer as an etch stop. Next, the silicon oxide layer is removed. The first silicon layer can then be etched to form the desired structure. In another illustrative embodiment, the first silicon layer has a patterned metal layer thereon. The SOI wafer is bonded to the glass wafer, with the patterned metal layer positioned adjacent the recesses in the glass wafer.

Abstract: Embodiments provide a method, article of manufacture, and apparatus for providing a component package for components such as integrated circuits. In one embodiment, a carrier includes a plurality of sidewalls formed thereon to form a component package assembly. In one aspect, a cover is bonded to the component package assembly to form a plurality of separable individual component packages having a cavity therein, where each individual component package encapsulates at least one component disposed on the carrier. The component package assembly is then separated into individually packaged devices.

Abstract: A method for manufacturing a bonded wafer, in which when a bonded wafer is manufactured using an ion implantation separation method, impurities attached in the ion implantation step can be removed effectively, and less failure called a void is generated on the bonding surface. Impurities such as particles or organic substances attached in ion implantation step (c) are removed using a physical removal method (d). The surface of a first wafer (1) subjected to impurities removal is closely contacted onto the surface of a second wafer (2) for heat treatment (e). The first wafer is separated in a thin-film form at a micro bubble layer (f).

Abstract: A method for making an array of thin single-crystal substrates on a handle substrate comprising the steps: attaching a plurality of single-crystal substrates to a face of a support wafer; polishing said plurality of attached single-crystal substrates so that said single-crystal substrates surfaces are coplanar on said support surface and to a selected surface roughness; implanting a hydrogen to a selected depth into said attached single-crystal substrates; bonding said polished and hydrogen implanted attached single-crystal substrates to a first handle substrate; and splitting said polished and hydrogen implanted attached single-crystal substrates at said selected depth thereby forming an array of thin single-crystal substrates on said first handle substrate and a support wafer having a remaining portion of said attached single-crystal substrates.

Abstract: A method of manufacturing a diaphragm utilising a precision grinding technique after etching a cavity in a wafer. A technique for preventing distortion of the diaphragm based on use of a sacrificial layer of porous silicon is disclosed.

Abstract: The present invention relates to a method of connecting two semiconductor components comprising the steps of providing in a first main surface of a first semiconductor substrate first component structures including first contact areas, forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to the second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material on the first main surface of said first semiconductor substrate, forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes, providing on a second semiconductor substrate second component structures including second contac

Abstract: Micromachining, etching and bonding techniques are employed to fabricate hermetically sealed gas-filled chambers from silicon and/or glass wafers. The hermetically sealed gas-filled chambers have precise dimensions and are filled with a preselected concentration of gas, thus rendering exceptional performance for use as an optical gas filter. The first step involves etching one or more cavities or holes in one or more glass or silicon wafers. These wafers eventually become part of a chip assembly having one or more hermetically sealed gas-filled chambers after appropriate bonding procedures. Interfaces between aligned silicon wafers are bonded using fusion bonding techniques whereas interfaces between silicon and glass wafers are bonded using anodic bonding techniques.

Abstract: A method for fabricating semiconductor wafers as multiple-depth structure (i.e., having portions of varying height). The method includes patterning a first substrate and bonding a second substrate to the first. This process creates a subsurface patterned layer. Portions of the second substrate may then be etched, exposing the subsurface patterned layer for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. Or, for example, exposed portions of the first substrate may have material added to them to create multiple-depth structures. This method of fabrication provides substantial advantages over previous methods.

Abstract: A selenidation reaction for bonding one or more active substrates to a base substrate is disclosed. A bonded-substrate is fabricated by forming a first multi-stacked layer of selenium and indium on a bonding surface of an active substrate and forming a second multi-stacked layer of selenium and indium on a mounting surface of a base substrate. The first and second multi-stacked layers are placed into contact with each other with substantially no pressure. Then the active substrate and the base substrate are bonded to each other by annealing them in an inert ambient to form an indium-selenium compound bond layer that adhesively bonds the substrates to each other. The annealing can occur at a lower temperature than prior wafer-bonding processes and the first and second multi-stacked layers can be deposited over a wide range of relatively low temperatures including room temperature.

Abstract: A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the trench to remove a first material (38) from the trench. A second material (44) is deposited to plug the opening to seal an air pocket (40) in the trench. The low permittivity region features air pockets with a high volume because the small size of the opening allows the second material to plug the trench without accumulating significantly in the trench.

Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.

Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.

Abstract: Mixtures for attaching a semiconductor chip to a substrate. The semiconductor chip has an array of joining material bumps, such as C4 solder balls. The substrate has an array of conductive pads corresponding to the array of joining material bumps. In a first embodiment the fixture has a body having a first cavity containing the semiconductor chip and a second cavity for containing the substrate. The substrate is placed over the semiconductor chip with the conductive pads opposing and in contact with the joining material bumps, such that during reflow of the joining material bumps, the weight of the substrate acts against the joining material bumps and aids in the attachment of the semiconductor chip to the substrate to form electrical connections therebetween.

Abstract: A microactuator has a first substrate, a second substrate, a first comb electrode having a plurality of first comb elements formed on an inner surface of the first substrate, a second comb electrode having a plurality of second comb elements formed on an inner surface of the second substrate, and a connecting film formed by partially removing an interlayer formed on the inner face of any one of the first substrate and the second substrate. The first substrate and the second substrate face each other with a distance and are movable with respect to each other. The first comb elements and the second comb elements are alternately disposed. Any one of the first electrode and the second electrode is bonded to the connecting film. This microactuator is preferably used in magnetic head units and magnetic recording apparatuses.

Abstract: Semiconductor circuit devices (dies) are incorporated into moisture-impenetrable electronic packages by forming enclosures around the die in three separate parts—base, sidewalls, and lid. The die is first soldered or otherwise bonded to the base, followed by attachment of the sidewalls to the base, and finally the lid to the sidewalls. For procedures involving a heat-conductive base and a high soldering temperature, the die can be secured to the base at the high soldering temperature, followed by application of the sidewalls to the base at a significantly lower temperature, avoiding potential high-temperature damage to the sidewalls. Plastic sidewalls which would otherwise deteriorate or become distorted upon exposure to the high soldering temperature can thus be used.

Abstract: The present invention provides a method of fabricating a wafer level package. A semiconductor wafer having a plurality of chips thereon is first provided. A substrate having an area smaller than that of the chip is installed on each chip. A plurality of wires are used to connect bonding pads of the chip to the substrate. An encapsulation is then used to sheathe all the wires. Finally, a plurality of solder balls are arranged on the surface of the substrate between the wires. A wafer level package is thus formed. A plurality of electronic package devices can be obtained after slicing the wafer level package. In the present invention, original manufacturing equipments still can be used. The packaged electronic package device has a size commensurate to the chip size so that it is compact and occupies less area. Moreover, it has good electronic properties.

Abstract: A surface micro-machined sensor uses a pedestal in a cavity to support a flexible structure and reduce the span of the flexible structure. The reduced span per sense area allows larger sensor areas without permitting forces to permanently deform the flexible structure or cause the structure to touch an opposite wall of the cavity. The flexible structure bonded to the pedestal and an elevated region surrounding the pedestal defines a cavity between the flexible membrane and a lower plane region. Active regions can be formed in the lower plane region for capacitors or transistors. A pedestal can be of various shapes including a circular, ovoid, rectangular or polygonal shape. The lower plane region can be of various shapes including a ring or donut shape, ovoid, rectangular or polygonal shape with an inner dimension corresponding to the outer dimension of the pedestal. The elevated region can be of various shapes with an inner dimension corresponding to the outer dimension of the lower plane region.

Abstract: In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.

Abstract: This invention is to support a plate member such as a bonded substrate stack in a horizontal state without coming into contact with one surface of the member and also to efficiently progress separation. Separation is executed while arranging a bonded substrate stack (50) generated by bonding a seed substrate (10) to a handle substrate (20) such that the seed substrate (10) remains on the lower side. At the first stage, the peripheral portion is separated while causing a first substrate support section (101) to chuck and support the central portion of the lower surface of the bonded substrate stack (50). Then, at the second stage, the central portion is separated while causing a second substrate support section (102) to support the lower peripheral portion and side of the bonded substrate stack (50).

Abstract: In the previously known methods, the buried layers, such as suicide for example, are produced on SOI wafers by thinning the wafer bonded onto the SOI wafer to the desired thickness, and then isolating the layers grown on the SOI wafer by means of a trench process.

Abstract: A semiconductor device is fabricated first by thermocompression-bonding a silicon oxide film onto a plurality of conductive films under vacuum using a film having the silicon oxide film formed thereon and then by separating the base film from the silicon oxide film. During the separation, the base film, being composed of a fluorine-containing resin, has smaller surface energy than a silicon oxide film and thus is easy to separate, leaving the silicon oxide film on the conductive films. As a result, the silicon oxide film is adhered on the conductive films so as to cover the conductive films, and an air gap is hence provided between the conductive films. Thus, a highly reliable semiconductor device capable of high-speed-operation is provided by controlling parasitic capacitances between interconnections arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.

Abstract: A method of inverting a plurality of plate-like materials. One form of the method may include supporting the plurality of plate-like materials in an orientation such that the plate-like materials are substantially parallel to each other in a first orientation. The method may also include engaging portions of each plate-like material to retain the plate-like materials in the substantially parallel orientation to each other, and simultaneously inverting the plate-like material to a second orientation.

Abstract: A method for forming bonds between similar and dissimilar material surfaces, particularly the surfaces of silicon wafers having various devices disposed thereon, wherein such bonds can be formed at room temperature and do not require the application of high pressures or voltages. The bonding material is polydimethylsiloxane, which is transparent and bio-compatible.

Abstract: The use of robust substrates on the surface micro-machined structures combines (1) the use of micro-machining technology; (2) the use of electronic packaging technologies; and (3) the use of conventional machining techniques to create a new class of micro-machined structures. A particular robust substrate-based micro-machine structure is a capacitive pressure sensor that includes a pressure sensitive diaphragm and an electrode.

Abstract: A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

Abstract: The invention relates to a method of producing calibration structures in semiconductor substrates in the manufacture of components, specifically micro-mechanical systems with integrated semiconductor electronic systems. In the method a first layer (3) is structured on a first substrate (4, 5, 6) to produce first areas (2) which are required for the function of the components. Moreover, second areas (1) are produced in the first layer (3), which represent the calibration structures. The second areas (1) present a refractive index different from the refractive index of adjoining areas. Subsequently, the first substrate (4, 5, 6) is joined with a second substrate (12) such that the first layer (3) will be enclosed between the two substrates. Then either the first or the second substrate is thinned down to a residual thickness. The substrate layer with this residual thickness constitutes, for instance, the membrane in a pressure sensor.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A method for fabricating of macroscopic two or three dimensionally ordered arrays of single wall nanotubes (SWNTs) comprising the following steps: chemically treating purified SWNTs using the sol gel process to add chemically reactive groups to either the tube ends or tube bodies in order to functionalize the SWNTs; suspending the functionalized SWNTs in an appropriate liquid medium such that a colloid is produced; treating the colloid with a chemical or heat to promote coupling of the individual functionalized SWNTs to each other; and heating the coupled SWNTs to evaporate any excess liquid so as to provide a final product comprising an array of covalently bound functionalized SWNTs.

Abstract: The present invention relates to a method of producing very thin substrate layers, particularly thin semiconductor areas, which may comprise integrated circuits. In the method two substrates (1, 2) are bonded by their faces via one or several intermediate connecting layers (3, 4). At least one of the bonding layers or the face of one of the substrates is structured before in such a way that channel-shaped recesses (5) are formed which permit a lateral penetration of an etching agent. The resulting wafer stack is thinned from one side down to the desired thickness of the layer. Finally, this thin layer is detached from the remaining substrate by introduction of the etching agent into the channel-shaped recesses. This detaching process is a low-price wet chemical process that does not expose the chip and the added value integrated thereon to any risk.

Abstract: A platform is provided for the manufacture of microwave, multilayer integrated circuits and microwave, multifunction modules. The manufacturing process involves bonding fluoropolymer composite substrates into a multilayer structure using fusion bonding. The bonded multilayers, with embedded semiconductor devices, etched resistors and circuit patterns, and plated via holes form a self-contained surface mount module. Film bonding, or fusion bonding if possible, may be used to cover embedded semiconductor devices, including embedded active semiconductor devices, with one or more layers.

Abstract: A small size electronic part comprises a silicon substrate having a functional element and a signal output portion to output a signal from the functional element to outside the electronic part; a glass substrate provided on the silicon substrate such that the signal output portion of the silicon substrate is in contact with the glass substrate; a communicating hole provided in the glass substrate and at least a portion of the signal output portion of the silicon substrate so as to pass through the glass substrate and cut into at least a part of the signal output portion; and a conductive film provided on an inner wall surface of the communicating hole and extending on a surface of the glass substrate.

Abstract: A new design is provided for the die-paddle that is used as part of a package for packaging semiconductor devices. The new design of the invention creates a space between the ground ring of the die-paddle and the surface over which the ground paddle is mounted. The new design further comprises an S-shaped segment between the ground ring and the center of the die-paddle, the S-shaped segment provides stress relieve between the ground ring and the center of the die-paddle.

Abstract: There is provided a method of fabricating an SOI wafer having high quality by hydrogen ion delamination method wherein a damage layer remaining on the surface of the SOI layer after delamination and surface roughness are removed maintaining thickness uniformity of the SOI layer. According to the present invention, there are provided a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after bonding heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after delaminating heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; and an SOI wafer fabricated by the methods.

Abstract: A method for transferring a thin film device on a substrate onto a transfer member, includes a step for forming a separation layer on the substrate, a step for forming a transferred layer including the thin film device on the separation layer, a step for adhering the transferred layer including the thin film device to the transfer member with an adhesive layer therebetween, a step for irradiating the separation layer with light so as to form internal and/or interfacial exfoliation of the separation layer, and a step for detaching the substrate from the separation layer.

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.

Abstract: In a photoelectric conversion apparatus obtained by arranging and fixing a plurality of semiconductor element substrates onto a base with an adhesive, the levels of the upper surfaces of the substrates are adjusted with a desired thickness of the adhesive so as to set the upper surfaces within the same plane while the distance from the upper surface of the base to the semiconductor element surface of each substrate is kept to a design value, thereby realizing a photoelectric conversion apparatus constituted by a plurality of substrates arranged two-dimensionally, which eliminates level gaps between the substrates, and hence is free from problems such as a decrease in resolution, a deterioration in sensitivity, and peeling of a phosphor and the like.

Abstract: A linear array of diode laser emitters is manufactured with sufficient thermal and electronic isolation among the emitters to permit separate addressability. The emitter bar has first and second opposed surfaces and a third surface through which the emitters direct output. A first surface of the emitter bar is affixed to a “standoff” element that has conductive surfaces connecting each emitter to a power source; these connections are maintained after a series of spaces is formed between the emitters of the emitter bar. The second surface of the emitter bar is affixed to a heat sink to form a finished assembly.

Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: In a sensor having a membrane structure, a sensor chip (silicon substrate) is provided with a through hole that is open on both upper and lower surfaces of the silicon substrate. A sensor element having a membrane structure is formed on the upper surface of the silicon substrate to close the through hole on the upper surface. The lower surface of the silicon substrate is bonded to a stem through adhesive to define a communication passage through which an inside and an outside of the through hole communicate with each other. Accordingly, the sensor can exhibit high reliability.

Abstract: A power semiconductor device package includes at least one power semiconductor device mounted onto at least one electrically and thermally conductive spacer having an upper end surface bonded to a back surface of the device; a substrate of hardened substrate molding material surrounding the semiconductor device and the spacer except for an active major surface of the device and an lower end surface of the spacer, a dielectric film overlying the device active major surface and a top side of the substrate, the dielectric layer having a plurality of holes aligned with predetermined ones of the contact pads; a top side patterned metal layer on the dielectric film including portions extending into the holes electrically and thermally connected to contact pads of the device; and a backside metal layer on a substrate bottom side electrically and thermally connected to the spacer lower end surface.

Abstract: A method of fabricating a microstructure having an inside cavity. The method includes depositing a first layer or a first stack of layers in a substantially closed geometric configuration on a first substrate. Then, performing an indent on the first layer or on the top layer of said first stack of layers. Then, depositing a second layer or a second stack of layers substantially with said substantially closed geometric configuration on a second substrate. Then, aligning and bonding said first substrate on said second substrate such that a microstructure having a cavity is formed according to said closed geometry configuration.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A method is provided for fabricating a MEMS structure from a silicon-on insulator (SOI) wafer that has been bonded to a support substrate, such as a glass substrate, in order to form silicon components that can be both precisely and repeatedly formed. The SOI wafer includes a handle wafer, an insulating layer disposed on the handle wafer and a silicon layer disposed on the insulating layer. At least one trench is etched through the silicon layer by reactive ion etching. By utilizing the reactive ion etching, the trenches can be precisely defined, such as to within a tolerance of 0.1 to 0.2 microns of a predetermined width. After bonding the support substrate to the silicon layer, the handle wafer is removed, such as by reactive ion etching. Thereafter, the insulating layer is selectively removed, again typically by reactive ion etching, to form the resulting MEMS structure that has a very precise and repeatable size and shape, such as to within a fraction of a micron.

Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. Each of the bond pads of both of the semiconductor devices are disposed adjacent a single, mutual edge of the back-to-back semiconductor device module. The back-to-back semiconductor device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. A process for securing the back-to-back semiconductor device module directly to the carrier substrate may employ a solder reflow technique. Alternatively, a module-securing device may be employed to secure the back-to-back semiconductor device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate.

Abstract: Phase Change Material (“PCM”) are used to reduce the range of temperature excursions in a semiconductor die attached to an interconnect substrate in the flip chip technology. In one embodiment a PCM underfill, which comprises PCM microspheres interspersed within a polymer, is dispensed in the interface area between the semiconductor die and the interconnect substrate. Reduction of the range of temperature excursions in the semiconductor die is achieved since the PCM underfill acts as a cushion to dampen the range of temperature excursions of the semiconductor die. During dissipation of power pulses in the semiconductor die, the PCM underfill absorbs energy from the semiconductor die by changing phase from solid to liquid without a concomitant rise in the temperature of the PCM underfill. Thus, the energy released when power pulses are being dissipated in the semiconductor die does not result in a rise in the temperature of the PCM underfill.

Abstract: A method of preparing small wafers for compatibility with conventional large wafer fabrication equipment comprising the following steps: indenting a face of a large wafer to form an array of depressions thereon, each depression sized to matingly accept a lower portion of a small wafer; applying a bonding medium to an exterior side of the depressions on the indented face of the large wafer; matingly fitting the small wafers into the depressions so that the small wafers are positioned in an array on the large wafer; and, removing the top portion of the small wafers standing out of the depressions by chemical mechanical polishing so that the remaining portions of the small wafers then have a uniform thickness generally equal to the depth of the indentations in the large wafer. A preferred aspect of this invention provides for a method as above wherein the small wafer is SiC and the large wafer is made from an amorphous substance which comprises SiC or aluminum nitride.