Subsequent Separation Into Plural Bodies (e.g., Delaminating, Dicing, Etc.) Patents (Class 438/458)
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Publication number: 20130134480Abstract: Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.Type: ApplicationFiled: January 9, 2013Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
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Publication number: 20130137241Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.Type: ApplicationFiled: December 28, 2012Publication date: May 30, 2013Applicant: MEMC Electronic Materials, Inc.Inventor: MEMC Electronic Materials, Inc.
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Patent number: 8450185Abstract: A semiconductor structure is bonded directly to a diamond substrate by Van der Waal forces. The diamond substrate is formed by polishing a surface of diamond to a first degree of smoothness; forming a material, such as diamond, BeO, GaN, MgO, or SiO2 or other oxides, over the polished surface to provide an intermediate structure; and re-polishing the material formed on the intermediate structure to a second degree of smoothness smoother than the first degree of smoothness. The diamond is bonded to the semiconductor structure, such as GaN, by providing a structure having bottom surfaces of a semiconductor on an underlying material; forming grooves through the semiconductor and into the underlying material; separating semiconductor along the grooves into a plurality of separate semiconductor structures; removing the separated semiconductor structures from the underlying material; and contacting the bottom surface of at least one of the separated semiconductor structures to the diamond substrate.Type: GrantFiled: May 14, 2012Date of Patent: May 28, 2013Assignee: Raytheon CompanyInventors: Ralph Korenstein, Mary K. Herndon, Chae Deok Lee
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Patent number: 8450152Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.Type: GrantFiled: July 28, 2011Date of Patent: May 28, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yuping Gong, Yan Xun Xue
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Patent number: 8450739Abstract: An electrooptical device substrate, contains: a first insulating film provided on a substrate; two or more pixels; a first concave portion provided in the first insulating film over the two or more pixels; a second concave portion provided on the bottom surface of the first concave portion; a thin film transistor containing an organic semiconductor layer provided in the second concave portion, a gate insulating film provided on the organic semiconductor layer, and a gate electrode provided on the gate insulating film and being matched to one pixel among the two or more pixels; a scanning line which is provided at an upper side with respect to the gate insulating film and provided in the first concave portion over the two or more pixels; and a data line electrically connected to the thin film transistor.Type: GrantFiled: December 22, 2010Date of Patent: May 28, 2013Assignee: Seiko Epson CorporationInventor: Soichi Moriya
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Patent number: 8450184Abstract: Manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. The stress layer may comprise a flexible material.Type: GrantFiled: May 24, 2012Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra Sadana
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Publication number: 20130130473Abstract: A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.Type: ApplicationFiled: December 14, 2012Publication date: May 23, 2013Inventors: Nadia Ben Mohamed, Ta-Ko Chuang, Jeffrey Scott Cites, Daniel Delprat, Alex Usenko
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Publication number: 20130130425Abstract: The invention relates to a method for producing a semiconductor, of the photovoltaic cell type, or similar electronic components. According to the invention, at least one silicon wafer is cut from the cross-section of a silicon rod and, after doping, a substrate is assembled on either side of the silicon wafer and the latter is cut into two parts through the thickness of the silicon, so as to form two semiconductor units each comprising a substrate and a thin silicon film.Type: ApplicationFiled: March 25, 2010Publication date: May 23, 2013Inventor: Jean-Pierre Medina
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Patent number: 8445360Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.Type: GrantFiled: February 15, 2011Date of Patent: May 21, 2013Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Masayuki Nakanishi, Tetsuji Togawa, Kenya Ito, Masaya Seki, Kenji Iwade, Takeo Kubota
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Patent number: 8445325Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.Type: GrantFiled: June 26, 2007Date of Patent: May 21, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
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Patent number: 8445358Abstract: An object of the present invention is to reduce the influence of a foreign substance adhering to a single crystalline semiconductor substrate and manufacture a semiconductor substrate with a high yield. Another object of the present invention is to manufacture, with a high yield, a semiconductor device which has stable characteristics. In the process of manufacturing a semiconductor substrate, when an embrittled region is to be formed in a single crystalline semiconductor substrate, the surface of the single crystalline semiconductor substrate is irradiated with hydrogen ions from oblique directions at multiple (at least two) different angles, thereby allowing the influence of a foreign substance adhering to the single crystalline semiconductor substrate to be reduced and allowing a semiconductor substrate including a uniform single crystalline semiconductor layer to be manufactured with a high yield.Type: GrantFiled: March 24, 2011Date of Patent: May 21, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Keiichi Sekiguchi
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Patent number: 8445359Abstract: To provide a manufacturing method of a semiconductor device using an SOI substrate, by which mobility can be improved. A plurality of semiconductor films formed using a plurality of bond substrates (semiconductor substrates) are bonded to one base substrate (support substrate). At least one of the plurality of bond substrates has a crystal plane orientation different from that of the other bond substrates. Accordingly, at least one of the plurality of semiconductor films formed over one base substrate has a crystal plane orientation different from that of the other semiconductor films. The crystal plane orientation of the semiconductor film is determined in accordance with the polarity of a semiconductor element formed using the semiconductor film. For example, an n-channel element in which electrons are majority carriers is formed using a semiconductor film having a face {100}, and a p-channel element in which holes are majority carriers is formed using a semiconductor film having a face {110}.Type: GrantFiled: June 16, 2011Date of Patent: May 21, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Koichiro Tanaka
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Publication number: 20130122629Abstract: The present innovations relate to optical/electronic structures, and, more particularly, to methods and products consistent with composite structures for optical/electronic applications, such as solar cells and displays, composed of a silicon-containing material bonded to a substrate and including laser treatment.Type: ApplicationFiled: August 10, 2012Publication date: May 16, 2013Inventor: Venkatraman Prabhakar
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Patent number: 8440487Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.Type: GrantFiled: February 24, 2012Date of Patent: May 14, 2013Assignee: Philtech Inc.Inventor: Yuji Furumura
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Publication number: 20130115753Abstract: A method of manufacturing a thin film-bonded substrate in which a high-quality gallium nitride (GaN) thin film can be transferred. The method includes implanting ions into a first GaN substrate from a Ga surface thereof and thereby forming a first ion implantation layer, bonding a first heterogeneous substrate onto the Ga surface of the first GaN substrate, cleaving the first GaN substrate along the first ion implantation layer and thereby leaving a second GaN substrate on the first heterogeneous substrate, implanting ions into the second GaN substrate from an N surface thereof and thereby forming a second ion implantation layer, bonding a second heterogeneous substrate onto the N surface of the second GaN substrate, and cleaving the second GaN substrate along the second ion implantation layer and thereby leaving a GaN thin film.Type: ApplicationFiled: November 5, 2012Publication date: May 9, 2013Applicant: SAMSUNG CORNING PRECISION MATERIALS CO., LTD.Inventor: Samsung Corning Precision Materials Co., Ltd.
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Patent number: 8436447Abstract: In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided.Type: GrantFiled: April 23, 2010Date of Patent: May 7, 2013Assignee: SanDisk 3D LLCInventors: Pankaj Kalra, Raghuveer S. Makala
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Patent number: 8435866Abstract: At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.Type: GrantFiled: September 28, 2010Date of Patent: May 7, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Taro Nishiguchi, Makoto Sasaki, Shin Harada, Kyoko Okita, Hiroki Inoue, Shinsuke Fujiwara, Yasuo Namikawa
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Patent number: 8435870Abstract: A method for manufacturing a semiconductor device includes: forming a first and second layers not firmly adhering to each other over a substrate; forming a first semiconductor element layer and a first insulating layer over the second layer; forming a hole reaching the first layer in the first insulating layer; oxidizing the first layer exposed at a bottom of the hole; forming a wiring electrically connected to the first semiconductor element layer over the first insulating layer and in the hole; and separating the first layer and the substrate from the second layer and the first semiconductor element layer and expose the wiring. Further, another method includes providing an anisotropic conductive adhesive between a second semiconductor element layer separated through a manufacturing process similar to the above and the wiring, whereby the first and second semiconductor element layers are electrically connected through the anisotropic conductive adhesive and the wiring.Type: GrantFiled: April 26, 2010Date of Patent: May 7, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mayumi Mikami, Konami Izumi
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Publication number: 20130105949Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Shigeki TANEMURA, Kazuki SATO, Atsushi IIJIMA
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Patent number: 8432021Abstract: An object is to provide a manufacturing method of an SOI substrate in which a plurality of single crystal semiconductor layers uniform in quality is bonded to a substrate having a larger area than a single crystal silicon substrate. At the time of a heat treatment, uniform heat distribution in single crystal semiconductor substrates is realized by using a tray which has depression portions each with a large depth and is not in contact with the single crystal semiconductor substrate bonded to a base substrate as a tray for supporting the base substrate and holding the single crystal semiconductor substrates. Further, by providing a supporting portion for the base substrate between the depression portions of the tray, a contact area between the tray and the base substrate is reduced.Type: GrantFiled: May 25, 2010Date of Patent: April 30, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tomoaki Moriwaka
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Publication number: 20130102126Abstract: A method for manufacturing a bonded wafer including: forming an ion-implanted layer in a bond wafer, bonding the bond wafer to a base wafer, delaminating the bond wafer at the ion-implanted layer, and performing a flattening heat treatment on a surface after delamination, in which a silicon single crystal wafer is used as the bond wafer where the region to form the ion-implanted layer has a resistivity of 0.2 ?cm or less, the ion-implanted layer is formed where the ion dose for forming the layer is 4×1016/cm2 or less, and the flattening heat treatment is performed in an atmosphere including HCl gas. Therefore, a method for manufacturing a bonded wafer having a low resistivity thin film (SOI layer) that contains dopant, such as boron, with high concentration according to the ion-implantation delamination method, where outward diffusion of dopant and suction due to oxidation can be inhibited to maintain low resistivity.Type: ApplicationFiled: April 21, 2011Publication date: April 25, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroji Aga, Satoshi Oka, Nobuhiko Noto
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Patent number: 8426292Abstract: A method of fabricating semiconductor devices is disclosed. The method comprises providing a wafer comprising a substrate with a plurality of epitaxial layers mounted on the substrate. Patterns are formed above the plurality of epitaxial layers remote from the substrate. A second substrate of a conductive metal is formed on the plurality of epitaxial layers remote from the substrate and between the patterns. The second substrate, the plurality of epitaxial layers and the substrate are at least partially encapsulated with a soft buffer material. The substrate is separated from the plurality of epitaxial layers at the wafer level and while the plurality of epitaxial layers are intact while preserving electrical and mechanical properties of the plurality of epitaxial layers by applying a laser beam through the substrate to an interface of the substrate and the plurality of epitaxial layers, the laser beam having well defined edges.Type: GrantFiled: December 1, 2008Date of Patent: April 23, 2013Assignee: Tinggi Technologies Private LimitedInventors: Shu Yuan, Xuejun Kang
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Publication number: 20130093059Abstract: A bonded substrate, the surface roughness of which is reduced, and a method of manufacturing the same. The bonded substrate includes a base substrate and an intermediate layer disposed on the base substrate. The intermediate layer has a greater bubble diffusivity than the base substrate. A thin film layer is bonded onto the intermediate layer, and has a different chemical composition from the base substrate.Type: ApplicationFiled: October 11, 2012Publication date: April 18, 2013Applicant: SAMSUNG CORNING PRECISION MATERIALS CO., LTD.Inventor: Samsung Corning Precision Materials, Co., Ltd.
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Publication number: 20130093063Abstract: A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer.Type: ApplicationFiled: October 11, 2012Publication date: April 18, 2013Applicant: SAMSUNG CORNING PRECISION MATERIALS CO., LTD.Inventor: Samsung Corning Precision Materials Co., Ltd.
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Patent number: 8421006Abstract: A device for generating sprays of charged droplets, and resulting nanoparticles, the device comprising a first needle connected to an electrical potential line to generate a first spray of charged particles from the first needle, and a second needle spaced apart from and facing the first needle, and connected to an electrical line configured to ground the second needle or to apply a voltage to the second needle that is the same polarity as the voltage applied to the first needle. The device also comprising an electric field modifier connected to the first needle, and configured to modify an electrical field to generate a second spray of charged particles from the second needle.Type: GrantFiled: November 9, 2010Date of Patent: April 16, 2013Assignee: MSP CorporationInventors: Amir A. Naqwi, Christopher W. Fandrey, Zeeshan H. Syedain
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Patent number: 8420503Abstract: A method for easily manufacturing a transparent SOI substrate having: a main surface with a silicon film formed thereon; and a rough main surface located on a side opposite to a side where the silicon film is formed. A method for manufacturing transparent SOI substrate, having a silicon film formed on a first main surface of the transparent insulating substrate, while a second main surface of the transparent insulating substrate, an opposite to the first main surface, is roughened. The method includes at least the steps of: roughening the first main surface with an RMS surface roughness lower than 0.7 nm and the second main surface with an RMS surface roughness higher than the surface roughness of the first main surface to prepare the transparent insulating substrate; and forming the silicon film on the first main surface of the transparent insulating substrate.Type: GrantFiled: April 1, 2009Date of Patent: April 16, 2013Assignee: Shin—Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Makoto Kawai, Atsuo Ito, Yoshihiro Kubota, Kouichi Tanaka, Yuji Tobisaka, Hiroshi Tamura
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Patent number: 8420500Abstract: The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm.Type: GrantFiled: September 11, 2008Date of Patent: April 16, 2013Assignee: SoitecInventors: Brigitte Soulier-Bouchet, Sébastien Kerdiles, Walter Schwarzenbach
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Patent number: 8420978Abstract: A high-throughput, low cost, patterning platform is provided that is an alternative to conventional photolithography and direct laser ablation patterning techniques. The processing methods are useful for making patterns of microsized and/or nanosized structures having accurately selected physical dimensions and spatial orientation that comprise active and passive components of a range of microelectronic devices. Processing provided by the methods is compatible with large area substrates, such as device substrates for semiconductor integrated circuits, displays, and microelectronic device arrays and systems, and is useful for fabrication applications requiring patterning of layered materials, such as patterning thin film layers in thin film electronic devices.Type: GrantFiled: January 18, 2007Date of Patent: April 16, 2013Assignees: The Board of Trustees of the University of Illinois, Anvik CorporationInventors: Kanti Jain, Junghun Chae, Sreeram Appasamy
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Patent number: 8420504Abstract: There are provided a semiconductor device having a structure which can realize not only suppression of a punch-through current but also reuse of a silicon wafer used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. A semiconductor film into which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted is formed over a substrate, and a single crystal semiconductor film is bonded to the semiconductor film by an SOI technique to form a stacked semiconductor film. A channel formation region is formed using the stacked semiconductor film, thereby suppressing a punch-through current in a semiconductor device.Type: GrantFiled: November 9, 2010Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Sho Kato, Fumito Isaka, Tetsuya Kakehata, Hiromichi Godo, Akihisa Shimomura
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Patent number: 8420506Abstract: A process for cleaving a substrate for the purpose of detaching a film therefrom. The method includes the formation of a stress-generating structure locally bonded to the substrate surface and designed to expand or contract in a plane parallel to the substrate surface under the effect of a heat treatment; and the application of a heat treatment to the structure, designed to cause the structure to expand or contract so as to generate a plurality of local stresses in the substrate which generates a stress greater than the mechanical strength of the substrate in a cleavage plane parallel to the surface of the substrate defining the film to be detached, the stress leading to the cleavage of the substrate over the cleavage plane. Also, an assembly of a substrate and the stress-generating structure as well as use of the assembly in a semiconductor device for photovoltaic, optoelectronic or electronic applications.Type: GrantFiled: November 29, 2011Date of Patent: April 16, 2013Assignee: SoitecInventor: Michel Bruel
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Patent number: 8420502Abstract: A method for producing a Group III-V semiconductor device, includes forming, on a base, a plurality of semiconductor devices isolated from one another, forming, through ion implantation, a high-resistance region in a surface layer of a side surface of each semiconductor device, after formation of the high-resistance region, forming a p-electrode and a low-melting-point metal diffusion prevention layer on the top surface of the semiconductor device, bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer, and removing the base through the laser lift-off process.Type: GrantFiled: February 22, 2010Date of Patent: April 16, 2013Assignee: Toyoda Gosei Co., Ltd.Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Kazuyoshi Tomita
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Patent number: 8420501Abstract: A method includes arranging a first bonding layer on a first functional region on a first substrate, or a region on a second substrate, bonding the first functional region to the second substrate through the first bonding layer, subjecting a first release layer to a first process to separate the first substrate from the first functional region at the first release layer, arranging a second bonding layer on a second functional region on the first substrate, or a region on a third substrate, bonding the second functional region to the second or third substrate through the second bonding layer, and subjecting a second release layer to a second process to separate the first substrate from the second functional region at the second release layer.Type: GrantFiled: November 3, 2009Date of Patent: April 16, 2013Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Yasuyoshi Takai
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Publication number: 20130089968Abstract: A process for finishing an as transferred layer on a semiconductor-on-insulator structure or a semiconductor-on-glass (or other insulator substrate) structure is provided by removing the damaged surface portion of a semiconductor layer while a leaving a smooth, finished semiconductor film on the glass. The damaged surface layer is treated with an oxygen plasma to oxidize the damaged layer and convert the damaged layer into an oxide layer. The oxide layer is then stripped in a wet bath, such as hydrofluoric acid bath, thereby removing the damaged portion of the semiconductor layer. The damaged layer may be an ion implantation damaged layer resulting from a thin film transfer processes used to make the semiconductor-on-insulator structure or the semiconductor-on-glass structure.Type: ApplicationFiled: June 28, 2011Publication date: April 11, 2013Inventor: Alex Usenko
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Publication number: 20130089967Abstract: The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this.Type: ApplicationFiled: September 27, 2012Publication date: April 11, 2013Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventor: SHIN-ETSU CHEMICAL CO., LTD.
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Patent number: 8415228Abstract: To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode.Type: GrantFiled: September 9, 2009Date of Patent: April 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Takashi Shingu, Taichi Endo
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Patent number: 8415208Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.Type: GrantFiled: July 15, 2002Date of Patent: April 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Junya Maruyama, Mayumi Mizukami, Shunpei Yamazaki
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Patent number: 8415186Abstract: The present invention provides a method of super flat chemical mechanical polishing (SF-CMP) technology, which is a method characterized in replacing laser lift-off in a semiconductor fabricating process. SF-CMP has a main step of planting a plurality of polishing stop points before polishing the surface, which is characterized by hardness of the polishing stop points material being larger than hardness of the surface material. Therefore, the present method can achieve super flat polishing surface without removing polishing stop points.Type: GrantFiled: August 10, 2007Date of Patent: April 9, 2013Assignee: Hong Kong Applied Science and Technology Research Institute Co. Ltd.Inventors: Yong Cai, Hung-Shen Chu
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Patent number: 8415230Abstract: Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.Type: GrantFiled: March 1, 2010Date of Patent: April 9, 2013Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Yasuyoshi Takai
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Patent number: 8415231Abstract: A photovoltaic device uses a single crystal or polycrystalline semiconductor layer which is separated from a single crystal or polycrystalline semiconductor substrate as a photoelectric conversion layer and has a SOI structure in which the semiconductor layer is bonded to a substrate having an insulating surface or an insulating substrate. A single crystal semiconductor layer which is a separated surface layer part of a single crystal semiconductor substrate and is transferred is used as a photoelectric conversion layer and includes an impurity semiconductor layer to which hydrogen or halogen is added on a light incidence surface or on an opposite surface. The semiconductor layer is fixed to a substrate having an insulating surface or an insulating substrate.Type: GrantFiled: August 19, 2011Date of Patent: April 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai
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Publication number: 20130084687Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.Type: ApplicationFiled: September 14, 2012Publication date: April 4, 2013Applicant: STMicroelectronics (Crolles 2) SASInventors: Julien CUZZOCREA, Laurent-Luc CHAPELON
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Publication number: 20130082361Abstract: Provided are a method of manufacturing a flexible device and a flexible device manufactured thereby. The method of manufacturing a flexible device according to the present disclosure includes: fabricating a device on an upper silicon layer of a silicon-on-insulator (SOI) substrate comprising a lower silicon layer, an insulation layer and the upper silicon layer stacked sequentially; adhering a second silicon substrate to the upper silicon layer; removing the lower silicon layer; transferring the upper silicon layer with the device fabricated to a flexible substrate using the second silicon substrate; and stacking a passivation layer on the flexible substrate, wherein the device is located at a position of a neutral mechanical plane of the entire device as the passivation layer is stacked.Type: ApplicationFiled: February 14, 2012Publication date: April 4, 2013Inventors: Keon Jae LEE, Kwyro Lee, Geon Tae Hwang, Donggu Im
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Patent number: 8409966Abstract: A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by the feature in which the following process A and process B are repeated. The process A includes irradiation of a surface of a semiconductor wafer with cluster ions to form a separation layer in the semiconductor wafer. The semiconductor wafer and a substrate having an insulating surface are then overlapped with each other and bonded, which is followed by thermal treatment to separate the semiconductor wafer at or around the separation layer. A separation wafer and an SOT substrate which has a crystalline semiconductor layer over the substrate having the insulating surface are simultaneously obtained by the process A. The process B includes treatment of the separation wafer for reusing, which allows the separation wafer to be successively subjected to the process A.Type: GrantFiled: July 7, 2011Date of Patent: April 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8409366Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.Type: GrantFiled: June 22, 2010Date of Patent: April 2, 2013Assignee: Oki Data CorporationInventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Masaaki Sakuta, Akihiro Hashimoto
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Patent number: 8409965Abstract: The present disclosure provides one embodiment of a method for fabricating light-emitting diode (LED) devices. The method includes forming a nano-mask layer on a first substrate, wherein the nano-mask layer has a randomly arranged grain pattern; growing a first epitaxy semiconductor layer in the first substrate, forming a nano-composite layer; growing a number of epitaxy semiconductor layers over the nano-composite layer; bonding a second substrate to the epitaxy semiconductor layers from a first side of the epitaxy semiconductor layers; applying a radiation energy to the nano-composite layer; and separating the first substrate from the epitaxy semiconductor layers from a second side of the epitaxy semiconductor layers.Type: GrantFiled: April 26, 2011Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsing-Kuo Hsia, Ching-Hua Chiu
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Publication number: 20130075726Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Pascal Fornara
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Publication number: 20130075868Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.Type: ApplicationFiled: September 27, 2011Publication date: March 28, 2013Applicant: SOITECInventors: Mariam Sadaka, Ionut Radu
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Patent number: 8404567Abstract: A manufacturing method of a semiconductor device, includes: forming grooves from a first surface side of a semiconductor wafer; separating plural chip areas into pieces by grinding a second surface of the semiconductor wafer after a protection sheet is attached to the first surface of the semiconductor wafer; attaching a laminated film in which a dicing film and an adhesive film are sequentially laminated on a supporting film composed of a resin film with high modulus of elasticity to the second surface of the semiconductor wafer; and cutting the adhesive film.Type: GrantFiled: March 2, 2010Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Yusuke Dohmae
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Patent number: 8404563Abstract: The embrittlement layer and the semiconductor layer remaining on the periphery of the semiconductor substrate after separation are selectively removed using a mixed solution containing a substance functioning as an oxidizer for oxidizing a semiconductor, a substance dissolving an oxide of a semiconductor, and a substance functioning as a decelerator of oxidization of a semiconductor and dissolution of an oxide of a semiconductor. Note that the semiconductor film is separated from the semiconductor substrate along an embrittlement layer that is formed in the semiconductor substrate by implantation of an H+ ion generated from a hydrogen gas with use of an ion implantation apparatus.Type: GrantFiled: June 22, 2010Date of Patent: March 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kazuya Hanaoka
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Patent number: 8404562Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.Type: GrantFiled: September 30, 2010Date of Patent: March 26, 2013Assignee: Infineon Technologies AGInventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze
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Publication number: 20130069195Abstract: According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate.Type: ApplicationFiled: March 14, 2012Publication date: March 21, 2013Inventor: Kyoichi Suguro