Abstract: A photovoltaic device uses a single crystal or polycrystalline semiconductor layer which is separated from a single crystal or polycrystalline semiconductor substrate as a photoelectric conversion layer and has a SOI structure in which the semiconductor layer is bonded to a substrate having an insulating surface or an insulating substrate. A single crystal semiconductor layer which is a separated surface layer part of a single crystal semiconductor substrate and is transferred is used as a photoelectric conversion layer and includes an impurity semiconductor layer to which hydrogen or halogen is added on a light incidence surface or on an opposite surface. The semiconductor layer is fixed to a substrate having an insulating surface or an insulating substrate.

Abstract: The present invention provides a method of super flat chemical mechanical polishing (SF-CMP) technology, which is a method characterized in replacing laser lift-off in a semiconductor fabricating process. SF-CMP has a main step of planting a plurality of polishing stop points before polishing the surface, which is characterized by hardness of the polishing stop points material being larger than hardness of the surface material. Therefore, the present method can achieve super flat polishing surface without removing polishing stop points.

Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.

Abstract: A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Abstract: Described herein is a novel technique used to make novel thin III-V semiconductor cleaved facet edge emitting active optical devices, such as lasers and optical amplifiers. These fully processed laser platelets with both top side and bottom side electrical contacts can be thought of as freestanding optoelectronic building blocks that can be integrated as desired on diverse substrates for a number of applications, many of which are in the field of communications. The thinness of these platelets and the precision with which their dimensions are defined using the process described herein makes it conducive to assemble them in dielectric recesses on a substrate, such as silicon, as part of an end-fire coupled, coaxial alignment optoelectronic integration strategy. This technology has been used to integrate edge emitting lasers onto silicon substrates, a significant challenge in the field of silicon optoelectronics.

Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

Abstract: A manufacturing method of a semiconductor device, includes: forming grooves from a first surface side of a semiconductor wafer; separating plural chip areas into pieces by grinding a second surface of the semiconductor wafer after a protection sheet is attached to the first surface of the semiconductor wafer; attaching a laminated film in which a dicing film and an adhesive film are sequentially laminated on a supporting film composed of a resin film with high modulus of elasticity to the second surface of the semiconductor wafer; and cutting the adhesive film.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.

Abstract: There is provided a thin-sheet glass substrate laminate which is approximately 100% impermeable to gas or vapor and has a high transparency and a thin thickness, and a method of manufacturing the same. A support is temporarily attached to one surface of a glass substrate after forming a pattern P on the one surface, the glass substrate is thinned by etching another surface of the glass substrate, a film base is temporarily attached to the etched another surface, the temporarily attached support is peeled off from the one surface of the glass substrate, the one surface from which the support is peeled off is laminated to a surface of a cover glass, and the temporarily attached film base is peeled off from the another surface.

Abstract: A method of adjustment on manufacturing of a monolithic oscillator including circuit elements and a BAW resonator, this method including the steps of: a) forming the circuit elements and the resonator and electrically connecting them; b) covering the resonator with a frequency adjustment layer; c) measuring the output frequency of the oscillator; d) modifying the thickness of the frequency adjustment layer to modify the output frequency of the oscillator.

Abstract: Microelectronic devices include a conductive via that extends into a substrate face and that also protrudes beyond the substrate face to define a conductive via end surface and a conductive via sidewall that extends from the end surface towards the substrate face. A conductive cap is provided on the end surface, the conductive cap including a conductive cap body that extends across the end surface and a flange that extends from the conductive cap body along the conductive via sidewall towards the substrate face. Related fabrication methods are also described.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: An oscillator device manufacturing method includes: placing an oscillator provided with electrodes on a convex pedestal provided on an assembly table; arranging, on the assembly table, a frame member including an opening surrounded by a frame thereof and provided with electrode pads on the frame such that the opening is positioned at the pedestal; connecting the electrode pads to the electrodes of the oscillator placed on the pedestal via wires, while the frame member is arranged on the assembly table; removing the frame member from the assembly table together with the oscillator after the connecting, and bonding the frame member connected to the oscillator to a substrate. By using the method, the oscillator device including the oscillator suspended in air above the substrate can be efficiently manufactured. In stead of using the frame member, a frame body in which frame members are arrayed can be employed.

Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.

Abstract: A method for manufacturing a bonded wafer including the steps of: implanting at least one gas ion of a hydrogen ion and a rare gas ion into a bond wafer from a surface thereof to form an ion-implanted layer; bonding the ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an oxide film; thereafter delaminating the bond wafer at the ion-implanted layer to prepare the bonded wafer having a silicon thin film formed on the base wafer; and performing a flattening heat treatment on the bonded wafer under an atmosphere containing hydrogen or hydrogen chloride, wherein a dopant gas is added into the atmosphere of the flattening heat treatment to perform the heat treatment, the dopant gas having the same conductivity type as a dopant contained in the silicon thin film.

Abstract: A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: Methods are provided for fabricating integrated circuit systems that include forming integrated circuits in and on a semiconductor substrate. Via holes are etched into a front surface of the semiconductor substrate and are filled with a conductive material. A carrier wafer having a layer of adhesive thereon is provided and an imprinted pattern is formed in the layer of adhesive. The front surface of the semiconductor substrate is bonded to the carrier wafer with the patterned layer of adhesive. A portion of a back surface of the semiconductor substrate is removed to expose a portion of the conductive material and the thinned back surface is attached to a second substrate. The semiconductor substrate is then de-bonded from the carrier wafer.

Abstract: The invention relates to a method of eliminating fragments of material present on the exposed surface of a first wafer bonded to a second wafer, the method including a step consisting of placing the first wafer in a liquid solution and propagating ultrasonic waves in the solution. The invention also relates to a process for manufacturing a multilayer structure comprising the following successive steps: bonding of a first wafer to a second wafer so as to form a multilayer structure; annealing of the structure; and thinning of the first wafer, including at least one step of chemically etching the first wafer. The process further includes, after the chemical etching step, the elimination of fragments of material present on the exposed surface of the thinned first wafer.

Abstract: To provide a semiconductor substrate in which a semiconductor element having favorable crystallinity and high performance can be formed. A single crystal semiconductor substrate having an embrittlement layer and a base substrate are bonded with an insulating layer interposed therebetween; the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment; a single crystal semiconductor layer is fixed to the base substrate; the single crystal semiconductor layer is irradiated with a laser beam; the single crystal semiconductor layer is in a partially melted state to be recrystallized; and crystal defects are repaired. In addition, the energy density of a laser beam with which the best crystallinity of the single crystal semiconductor layer is obtained is detected by a microwave photoconductivity decay method.

Abstract: An object of the present invention is to provide an SOI substrate including a semiconductor layer which is efficiently planarized. A method for manufacturing an SOI substrate includes a step of irradiating a bond substrate with an accelerated ion to form an embrittlement region; a step of bonding the bond substrate and the base substrate with an insulating layer positioned therebetween; a step of splitting the bond substrate at the embrittlement region to leave a semiconductor layer bonded to the base substrate; a step of disposing the semiconductor layer in front of a semiconductor target containing the same semiconductor material as the semiconductor layer; and a step of alternately irradiating the surface of the semiconductor layer and the semiconductor target with a rare gas ion, so that the surface of the semiconductor layer is planarized.

Abstract: The invention relates to a process for fabricating a multilayer structure that includes bonding a first wafer onto a second wafer, where the first wafer may have a chamfered edge and the bonding interface has an adhesion energy of less than or equal to 1 J/m2, and thinning the first wafer so as to form a transferred layer, where before thinning the first wafer, a step of trimming the edge of the first wafer is carried out using a grinding wheel having a working surface which comprises grit particles with an average size of greater than or equal to 800 mesh or less than or equal to 18 microns, and wherein the trimming step is carried out by lowering the grinding wheel at a rate of descent of greater than or equal to 5 microns per second, such that the descent of the grinding wheel into the first wafer continues to a distance from the bonding interface that is less than or equal to 30 ?m.

Abstract: An embodiment of this invention discloses a method of separating two material systems, which comprises steps of providing a bulk sapphire; forming a nitride system on the bulk sapphire; forming at least two channels between the bulk sapphire and the nitride system; etching at least one inner surface of the channel; and separating the bulk sapphire and the nitride system.

Abstract: Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain.

Abstract: An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.

Abstract: The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.

Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Abstract: The present invention provides a method for manufacturing an SOI wafer wherein an HCl gas is mixed in a reactive gas at a step of forming a silicon epitaxial layer on an entire surface of an SOI layer of the SOI wafer having an oxide film on a terrace portion. As a result, it is possible to provide the method for manufacturing an SOI wafer that can easily grow the silicon epitaxial layer on the SOI layer of the SOI wafer having the oxide film on the terrace portion, suppress warpage of the SOI wafer to be manufactured, reduce generation of particles even at subsequent steps, e.g., device manufacture, and decrease a cost for manufacturing such an SOI wafer.

Abstract: A method for producing a light-emitting device, includes: performing, on a first substrate made of III-V group compound semiconductor, crystal growth of a laminated body including an etching easy layer contiguous to the first substrate and a light-emitting layer made of nitride semiconductor; bonding a second substrate and the laminated body; and detaching the second substrate provided with the light-emitting layer from the first substrate by, one of removing the etching easy layer by using a solution etching method, and removing the first substrate and the etching easy layer by using mechanical polishing method.

Abstract: A MEMS mirror for a laser printing application includes providing a CMOS substrate including a pair of electrodes, and providing a reflecting mirror moveable over the substrate and the electrodes. Voltages applied to the electrodes create an electrostatic force causing an end of the mirror to be attracted to the substrate. A precise position of the mirror can be detected and controlled by sensing a change in capacitance between the mirror ends and the underlying electrodes.

Abstract: A method for thinning a structure of at least two assembled wafers, where one of the wafers includes channels on its surface facing the other wafer. In order to cause thinning of the structure, a fluid is introduced into the channels in a supercritical state and the fluid is passed from the supercritical state into the gaseous state. The channels do not open to the outside of the structure, such that the method further includes forming at least one access opening to the channels from the outer surface of the structure and before introducing the fluid in the supercritical state.

Abstract: Provided is a method for manufacturing an SOI wafer, which is capable of: efficiently removing an ion-implanted defect layer existing in an ion implanted layer in the vicinity of a peeled surface peeled by an ion implantation peeling method; ensuring the in-plane uniformity of a substrate; and also achieving cost reduction and higher throughput. The method for manufacturing an SOI wafer includes at least the steps of: bonding a silicon wafer with or without an oxide film onto a handle wafer to prepare a bonded substrate, wherein the silicon wafer has an ion implanted layer formed by implanting hydrogen ions and/or rare gas ions into the silicon wafer; peeling the silicon wafer along the ion implanted layer, thereby transferring the silicon wafer onto the handle wafer to produce a post-peeling SOI wafer; immersing the post-peeling SOI wafer in an aqueous ammonia-hydrogen peroxide solution; and performing a heat treatment at a temperature of 900° C.

Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.

Abstract: A workpiece machining method includes attaching a workpiece to a workpiece support with the aid of joining means. The workpiece and the workpiece support are joined to one another by an annular joining means. The composite produced is machined. The machined workpiece is separated from the workpiece support.

Abstract: Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.

Abstract: An advanced, very high transmittance, back-illuminated, silicon-on-sapphire wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon layers, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiNX<1.33), that provides optimal refractive index matching between sapphire and silicon. A one quarter wavelength, magnesium fluoride (?/4-MgF2) antireflective layer deposited on the back surface of the thinned sapphire provides refractive index matching at the air-sapphire interface. Selecting a composition of x=0.62 for a-SiNX, tunes an optimal refractive index for the layer. Selecting design thicknesses of 52 nm for single crystal AlN, 30 nm for a-SiN0.

Abstract: The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer.

Abstract: A semiconductor device includes a vertical type semiconductor element formed by using a silicon substrate, a P type impurity diffusion layer being formed at a back surface of the silicon substrate. The surface of the P type impurity diffusion layer is wet etched to expose a single silicon crystal surface of the P type impurity diffusion layer, and a metal layer having a work function of 4.5 eV or more is disposed to the single silicon crystal surface so that an ohmic contact is made between the single silicon crystal surface of the P type impurity diffusion layer and the metal layer without making a silicon-metal alloy layer between the P type impurity diffusion layer and the metal layer.

Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.

Abstract: The invention pertains to a combination of a substrate (6) and a wafer (15), wherein the substrate (6) and the wafer (15) are arranged parallel to one another and bonded together with the aid of an adhesive layer (8) situated between the substrate (6) and the wafer (15), and wherein the adhesive is chosen such that its adhesive properties are neutralized or at least diminished when a predetermined temperature is exceeded. According to the invention, the adhesive layer (8) is only applied annularly between the substrate (6) and the wafer (15) in the edge region of the wafer (15).

Abstract: Provided are a semiconductor surface protecting method and surface protecting sheet employing a material having adequate conformability for irregularities on semiconductor wafer circuit sides and sufficient rigidity as a support during grinding, and which does not become fluid with repeated temperature increases. Also provided is a surface protecting sheet for protection of the circuit side in the step of back side grinding of a semiconductor wafer, the surface protecting sheet having a polymeric film material with a surface protecting layer thereon that may become fluid upon heating and which hardens upon exposure to radiation or upon heating.

Abstract: A semiconductor substrate is provided by a method suitable for mass production. Further, a semiconductor substrate having an excellent characteristic with effective use of resources is provided.

Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.

Abstract: In a method of manufacturing a semiconductor thin film piece device, a plurality of semiconductor thin film pieces (14) are selected from among the semiconductor thin film pieces (14) formed on a first substrate (35), and bonded to a first set of predetermined area on a second substrate (12). Subsequently, a plurality of semiconductor thin film pieces are selected from the remaining semiconductor thin film pieces (14), and bonded to a second set of predetermined area.

Abstract: A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.

Abstract: Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully spanning a distance between the first and second chip surfaces.

Abstract: The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.