Abstract: To avoid problems of hydrolysis of the silicon oxide formed by PECVD at the surface of at least one wafer, it is proposed to cover, in the vacuum deposition chamber used to deposit the silicon oxide, said oxide with a temporary protective layer containing nitrogen. The protective layer thus protects the silicon oxide against the outer environment and especially against humidity when the wafer provided with the silicon oxide is stored outside of the vacuum deposition chamber. Afterwards, the protective layer is removed, for example, by chemical-mechanical. polishing, just before the two wafers are placed into contact. The protective layer may be formed by a PECVD silicon nitride deposition, by plasma nitriding or nitrogen doping of a superficial portion of the silicon oxide.

Abstract: A method for producing a stacked structure having an ultra thin buried oxide (UTBOX) layer therein by forming an electrical insulator layer on a donor substrate, introducing elements into the donor substrate through the insulator layer, forming an electrical insulator layer, on a second substrate, and bonding the two substrates together to form the stack, with the two insulator layers limiting the diffusion of water and forming the UTBOX layer between the two substrates at a thickness of less than 50 nm, wherein the donor oxide layer has, during bonding, a thickness at least equal to that of the bonding oxide layer.

Abstract: In the manufacturing steps of a power-type semiconductor device, after grinding the back surface of the semiconductor wafer, when a metal film is deposited by sputtering deposition over the back surface of the wafer in a preheated state, the wafer is contained in an annular susceptor, and processed. A radial vertical cross section of the annular shape of the susceptor has a first upper surface closer to a horizontal surface for holding a peripheral portion of the top surface of the semiconductor wafer against gravity, and a second upper surface continued to and located outside the first upper surface and closer to a vertical surface for holding a side surface of the semiconductor wafer against lateral displacement.

Abstract: A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

Abstract: A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate.

Abstract: Methods of forming electro-micromechanical resonators provide passive temperature compensation of semiconductor device layers used therein. A first substrate is provided that includes a first electrically insulating temperature compensation layer on a first semiconductor device layer. A step is performed to bond the first electrically insulating temperature compensation layer to a second substrate containing the second electrically insulating temperature compensation layer therein, to thereby form a relatively thick temperature compensation layer. A piezoelectric layer is formed on the first electrically insulating temperature compensation layer and at least a first electrode is formed on the piezoelectric layer.

Abstract: The process comprises the following steps: a) a first element (3) or a plurality of said first elements (3) is/are machined in a first silicon wafer (1) keeping said elements (3) joined together via material bridges (5); b) step a) is repeated with a second silicon wafer (2) in order to machine a second element (4), differing in shape from that of the first element (3), or a plurality of said second elements (4); c) the first and second elements (3, 4) or the first and second wafers (1, 2) are applied, face to face, with the aid of positioning means (6, 7); d) the assembly formed in step c) undergoes oxidation; and e) the parts (10) are separated form the wafers (1, 2). Micromechanical timepiece parts obtained according to the process.

Abstract: In order to produce a power semiconductor for operation at high blocking voltages, there is produced on a lightly doped layer having a doping of a first charge carrier type a medium-doped layer of the same charge carrier type. A highly doped layer is produced at that side of the medium-doped layer which is remote from the lightly doped layer, of which highly doped layer a part with high doping that remains in the finished semiconductor forms a second stop layer, wherein the doping of the highly doped layer is higher than the doping of the medium-doped layer. An electrode is subsequently indiffused into the highly doped layer. The part with low doping that remains in the finished semiconductor forms the drift layer and the remaining medium-doped part forms the first stop layer.

Abstract: A method for making a semiconducting structure, including: a) forming, on a surface of a final semiconductor substrate, a semiconducting layer, doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer, c) then assembling, by direct adhesion of the source substrate, on the final substrate, the layer forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film made from a semiconducting material.

Abstract: A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.

Abstract: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Abstract: A process for forming a thin film of a given material includes providing a first substrate having, on the surface, an amorphous and/or polycrystalline film of the given material and a second substrate is bonded to the first substrate by hydrophobic direct bonding (molecular adhesion), the second substrate having a single-crystal reference film of a given crystallographic orientation on the surface thereof. A heat treatment is applied at least to the amorphous and/or polycrystalline film, where the heat treatment causes at least a portion of the amorphous and/or polycrystalline film to undergo solid-phase recrystallization along the crystallographic orientation of the reference film, where the reference film acts as a recrystallization seed. The at least partly recrystallized film is then separated from at least a portion of the reference film.

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Abstract: When a thermal expansion coefficient of a handle substrate is higher than that of a donor substrate, delamination is provided without causing a crack in the substrates. A method for producing a bonded wafer, with at least the steps of: implanting ions into a donor substrate (3) from a surface thereof to form an ion-implanted interface (5); bonding a handle substrate (7) with a thermal expansion coefficient higher than that of the donor substrate (3) onto the ion-implanted surface of the donor substrate to provide bonded substrates, subjecting the bonded substrates to a heat treatment to provide an assembly (1), and delaminating the donor substrate (3) of the assembly (1) at the ion-implanted interface wherein the assembly (1) has been cooled to a temperature not greater than room temperature by a cooling apparatus (20), so that a donor film is transferred onto the handle substrate (7).

Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer, the method configured to grow an epitaxial layer on an SOI layer of the SOI wafer having the SOI layer on a BOX layer to increase a thickness of the SOI layer, wherein epitaxial growth is carried out by using an SOI wafer whose infrared reflectance in an infrared wavelength range of 800 to 1300 nm falls within the range of 20% to 40% as the SOI wafer on which the epitaxial layer is grown. As a result, a high-quality SOI wafer with less slip dislocation and others can be provided with excellent productivity at a low cost as the SOI wafer including the SOI layer having a thickness increased by growing the epitaxial layer, and a manufacturing method thereof can be also provide.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure includes: (a) a first process of bonding a device wafer and a handling wafer; (b) a second process of thinning a back side of an Si substrate which is formed on the device wafer, after the first process; (c) a third process of forming an anti-reflective layer and a PMD (preferential metal deposition) dielectric layer, after the second process; (d) a fourth process of forming vias on back sides of super contacts which are formed on the Si substrate, after the third process; and (e) a fifth process of forming a pad, after the fourth process.

Abstract: A method for rejoining an IC die, removed from an existing substrate, to a new substrate, is disclosed herein. In one embodiment, such a method includes grinding an existing substrate from an IC die to create a substantially planar surface exposing interconnects and surrounding underfill material. A new substrate is provided having electrically conductive pedestals protruding therefrom. The electrically conductive pedestals are positioned to align with the exposed interconnects and have a melting point substantially higher than the melting point of the interconnects. The method places the exposed interconnects in contact with the electrically conductive pedestals. The method then applies a reflow process to melt and electrically join the exposed interconnects with the electrically conductive pedestals. A structure produced by the method is also disclosed.

Abstract: It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.

Abstract: To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer.

Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

Abstract: A semiconductor device including a first element including a photodiode and an amplifier circuit which amplifies output current of the photodiode, over a first insulating film; and a second element including a color filter and an overcoat layer over the color filter over a second insulating film is manufactured. The first element and the second element are attached to each other by bonding the first insulating film and the second insulating film with a bonding material. Further, the amplifier circuit is a current mirror circuit including a thin film transistor. Still further, a color film may be used instead of a color filter.

Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.

Abstract: A method for producing a semiconductor device includes a step of forming a first insulation film, a step of forming a separation layer in a base layer, a step of forming a light-blocking film on the surface of the first insulation film, a step of forming a second insulation film such that the light-blocking film is covered, a step of affixing the base layer provided with the light-blocking film to a substrate, a step of separating and removing along the separation layer a portion of the base layer affixed to the substrate, and a step of forming a semiconductor layer such that at least a portion thereof overlaps with the light-blocking film.

Abstract: To provide a semiconductor wafer surface protection sheet having good adhesion to irregularities on a patterned surface of a semiconductor wafer and having good peelability after wafer grinding. Specifically, a semiconductor wafer surface protection sheet is provided that includes a base layer having a tensile elasticity at 25° C., E(25), of 1 GPa or more; a resin layer A that satisfies the condition EA(60)/EA(25)<0.1, where EA(25) is a tensile elasticity at 25° C. and EA(60) is a tensile elasticity at 60° C., the EA(60) ranging from 0.005 MPa to 1 MPa; and a resin layer B having a tensile elasticity at 60° C., EB(60), of 1 MPa or more and having a thickness of 0.1 ?m to less than 100 ?m, the EB(60) being larger than the EA(60) of the resin layer A.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract: A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused.

Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.

Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.

Abstract: An integrated circuit package system includes a first integrated circuit die having die pads only adjacent a single edge of the first integrated circuit die, forming first L-shaped leadfingers adjacent the single edge, connecting the die pads and the first L-shaped leadfingers, and encapsulating the die pads and portions of the first L-shaped leadfingers to form a first package.

Abstract: Provided is a method for manufacturing a lamination type semiconductor integrated device that can simultaneously attain grinding force resistance during back side grinding of a semiconductor wafer, heat resistance during anisotropic dry etching and the like, chemical resistance during plating and etching, smooth debonding of a support substrate for processing at the end, and low adherend staining; the method comprises at least a step of back side grinding of a first semiconductor wafer having a device formed on its surface and a step of laminating by electrical bonding the first semiconductor wafer with a second semiconductor wafer having a device formed on its surface, wherein, at the time of back side grinding of the first semiconductor wafer, back of the first semiconductor wafer is ground after surface of formed device on the first semiconductor wafer is bonded to a support substrate for processing by using a pressure-sensitive silicone adhesive.

Abstract: The method may include providing a first substrate, the first substrate including a sacrificial layer, an active layer having an image sensor circuit portion and an interconnection layer electrically connected to the image sensor circuit portion sequentially stacked; performing an edge-trimming process with respect to the first substrate to form an interconnection layer pattern, an active layer pattern and a sacrificial layer pattern; adhering the first substrate to a second substrate; removing the sacrificial layer pattern to expose the active layer pattern; and forming a transillumination layer to provide light to an image sensor portion on the active layer pattern.

Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract: A method of processing a device wafer includes the carrier wafer preparing step of preparing a carrier wafer including an excessive carrier region on a surface thereof which is disposed in a position corresponding to an excessive outer circumferential region on a surface of the device wafer, the recess forming step of forming a recess in the excessive carrier region the carrier wafer, after the recess forming step, the adhesive placing step of placing an adhesive in the recess so as to project from the surface of the carrier wafer, after the adhesive placing step, the wafer bonding step of bonding the surface of the carrier wafer and the surface of the device wafer to each other, thereby securing the device wafer to the carrier wafer with the adhesive, and after the wafer bonding step, the thinning step of thinning the device wafer to a predetermined thickness by grinding or polishing a reverse side of the device wafer.

Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

Abstract: A method for manufacturing a flexible display device in which a flexible substrate is acquired by forming display devices on one side of the substrate and thinning the substrate by removing surface portions on an opposite side of the substrate. The thickness of the substrate is changed from a first thickness, which gives rigidity to the substrate to the second thickness, which gives flexibility to the substrate.

Abstract: Optical modulator utilizing wafer bonding technology. An embodiment of a method includes etching a silicon on insulator (SOI) wafer to produce a first part of a silicon waveguide structure on a first surface of the SOI wafer, and preparing a second wafer, the second wafer including a layer of crystalline silicon, the second wafer including a first surface of crystalline silicon. The method further includes bonding the first surface of the second wafer with a thin oxide to the first surface of the SOI wafer using a wafer bonding technique, wherein a second part of the silicon waveguide structure is etched in the layer of crystalline silicon.

Abstract: Manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. The stress layer may comprise a flexible material.

Abstract: The present invention relates to an electromechanical transducer and a method of producing it, in which the substrate rigidity is maintained to prevent the substrate from being broken during formation of dividing grooves or a film. The electromechanical transducer includes a plurality of elements each having at least one cell. An insulating layer is formed on a first substrate, and gaps are formed in the insulating layer. A second substrate is bonded to the insulating layer provided with the gaps. Then, dividing grooves are formed in the first substrate and are at least partially filled with an insulating member. Then, the thickness of the second substrate bonded to the insulating layer is reduced to form a film.

Abstract: An object of the present invention is to reduce the influence of a foreign substance adhering to a single crystalline semiconductor substrate and manufacture a semiconductor substrate with a high yield. Another object of the present invention is to manufacture, with a high yield, a semiconductor device which has stable characteristics. In the process of manufacturing a semiconductor substrate, when an embrittled region is to be formed in a single crystalline semiconductor substrate, the surface of the single crystalline semiconductor substrate is irradiated with hydrogen ions from oblique directions at multiple (at least two) different angles, thereby allowing the influence of a foreign substance adhering to the single crystalline semiconductor substrate to be reduced and allowing a semiconductor substrate including a uniform single crystalline semiconductor layer to be manufactured with a high yield.

Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.

Abstract: A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.

Abstract: A micro machining method includes utilizing a polymer as an intermediate adhesion layer, and bonding a underlay with a substrate by pressure bonding, thinning the substrate and deep-etching it to form through holes, backfilling the through holes and deep-etching the substrate again to form a plating hole, plating metal in the plating hole to form a support between the underlay and the substrate, and dissolving the through holes, and etching the polymer through the through holes to release structures. Alternatively, after forming the substrate on the underlay, the method can include thinning the substrate and deep-etching it to form a plating hole, plating metal in the plating hole to form a support between the underlay and the substrate, deep-etching the substrate again to form through holes, and etching the polymer through the through holes to release structures.

Abstract: A printed wiring board includes a first insulation layer, a first conductive circuit formed on the first insulation layer, a second insulation layer formed on the first insulation layer and the first conductive circuit and having an opening portion reaching the first conductive circuit, a second conductive circuit formed on the second insulation layer, and a via conductor formed in the opening portion and connecting the first conductive circuit and the second conductive circuit. The via conductor is formed an inner-wall surface of the opening portion and has a seed layer including a nitride compound and/or a carbide compound containing Ti, Zr, Hf, V, Nb, Ta or Si and a plated-metal film formed in the opening portion, and the plated-metal film and the first conductive circuit have at least portions making direct contact.

Abstract: An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract: Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.

Abstract: A method of fabricating integrated circuits is provided in which sacrificial material is provided on a first surface of a substrate to define structural elements, integrated circuit material is provided on the sacrificial material to provide integrated circuit structures as defined by the structural elements, the sacrificial material is removed from the first surface of the substrate to provide partially fabricated integrated circuits defined by the integrated circuit structures, a carrier handle is attached to the partially fabricated integrated circuits, and the substrate is thinned from a second surface of the substrate opposite the first surface to provide the fabricated integrated circuits.

Abstract: A process to thin semiconductor wafers to less than 50 microns employs a dissolvable photoresist or polyimide or other glue material to hold a thick carrier plate such as a perforated glass to the top surface of a thick processed wafer and to grind or otherwise remove the bulk of the wafer from its rear surface, leaving only the preprocessed top surface, which may include semiconductor device diffusions and electrodes. A thick metal such as copper or a more brittle copper alloy is then conductively secured to the ground back surface and the glue is dissolved and the carrier plate is removed. The wafer is then cleaned and diced into plural devices such as MOSFETs; integrated circuits and the like.

Abstract: A process for cleaving a substrate for the purpose of detaching a film therefrom. The method includes the formation of a stress-generating structure locally bonded to the substrate surface and designed to expand or contract in a plane parallel to the substrate surface under the effect of a heat treatment; and the application of a heat treatment to the structure, designed to cause the structure to expand or contract so as to generate a plurality of local stresses in the substrate which generates a stress greater than the mechanical strength of the substrate in a cleavage plane parallel to the surface of the substrate defining the film to be detached, the stress leading to the cleavage of the substrate over the cleavage plane. Also, an assembly of a substrate and the stress-generating structure as well as use of the assembly in a semiconductor device for photovoltaic, optoelectronic or electronic applications.