Abstract: Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.

Abstract: Uniform masking for wafer dicing using laser and plasma etch is described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits having bumps or pillars includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a first mask material layer soluble in a solvent over the semiconductor substrate and a second mask material layer, insoluble in the solvent, over the first mask material layer. The multi-layered mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then plasma etched through the gaps in the patterned mask to singulate the IC with the second mask material layer protecting the first mask material layer for at least a portion of the plasma etch. The soluble material layer is dissolved subsequent to singulation to remove the multi-layered mask.

Abstract: A laser processing method is disclosed, comprising the steps of: directing a laser beam to a workpiece; and effecting a relative motion between the laser beam and the workpiece. In particular, the step of directing the laser beam to the workpiece comprises focusing the laser beam within the workpiece until an internal damage forms within the workpiece and a crack propagates from the internal damage to at least one surface of the workpiece to form a surface crack on the workpiece. Further, the step of effecting the relative motion between the laser beam and the workpiece is such that the surface crack on the workpiece propagates along a line of separation on the workpiece. A laser processing apparatus is also disclosed.

Abstract: A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

Abstract: A laser processing method which can efficiently perform laser processing while minimizing the deviation of the converging point of a laser beam in end parts of an object to be processed is provided.

Abstract: The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

Abstract: An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

Abstract: The present invention provides a method for plasma processing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing at least two cutting regions on the substrate, the cutting regions being positioned between all adjacent device structures on the substrate; generating a plasma using the plasma source; and processing the work piece using the generated plasma.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by forming trenches along singulation lines and initiating a cracks from within the trenches, which propagate through the semiconductor wafer in a more controlled manner.

Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Abstract: The present invention provides a dicing die bond film in which yielding and breaking of the dicing film are prevented and in which the die bond film can be suitably broken with a tensile force. In the dicing die bond film of the present invention, the tensile strength of the contact part in which the outer circumference of the push-up jig contacts the dicing film at 25° C. is 15 N or more and 80 N or less and the yield point elongation is 80% or more, the tensile strength of the wafer bonding part of the dicing film at 25° C. is 10 N or more and 70 N or less and the yield point elongation is 30% or more, [(the tensile strength of the contact part)?(the tensile strength of the wafer bonding part)] is 0 N or more and 60 N or less, and the breaking elongation rate of the die bond film at 25° C. is more than 40% and 500% or less.

Abstract: A method for cutting brittle sheet-shaped structure is disclosed. A brittle sheet-shaped structure having a cutting surface including a first cutting line on the cutting surface of the brittle sheet-shaped structure is formed. The cutting surface is divided into a first section and a second section, wherein the first section has a predetermined shape. At least one second cutting line is formed on the second section along part of the first cutting line or a tangent line of the first cutting line. A number of third cutting lines are formed on the second section by taking the first cutting line as endpoints. A brittle sheet-shaped structure having the predetermined shape is finally obtained by splitting the brittle sheet-shaped structure along the first cutting line, the at least one second cutting line, and the third cutting lines.

Abstract: An object to be processed is reliably cut along a line to cut. An object to be processed is irradiated with laser light while locating a converging point at the object, so as to form a modified region in the object along a line to cut. The object formed with the modified region is subjected to an etching process utilizing an etching liquid exhibiting a higher etching rate for the modified region than for an unmodified region, so as to etch the modified region. This can etch the object selectively and rapidly along the line to cut by utilizing a higher etching rate in the modified region.

Abstract: A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical.

Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.

Abstract: Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.

Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally the present disclosure provide techniques resulting in a optical device comprising a substrate having three or more corners, where at least one of the corners is defined by a dislocation bundle characterized by a diameter of less than 100 microns, the gallium and nitrogen containing substrate having a predefined portion free from dislocation bundle centers, an active region containing one or more active layers, the active region being positioned within the predefined region; and a conductive region formed within the predefined region.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.

Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

Abstract: Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A laser beam processing method for a wafer includes a first processed groove forming step in which a laser beam is radiated along a planned dividing line so that the overlapping rate of condensed beam spots is equal to or less than 95%, to thereby form a first laser beam processed groove. The laser beam processing method for a wafer further includes a second processed groove forming step in which a laser beam is radiated along the first laser beam processed groove in such a manner that the overlapping rate of condensed beam spots is equal to or more than 97%, to thereby form a second laser beam processed groove at a bottom portion of the first laser beam processed groove.

Abstract: The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer.

Abstract: A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test structure is probed, and then a passivation layer overlying the surface of the wafer is formed, the passivation layer overlying the plurality of bond pads and overlying the test structure. Openings in the regions of the passivation layer overlying the plurality of bond pads are then formed to expose the plurality of bond pads while retaining the regions of the passivation layer overlying the test structure until singulation of the wafer. Pad metallizations are formed at the plurality of bond pads via the openings in the regions of the passivation layer and the wafer is singulated. The resulting dies may be packaged and the resulting IC packages may be implemented in electronic devices.

Abstract: A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.

Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.

Abstract: This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads.

Abstract: A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.

Abstract: A semiconductor device comprising scribe areas that include dicing areas for separating chip areas, a groove forming area surrounding each chip area, and includes interlayer insulating lamination disposed above the semiconductor wafer; a multilayer wiring structure formed in the interlayer insulating lamination, the multilayer wiring structure including wiring layers disposed in the chip area, and dummy wirings disposed in the chip area and the scribe area, the wiring layers and the dummy wirings being formed from same mother layers; a cover layer including a passivation layer, the cover layer covering the multilayer wiring structure; and a groove formed in each groove forming area, the groove surrounding the chip areas and extending from a surface of the semiconductor wafer and at least through the passivation layer; wherein the multilayer wiring structure includes no dummy wirings in the groove forming area at least in an uppermost wiring layer.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract: A process to divide a wafer into individual chips is disclosed. The process (1) etches semiconductor layers for an active device to form two grooves putting the virtual cut line therebetween, where the semiconductor wafer is to be divided along the virtual cut line; (2) etches the substrate in a region including the virtual cut line but offset from the groove from the back surface thereof so as to expose the semiconductor layers in the primary surface; and (3) etches the semiconductor layer exposed in step (2).

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a first mask material layer soluble in a solvent over the semiconductor substrate and a second mask material layer, insoluble in the solvent, over the first mask material layer. The multi-layered mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then plasma etched through the gaps in the patterned mask to singulate the IC with the second mask material layer protecting the first mask material layer for at least a portion of the plasma etch. The soluble material layer is dissolved subsequent to singulation to remove the multi-layered mask.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: Methods of dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, lower than the first. Multiple passes of a beam adjusted to have different fluence level or multiple laser beams having various fluence levels may be utilized to ablate mask and IC layers to expose a substrate with the first fluence level and then clean off redeposited materials from the trench bottom with the second fluence level. A laser scribe apparatus employing a beam splitter may provide first and second beams of different fluence from a single laser.

Abstract: The disclosure provides a method for fabricating the flexible electronic devices, including: providing a first rigid carrier substrate and a second rigid carrier substrate, wherein at least one flexible electronic device is formed between the first rigid carrier substrate and the second rigid carrier substrate, and a plurality of first de-bonding areas, a first flexible substrate, the flexible electronic device, a second flexible substrate, a plurality of second de-bonding areas and the second rigid carrier substrate are formed on the first rigid carrier substrate; performing a first cutting step to cut through the first de-bonding areas; separating the first rigid carrier substrate from the first de-bonding areas; removing the first rigid carrier substrate from the first de-bonding areas; and performing a second cutting step to cut through the second de-bonding areas; separating and removing the second rigid carrier substrate from the second de-bonding areas.

Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.

Abstract: A semiconductor device according to the present invention including: a substrate; a compound semiconductor layer formed on the substrate; an element forming area provided in the compound semiconductor layer; and at least one semiconductor element, which includes a first main electrode and a main second electrode, wherein the at least one semiconductor element is formed in the element forming area, wherein the compound semiconductor layer includes: a first compound growth layer, which is formed on the substrate and includes the element forming area; and a second compound growth layer formed on the substrate to surround the element forming area when viewed from a plane, wherein the second compound growth layer has a crystallinity lower than a crystallinity of the first compound growth layer.

Abstract: A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.

Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.

Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.

Abstract: A method of dicing a semiconductor wafer comprises scribing at least one dielectric layer along dice lanes to remove material from a surface of the wafer using a laser with a pulse-width between 1 picosecond and 1000 picoseconds and with a repetition frequency corresponding to times between pulses shorter than a thermal relaxation time of the material to be scribed. The wafer is then diced through a metal layer and at least partially through a substrate of the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a film on a main face of a semiconductor substrate having a plurality of device forming regions for forming semiconductor devices, the film having a coefficient of thermal expansion different from that of the semiconductor substrate and including a cutout on a region between the plurality of device forming regions; forming the semiconductor devices in the respective device forming regions by using the film; and dividing the semiconductor substrate into the respective device forming regions.

Abstract: A computer obtains user input from an input to control a cutter and a conveyor to cut a substrate. The control module of the computer calculates a total number of cuts of the substrate and a distance that the substrate moves before each cut of the substrate according to user input. A conveyer control module of the computer controls the conveyer to move the substrate, where a reminder signal is sent out after the substrate has moved the distance. A cutter control module of the computer controls the cutter to cut the substrate.