Abstract: An array of III-V material transistors singulated from a Si or SiC wafer disposed on a stretchable tape compatible with pick and place tools and a method of forming same.

Abstract: The present disclosure relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a gate stacked structure, a channel layer passing through the gate stacked structure in a vertical direction, a memory layer disposed between the channel layer and the gate stacked structure, a dummy stacked structure extended toward the gate stacked structure, a first dummy pattern passing through the dummy stacked structure in the vertical direction, and a gap arranged in the first dummy pattern.

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: A semiconductor device according to the present embodiment comprises a first metallic line. The first metallic line is provided above a substrate and extends in a first direction with a first width. At least one second metallic line is connected to the first metallic line and extends in a second direction from the first metallic line with a second width that is smaller than the first width. A dummy metallic line is arranged adjacently to the at least one second metallic line, connected to the first metallic line, and extends in the second direction from the first metallic line. The dummy metallic line is not electrically connected to lines other than the first metallic line.

Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.

Abstract: A wafer processing apparatus includes a rotating chuck rotatably installed on a driver, a vacuum chuck which is disposed on the rotating chuck and on which a wafer is seated, a chuck module installed in the rotating chuck to fix the wafer to the vacuum chuck, and a moving module configured to move the vacuum chuck or the chuck module to increase a gap between adjacent dies of the wafer.

Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.

Abstract: A semiconductor wafer thinned by a stealth lasing process, and semiconductor dies formed therefrom. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by focusing a laser at discrete points in the wafer substrate beneath the surface of the wafer. Upon completion of stealth lasing in one or more planar layers in the substrate, a portion of the substrate may be removed, leaving the wafer thinned to a desired final thickness.

Abstract: A substrate having a first side and a second side opposite the first side is processed by providing a protective film having a front surface and a back surface opposite the front surface and providing a holding frame for holding the substrate. The holding frame has a central opening. The holding frame is attached to the back surface of the protective film so as to close the central opening of the holding frame by the protective film, and the first side of the substrate or the second side of the substrate is attached to the front surface of the protective film. The substrate is processed from the side of the substrate which is opposite the side of the substrate attached to the front surface of the protective film, and/or the side of the substrate which is attached to the front surface of the protective film.

Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

Abstract: An illumination system can include a dual junction light-emitting diode (LED) array including first and second junctions that extend in a plane. The first junction can emit first light from a plurality of first light-emitting areas that are separated by first boundaries. The second junction can be disposed on the first junction such that the first light passes through the second junction. The second junction can emit second light from a plurality of second light-emitting areas. The second light-emitting areas can be separated by second boundaries that correspond in a one-to-one correspondence to the first boundaries. The second boundaries can be offset in the plane from the corresponding first boundaries. The offset can help reduce or eliminate dark bands in the combined first and second light, which could be present if the second boundaries were not offset from the first boundaries.

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

Abstract: A wafer structure including a chip substrate and plural inkjet chips is disclosed. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of at least 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the first inkjet chip and the second inkjet chip. Each of the first inkjet chip and the second inkjet chip includes plural ink-drop generators. Each of the ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and form plural horizontal axis array groups having a central stepped pitch equal to 1/600 inches or less.

Abstract: Semiconductor light emitting devices and packages are provided. The semiconductor light emitting device includes a substrate, a luminous structure, and first and second electrodes. The substrate has a first region and a second region that is spaced apart in a first direction from the first region. The luminous structure includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked on the substrate. The first electrode is on the second semiconductor layer. The second electrode is electrically coupled to the first semiconductor layer through plural first openings that penetrate the first electrode, the second semiconductor layer, and the active layer, where the first openings expose the first semiconductor layer. The first electrode is in contact with the second semiconductor layer in the first region and in the second region, and the first openings are in the first region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer having a functional region and a non-functional region surrounding the functional region; a first dielectric layer formed on the wafer; a first opening formed in the first dielectric layer on the non-function region of the wafer; and a first connection layer formed in the first opening. The first connection layer closes a top portion of the first opening and a first void is formed in the first connection layer in the first opening.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. Each of the first inkjet chip and the second inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process and formed on the chip substrate. Each ink-drop generator includes a barrier layer, an ink-supply chamber and a nozzle. The ink-supply chamber and the nozzle are integrally formed in the barrier layer.

Abstract: A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing.

Abstract: An elastic wave device includes a piezoelectric body including a main surface, an IDT electrode provided on the main surface of the piezoelectric body, and a wiring electrode provided on the main surface of the piezoelectric body and electrically connected to the IDT electrode, in which the wiring electrode includes a portion that extends to an edge of the main surface of the piezoelectric body, and a width of the wiring electrode on the edge is narrower than a width of the wiring electrode in a portion not on the edge.

Abstract: The invention relates to methods of processing a wafer, having on one side a device area with a plurality of devices. In particular, the invention relates to a method which comprises providing a protective film, and applying the protective film to the side of the wafer being opposite to the one side, so that at least a central area of a front surface of the protective film is in direct contact with the side of the wafer being opposite to the one side. The method further comprises applying an external stimulus to the protective film during and/or after applying the protective film to the side of the wafer being opposite to the one side, so that the protective film is attached to the side of the wafer being opposite to the one side, and processing the one side of the wafer and/or the side of the wafer being opposite to the one side.

Abstract: A processing device to form a pattern on a surface of an object to be processed using diffraction of a laser beam emitted from a laser source, the device including: a main body providing a space to process the object using the laser beam emitted from the laser source; a laser transmission unit formed at a first portion of the main body, and configured to diffract the laser beam so that a diffracted laser beam is emitted toward the object; an actuator formed at a second portion of the main body, and connected to the laser transmission unit so as to change an emission pattern of the diffracted laser beam while rotating the laser transmission unit vertically/horizontally or in a set radius; and a controller provided at a third portion of the main body, and connected to the actuator to control an operation of the actuator.

Abstract: Provided is a method of manufacturing a display device, in which a defective rate of a display substrate is reduced by, prior to main processing, irradiating a laser to a portion of a processing area of a display substrate, and predicting and correcting a location to which the laser is irradiated. The method includes irradiating a first laser to a first irradiation area of a processing area of a display substrate, obtaining a first image of the processing area of the display substrate, calculating a first displacement between a center of the first irradiation area irradiated with the first laser and a center of the processing area by using the first image, determining a second irradiation area to which a second laser is to be irradiated on the display substrate based on the first displacement, and irradiating the second laser to the second irradiation area.

Abstract: Systems and methods for providing a combined mosquito staging and dissection system are disclosed. The system can include a mosquito staging subsystem; a robotic pick-and-place station; and a dissection, extrusion, collection, and disposal subsystem. The subsystems can include one or more stations to provide orientation, decapitation, extrusion of salivary glands, and disposal of carcasses of the mosquitoes. The resident live sporozoites from the salivary glands can be used to produce Plasmodium SPZ-based vaccines.

Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Abstract: An inspecting device includes a stage configured to support a wafer in which a plurality of rows of modified regions are formed in a semiconductor substrate, a light source configured to output light, an objective lens configured to pass light propagated through the semiconductor substrate, a light detection part configured to detect light passing through the objective lens, and an inspection part configured to inspect whether or not there is a tip of a fracture in an inspection region between a front surface and the modified region closest to the front surface of the semiconductor substrate. The objective lens positions a virtual focus symmetrical with a focus with respect to the front surface in the inspection region. The light detection part detects light propagating from the back surface side of the semiconductor substrate to the back surface side via the front surface.

Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

Abstract: Implementations of a method of singulating a plurality of semiconductor die may include forming an opening in a layer of passivation material coupled to a second side of a semiconductor substrate; etching substantially through a thickness of the semiconductor substrate at the opening in the layer of passivation material to form etched sidewalls along the thickness at a plurality of die streets; and jet ablating one or more portions of the layer of passivation material that overhangs the etched sidewalls.

Abstract: A semiconductor device according to the present embodiment includes a wiring substrate having a wiring layer. A first semiconductor chip is provided above the wiring substrate. A metallic wire connects the first semiconductor chip and the wiring substrate to each other. A silicon chip is provided above the first semiconductor chip and covers above the metallic wire. A resin layer seals the first semiconductor chip and the silicon chip, and the metallic wire. The silicon chip is insulated from the wiring substrate.

Abstract: A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

Abstract: Provided is a wafer processing method for dividing a wafer having devices formed on a front side thereof into individual device chips, the front side being partitioned by a plurality of crossing division lines having a testing metal pattern formed in part thereof into a plurality of regions where the respective devices are formed. The method includes a first modified layer forming step of applying a laser beam of a wavelength having a transmitting property to the wafer with a focal point of the laser beam positioned inside the wafer at a first depth from the back side, thereby forming a first modified layer along a division line, and a second modified layer forming step of applying the laser beam with the focal point positioned at a second depth shallower than the first depth, thereby forming a second modified layer along the same division line.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

Abstract: A protective film composition includes a polymer having the following formula: each of a, b, and c is a mole fraction; a+b+c=1; 0.05?a/(a+b+c)?0.3; 0.1?b/(a+b+c)?0.6; 0.1?c/(a+b+c)?0.6; each of R1, R2, and R3 is a hydrogen atom or a methyl group; R4 is a hydrogen atom, a butyrolactonyl group, or a substituted or unsubstituted C3 to C30 alicyclic hydrocarbon group; and R5 is a substituted or unsubstituted C6 to C30 linear or cyclic hydrocarbon group. A method of manufacturing a semiconductor package includes forming a sawing protective film on a semiconductor structure by using the protective film composition and sawing the sawing protective film and the semiconductor structure from the sawing protective film.

Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.

Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.

Abstract: A micro-electro mechanical system (MEMS) device includes a MEMS substrate, at least one movable element laterally confined within a matrix layer that overlies the MEMS substrate, and a cap substrate bonded to the matrix layer through bonding material portions. A first movable element selected from the at least one movable element is located inside a first chamber that is laterally bounded by the matrix layer and vertically bounded by a first capping surface that overlies the first movable element. The first capping surface includes an array of downward-protruding bumps including respective portions of a dielectric material layer. Each of the downward-protruding bumps has a vertical cross-sectional profile of an inverted hillock. The MEMS device can include, for example, an accelerometer.

Abstract: An integrated circuit assembly including an integrated circuit formed on one side of a substrate and a thermal spreading layer composed of a silver ink directly printed on an opposite side of the substrate from the integrated circuit, where the thermal spreading layer removes heat generated by the integrated circuit. The assembly also includes a heat sink thermally attached to the thermal spreading layer opposite to the substrate, where the heat sink is attached to the thermal spreading layer by printing the same material on the heat sink as the thermal spreading layer and pressing the spreading layer to the heat sink.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: This disclosure relates to a flank wettable semiconductor device, having: a lead frame including a plurality of leads with a lead end portion and a semiconductor die mounted on the lead frame. The lead end portion comprises a recess portion having a height that corresponds to a thickness of the lead end portion, and a plate member mounted on the leadframe at the lead end portion.

Abstract: A laminated element manufacturing method includes a first forming step of forming a first modified region along a line to cut by irradiating a semiconductor substrate of a first wafer with a laser light along the line to cut, a first grinding step of grinding the semiconductor substrate of the first wafer, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second modified region along the line to cut by irradiating a semiconductor substrate of the second wafer with a laser light along the line to cut, and a second grinding step of grinding the semiconductor substrate of the second wafer.

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

Abstract: A method includes attaching a first die and a second die to a carrier; forming a molding material between the first die and second die; and forming a redistribution structure over the first die, the second die and the molding material, the redistribution structure includes a first redistribution region; a second redistribution region; and a dicing region between the first redistribution region and the second redistribution region. The method further includes forming a first opening and a second opening in the dicing region, the first opening and the second opening extending through the redistribution structure and exposing the molding material; and separating the first die and the second die by cutting through a portion of the molding material aligned with the dicing region from a second side of the molding material toward the first side of the molding material, the second side opposing the first side.

Abstract: A dicing system and methods may include a novel way to separate die on a wafer in preparation for packaging that results in smooth diced edges. This is specifically advantageous, but not limited to, edge-coupled photonic chips. This method etches from the front side of the wafer and dices from the back side of the wafer to create a complete separation of die. It creates an optically smooth surface on the front side of the wafer at the location of the optical device (waveguides or other) which enables direct mounting of adjacent devices with low coupling loss and low optical scattering. The backside dicing may be wider than the front side etch, so as to recess this sawed surface and prevent it from protruding outward, resulting in rough surfaces inhibiting a direct joining of adjacent devices.

Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.

Abstract: A method of manufacturing a packaged device chip includes the steps of forming a rewiring layer having rewiring patterns respectively in a plurality of areas demarcated on the rewiring layer by a projected dicing line on a first surface of a support member that has a second surface opposite the first surface, forming a dividing groove for dividing the rewiring layer in the rewiring layer along the projected dicing line, placing device chips in the respective areas on the rewiring layer and connecting the rewiring patterns and the device chips to each other, covering the device chips and the rewiring layer with molded resin while filling the dividing groove with the molded resin, and cutting the molded resin across an area disposed within the dividing groove and narrower than the dividing groove and forming packaged device chips.

Abstract: A package substrate processing method for processing a package substrate having a division line, an electrode being formed on the division line includes a cutting step of cutting the package substrate along the division line by using a cutting blade and a burr removing step of removing burrs produced from the electrode in the cutting step by spraying a fluid to the package substrate along the division line after performing the cutting step. The cutting step includes a step of supplying a cutting liquid containing an organic acid and an oxidizing agent to a cutting area where the package substrate is to be cut by the cutting blade.

Abstract: A wafer processing method includes a wafer providing step of providing the wafer by placing either of a polyolefin sheet or a polyester sheet each of which has a size equal to or larger than that of the wafer, on a flat upper surface of a support table and positioning a front surface of the wafer on an upper surface of the sheet, a sheet thermocompression bonding step of evacuating an enclosing environment in which the wafer is provided through the sheet on the support table, heating the sheet, pressing the wafer to pressure-bond the wafer to the sheet, thereby forming a raised portion by which an outer circumference of the wafer is surrounded, a back surface processing step of processing the back surface of the wafer, and a peeling step of peeling off the wafer from the sheet.

Abstract: A laminate processing method includes a water-soluble resin filling step of filling a water-soluble resin in a division groove formed in a dividing step, a modified layer removing step of positioning a cutting blade in the division groove formed in a back surface of a wafer to cut the division groove in a state in which the water-soluble resin is solidified or half-solidified, thereby removing a modified layer, and a water-soluble resin removing step of supplying cleaning water from the back surface of the wafer with a state in which an expandable tape is expanded being maintained, thereby removing the water-soluble resin being filled in a cut groove and the division groove.

Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.

Abstract: A method according to embodiments of the invention includes providing a light emitting semiconductor structure grown on a substrate. The substrate has a front side and a back side opposite the front side. Notches are formed in the substrate. The notches extend from the front side of the substrate into the substrate. After forming notches in the substrate, the back side of the substrate is thinned to expose the notches.

Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.