Semiconductor Substrate Dicing Patents (Class 438/460)
  • Patent number: 10388814
    Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.
    Type: Grant
    Filed: June 10, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10319088
    Abstract: An inspection apparatus according to an aspect of the present invention includes an EUV light source 11, an illumination optical system 10 provided to apply the EUV light to an EUV mask 60, a concave mirror and a convex mirror 22 configured to reflect the EUV light reflected on the EUV mask 60, a camera 32 configured to detect EUV light reflected on the convex mirror 22 and thereby take an image of the EUV mask 60, an AF light source 16 configured to generate AF light having a wavelength of 450 nm to 650 nm, first and second detectors 27 and 30 configured to detect the AF light reflected on the EUV mask 60 through the concave mirror with the hole 21 and the convex mirror 22, and an processing device 31 configured to adjust a focus point of the EUV light on the EUV mask 60.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 11, 2019
    Assignee: Lasertec Corporation
    Inventors: Hiroki Miyai, Kiwamu Takehisa
  • Patent number: 10297487
    Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Patent number: 10283466
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 7, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
  • Patent number: 10269638
    Abstract: A semiconductor apparatus includes a semiconductor substrate having an upper surface on which a semiconductor element is disposed, a lower surface opposite to the upper surface, and a side surface connecting the upper surface and the lower surface. The side surface has a plurality of concavities that each extend along the edge of the upper surface and that are arranged in a direction intersecting with the upper surface and the lower surface, and a plurality of ridges that are each located at the boundary between adjacent two of the plurality of concavities. The plurality of concavities and the plurality of ridges are covered with an insulating film containing carbon and fluorine.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kunihiro Abe
  • Patent number: 10228720
    Abstract: The present application describes various embodiments of systems and methods for providing internal components for portable computing devices having a thin profile. More particularly, the present application describes internal components configured to fit within a relatively thin outer enclosure.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: March 12, 2019
    Assignee: Apple Inc.
    Inventors: Brett W. Degner, Christiaan A. Ligtenberg, Ron A. Hopkinson, Patrick Kessler, Bradley J. Hamel, Dinesh C. Mathew, John M. Brock, Keith J. Hendren, Peteris K. Augenbergs, Joss N. Giddings, Matthew C. Waldon, Cina Hazegh, Matthew P. Casebolt, Charles A. Schwalbach, Brandon S. Smith, William F. Leggett, Gavin J. Reid, Tom Tate, Gary Thomason
  • Patent number: 10217679
    Abstract: The present invention relates to a method of processing a solder masked carrier with electronic components, comprising the detection of a carrier related reference and the detection of a solder mask dependent reference, which detected reference are used for processing the position of the solder mask on the carrier. The invention also relates to an electronic component as produced with such method.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 26, 2019
    Assignee: Besi Netherlands B.V.
    Inventors: Jurgen Hendrikus Gerhardus Huisstede, Mark Hermans
  • Patent number: 10177026
    Abstract: A method of fabricating a semiconductor structure. The method includes forming a sacrificial gate structure, depositing a dielectric material, and implanting the dielectric material using a silicon cluster gas. The silicon cluster gas has two or more silicon atoms.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-wei Sung, Ming-Hui Li, Ming-Ying Tsai
  • Patent number: 10141196
    Abstract: The present application contemplates a method for manufacturing a power semiconductor device.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 27, 2018
    Assignee: ABB Schweiz AG
    Inventors: Sven Matthias, Charalampos Papadopoulos, Chiara Corvasce, Arnost Kopta
  • Patent number: 10128305
    Abstract: A semiconductor element is disclosed including a construction with electrode-dividing grooves, in which a dark current is smaller than in existing examples. A method of forming such grooves is also disclosed. In an embodiment, grooves, which electrically divide an electrode layer formed on the surface of a substrate, are formed with a V-shaped cross-sectional shape, groove side walls in the electrode layer, constituting the grooves, being sloping surfaces. An embodiment of the method of forming the grooves includes using a dicing blade having a blade distal end portion which is sharpened into a V-shape to cut a semiconductor wafer in which multiple patterns of semiconductor elements including an electrode layer on the surface of a substrate are formed, forming the grooves having a V-shaped cross-sectional shape which divide the electrode layer in each semiconductor element.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 13, 2018
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Sakari Kaneku, Yasuhiro Shuto, Akira Tachibana
  • Patent number: 10121672
    Abstract: There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 6, 2018
    Assignee: Disco Corporation
    Inventor: Koichi Shigematsu
  • Patent number: 10112256
    Abstract: An SiC wafer is produced from a single crystal SiC ingot by a method that includes forming a plurality of breakable layers constituting a separation surface in the SiC ingot, each breakable layer including a modified layer and cracks extending from the modified layer along a c-plane, and separating part of the SiC ingot along the separation surface as an interface to thereby produce the SiC wafer. In forming the separation surface, the energy density of a pulsed laser beam is set to an energy density not causing the formation of an upper damage layer above the breakable layer previously formed due to the reflection of the pulsed laser beam from the breakable layer and not causing the formation of a lower damage layer below the breakable layer previously formed due to the transmission of the pulsed laser beam through the breakable layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Disco Corporation
    Inventor: Kazuya Hirata
  • Patent number: 10115869
    Abstract: The invention relates to an optoelectronic semiconductor chip (10) comprising a carrier (2) and a semiconductor body (1) having an active layer (13) provided for generating electromagnetic radiation. Said carrier (2) has a first main surface (2A) facing the semiconductor body, a second main surface (2B) facing away from the semiconductor body, and a sidewall (2C) arranged between the first main surface and the second main surface. The carrier (2) has a structured region (21, 22, 23, 2C) for enlarging the total surface area of the sidewall, wherein the structured region has singulation traces. The invention also relates to an optoelectronic component (100) comprising such a semiconductor chip and a method for producing a plurality of such semiconductor chips are specified.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 30, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Mathias Kaempf, Simon Jerebic, Ingo Neudecker, Guenter Spath, Michael Huber
  • Patent number: 10103061
    Abstract: Disclosed herein is a processing method of a single-crystal substrate having a film formed on a front side or a back side thereof to divide the single-crystal substrate along a plurality of preset division lines. The method includes a film removing step of removing the film along the division lines, a shield tunnel forming step of applying a pulsed laser beam having a wavelength which permeates through the single-crystal substrate along the division lines to form shield tunnels, each including a fine hole and an amorphous region shielding the fine hole, in the single-crystal substrate along the division lines, and dividing step of exerting an external force on the single-crystal substrate to which the shield tunnel forming step is performed to divide the single-crystal substrate along the division lines.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 16, 2018
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Noboru Takeda, Takumi Shotokuji
  • Patent number: 10056285
    Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 10030174
    Abstract: A protective film-forming composite sheet 10 comprises a pressure sensitive adhesive sheet 16 in which a pressure sensitive adhesive layer 12 is provided on a base material 11, a protective film-forming film 13, and a release film 14. When ? (mN/25 mm) represents the maximum peel force between the protective film-forming film 13 and the release film 14; ? (mN/25 mm) represents the minimum peel force between the pressure sensitive adhesive sheet 16 and the protective film-forming film 13; and ? (mN/25 mm) represents the maximum peel force between the pressure sensitive adhesive sheet 16 and the protective film-forming film 13, the following relationships (1) to (3) hold for ?, ?, and ?; ??70??(1) ?/??0.50??(2) ??2000??(3).
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 24, 2018
    Assignee: LINTEC CORPORATION
    Inventors: Hiroyuki Yoneyama, Naoya Saiki
  • Patent number: 10029466
    Abstract: An ink-jet recording head includes a plurality of recording element substrates each having an ejection pressure generating element configured to generate pressure for ejecting ink from an ink discharge port. The plurality of recording element substrates each include a first surface on which the corresponding ejection pressure generating element is disposed and a second surface, serving as an end surface intersecting with the first surface, being at least partially formed by etching.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirotaka Miyazaki
  • Patent number: 10008433
    Abstract: A semiconductor device includes a semiconductor chip formed using a silicon carbide and having electrodes on a first surface and a second surface opposite to the first surface, a terminal disposed adjacent to the first surface and connected to the electrode on the first surface through a bonding member, and a heat sink disposed adjacent to the second surface and connected to the electrode on the second surface through a bonding member. The first surface is a (0001) plane and a thickness direction of the semiconductor chip corresponds to a [0001] direction. Of the distances between the end portions of the semiconductor chip having a square two-dimensional shape and the end portions of the terminal having a rectangular two-dimensional shape, the shortest distance L1 in a [1-100] direction is shorter than the shortest distance L2 in a [11-20] direction.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 26, 2018
    Assignee: DENSO CORPORATION
    Inventors: Tomoo Morino, Hiroshi Ishino
  • Patent number: 10002836
    Abstract: A method of fabricating a semiconductor product including processing of a semiconductor wafer from a front surface including structures disposed in the substrate of the wafer adjacent to the front surface and forming a wiring embedded in a dielectric layer disposed on the front surface. The wafer is mounted to a carrier wafer at its front surface so that material can be removed from the backside of the wafer to thin the wafer. Backside processing of the wafer includes forming implantations from the backside, forming deep trenches to isolate the structures from other structures within the wafer, forming a through-silicon via to contact features on the frontside of the wafer, and forming a body contact. Several devices can be generated within the same wafer.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 19, 2018
    Assignee: LFoundry S.r.l.
    Inventors: Gerhard Spitzlsperger, Carsten Schmidt
  • Patent number: 9969147
    Abstract: A method for manufacturing a panel includes at least one step as below. A pre-treatment is performed on a first bonding component between two substrates, so that a part of a first bonding portion of the first bonding component becomes a first transformation portion, in which at least one characteristic of the first bonding portion is different from that of the first transformation portion.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 15, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Hua Ai, Tseng Yu
  • Patent number: 9960317
    Abstract: A lamination includes a sheet substrate and a display element layer. The sheet substrate includes a plurality of product regions cut out into a plurality of products and a blank region surrounding the product regions. The display element layer is formed on each of a plurality of display areas placed on each of the plurality of product regions for displaying an image. The sheet substrate adheres to a top of a substrate. The substrate has light transmissivity. A protective film is adhered to the lamination so as to cover the display areas. A divider line is formed in a blank region that surrounds the product regions by removing a portion of the lamination. The substrate is removed from the sheet substrate by irradiating the sheet substrate with a laser beam.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 1, 2018
    Assignee: Japan Display Inc.
    Inventors: Kenji Toribatake, Kazufumi Watabe
  • Patent number: 9947918
    Abstract: Embodiments of the present disclosure pertain to porous silicon particulates and anode materials that contain them. In some embodiments, each of the porous silicon particulates include a plurality of macropores, mesopores and micropores such that the micropores and mesopores are within the macropores. The porous silicon particulates also contain: a coating associated with the porous silicon particulates; and a binding material associated with the porous silicon particulates. The binding material can include binders, carbon materials, polymers, metals, additives, carbohydrates, and combinations thereof.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: April 17, 2018
    Assignees: WILLIAM MARSH RICE UNIVERSITY, LOCKHEED MARTIN CORPORATION
    Inventors: Sibani Lisa Biswal, Michael S. Wong, Madhuri Thakur, Steven L. Sinsabaugh
  • Patent number: 9947645
    Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 17, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD., ENESAS ELECTRONICS CORPORATION
    Inventors: Soon Yoeng Tan, Teck Jung Tang, Ian D. Melville, Yelei Vianna Yao, Yasushi Yamagata
  • Patent number: 9938457
    Abstract: Methods for fabricating coated semiconductor elements are presented. The methods include the steps of combining a phosphor of formula I and a polymer binder to form a composite material, providing a semiconductor wafer including IniGajAlkN, wherein 0?i; 0?j; 0?k, and a sum of i, j and k is equal to 1, coating the composite material on a surface of the semiconductor wafer to form a coated semiconductor wafer, and dicing the coated semiconductor wafer using a cutting fluid apparatus to form one or more coated semiconductor elements. A cutting fluid of the cutting fluid apparatus includes a C1-C20 alcohol, a C1-C20 ketone, a C1-C20 acetate compound, acetic acid, oleic acid, carboxylic acid, a source of A, silicic acid, or a combination thereof.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 10, 2018
    Assignee: General Electric Company
    Inventors: Digamber Gurudas Porob, James Edward Murphy, Florencio Garcia, Srinivas Prasad Sista, Anant Achyut Setlur, William Winder Beers, Fangming Du
  • Patent number: 9929052
    Abstract: A wafer is processed by transferring a wafer to a holding surface of a chuck table by using a suction pad. The front side of the wafer is held through a protective tape on the holding surface under suction. The suction pad is then removed from the back side of the wafer and the back side of the wafer is ground, thereby thinning the wafer and also dividing the wafer into individual device chips. The wafer is mounted on the holding surface while held by the suction pad. The wafer is sandwiched between the suction pad and the holding surface when the suction force is removed. A suction force is applied to the holding surface to thereby hold the front side of the wafer through the protective tape on the holding surface, and the suction pad is then removed from the back side of the wafer.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 27, 2018
    Assignee: Disco Corporation
    Inventors: Masaru Nakamura, Hiroshi Kitamura
  • Patent number: 9929381
    Abstract: Discloses is a packaging equipment, a method for using the same, and a computer readable storage medium. The packaging equipment includes a movable mechanism and a package assembly, and the movable mechanism is configured to drive the package assembly to move along a predetermined path. The package assembly includes a first rotating mechanism and a first functional module disposed along a first axis, a second functional module is disposed on the first rotating mechanism, and the first rotating mechanism is configured to drive the second functional module to rotate around the first axis.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: March 27, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiaolei Zhang, Seiji Fujino, Wei Cui, Xiaohu Wang
  • Patent number: 9893046
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 9887091
    Abstract: A method of processing a wafer includes: a grinding step of grinding a back surface of the wafer to form, on the back side of the wafer, a recess corresponding to a device region and an annular projecting portion corresponding to a peripheral marginal region; and a splitting groove forming step of forming, after the grinding step is conducted, a splitting groove for splitting the device region and the peripheral marginal region from each other at the boundary between the recess and the annular projecting portion, the splitting groove extending from the front surface of the wafer to reach the back surface of the wafer. The splitting groove is formed by dry etching.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: February 6, 2018
    Assignee: DISCO CORPORATION
    Inventor: Katsuhiko Suzuki
  • Patent number: 9842770
    Abstract: A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the movement (i.e., flow) of the contact metal or metal alloy during a reflow anneal process such that a void-free metallization structure of the contact metal or metal alloy is provided.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9839135
    Abstract: A method of producing electronic components each including a substrate-type terminal and a device connected to the substrate-type terminal including a substrate body with first and second principal surfaces opposite to each other and an electrode configured to be connected to the device on the first principal surface, wherein the device is disposed on the first principal surface, includes forming grooves in a substrate from one of the first and second principal surfaces of the substrate such that the substrate is divided into the substrate-type terminals, the grooves each having a depth less than a thickness of the substrate, cutting the substrate from another principal surface opposite to the principal surface of the substrate body such that the grooves penetrate through the substrate in a thickness direction thereof, and mounting the device on each of the first principal surfaces.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: December 5, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazuto Ogawa, Takashi Watanabe, Junya Shimakawa, Mitsuhide Kato
  • Patent number: 9812362
    Abstract: Disclosed herein is a wafer processing method including a cover plate providing step of providing a cover plate on the front side of a wafer to thereby form a composite wafer, a welding step of applying a laser beam along each division line formed on the front side of the wafer in the condition where the focal point of the laser beam is set at the interface between the wafer and the cover plate on opposite sides of the lateral center of each division line, thereby forming two parallel welded lines for joining the wafer and the cover plate along each division line, and a dividing step of forming a cut line between the two parallel welded lines formed along each division line, thereby cutting the composite wafer along each division line to obtain individual device chips each covered with the cover plate.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 7, 2017
    Assignee: Disco Corporation
    Inventors: Noboru Takeda, Hiroshi Morikazu
  • Patent number: 9769924
    Abstract: A land grid array (LGA) includes a grid array of metal pads plated directly onto a printed circuit board, and a discrete metal pad soldered to each of the plated metal pads in the grid array. Each discrete metal pad has an exposed contact surface after soldering, and a thickness of each discrete metal pad is selected as a function of location in the grid array so that the discrete pads provide a locus of exposed surfaces having greater flatness than the printed circuit board.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 19, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Larry G. Pymento, Tony C. Sass, Paul A. Wormsbecher
  • Patent number: 9764978
    Abstract: A method and device for separating a substrate with a laser beam. The duration of the laser beam's effect is extremely short, so the substrate is only modified concentrically about the laser beam axis (Z) without it degrading the substrate material. While the laser beam acts upon the substrate, the substrate moves relative to a laser machining head, producing plural filament-type modifications along a separating surface to be incorporated. The laser beam is initially diverted by a transmission medium having a higher intensity dependent refractive index than air, then reaches the substrate. The non-constant pulsed laser intensity increases to a maximum over the temporal course of the single pulse, then reduces, and the refractive index changes. The laser beam focus point moves between the substrate's outer surfaces along the beam axis (Z), reaching the desired modification along the beam axis (Z) without correcting the laser machining head in the z-axis.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: September 19, 2017
    Assignee: LPKF LASER & ELECTRONICS AG
    Inventors: Robin Alexander Krueger, Norbert Ambrosius, Roman Ostholt
  • Patent number: 9768127
    Abstract: Disclosed herein is a wafer processing method including a first modified layer forming step of applying a laser beam having a transmission wavelength to a wafer from the back side thereof along each division line in the condition where the focal point of the laser beam is set inside the wafer near the front side thereof, thereby forming a first modified layer inside the wafer along each division line. The wafer processing method further includes a second modified layer forming step of applying the laser beam to the wafer from the back side thereof along each division line in the condition where the focal point of the laser beam is set adjacent to the first modified layer thereabove toward the back side of the wafer, thereby forming a second modified layer for growing a crack from the first modified layer toward the front side of the wafer.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: September 19, 2017
    Assignee: Disco Corporation
    Inventor: Masaru Nakamura
  • Patent number: 9748119
    Abstract: Disclosed herein is a wafer processing method in which laser processing is carried out on a wafer along streets. The wafer processing method includes a step of holding the wafer by a chuck table, a protective film forming step of forming a water-soluble protective film on a surface of the wafer, a laser beam irradiating step of irradiating the wafer with a laser beam along the streets after the protective film forming step, a step of supplying a chemical having an amino group to the wafer, and a removing step of cleaning and removing a compound that is generated by the supplying of the chemical having an amino group and contains phosphorus.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 29, 2017
    Assignee: Disco Corporation
    Inventors: Senichi Ryo, Hirokazu Matsumoto, Toshiyuki Yoshikawa, Yukinobu Ohura
  • Patent number: 9750133
    Abstract: According to one embodiment, there is provided a printed circuit board including a substrate having a trench between a first region and a second region. The first region is a region where a first package is to be mounted. The second region is a region where a second package is to be mounted. The trench has an opening portion in at least one of a first main surface and a second main surface of the substrate. The first main surface is a surface on which the first package is placed. The second main surface is positioned on reverse side of the first main surface of the substrate.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 29, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toyokazu Shibata, Osamu Wada
  • Patent number: 9730331
    Abstract: A display panel motherboard and a manufacturing method thereof are provided. The display panel motherboard comprises display panel regions (Q1) spaced apart from each other and precut regions (Q2) adjacent to the display panel regions. The manufacturing method comprises forming an electrical insulating layer (102); and removing at least portions of the electrical insulating layer provided on the precut regions (Q2). The method avoids the problem of other patterns offset on the display panel motherboard caused by the larger internal stress within the electrical insulating layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: August 8, 2017
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Guang Yang, Peng Shen, Yanming Wang
  • Patent number: 9721823
    Abstract: A method of transferring micro-devices is provided. A carrying unit including a carrying substrate, a plurality of electrodes, a dielectric layer covering the electrodes, and a plurality of micro-devices disposed on the electrodes, including a first micro-device and a second micro-device, are also provided. A voltage is applied to an electrode corresponding to the first micro-device, so that an electrostatic force generated on the first micro-device by the carrying unit is larger than a force generated on the second micro-device by the carrying unit. A transfer stamp contacts the first micro-device and the second micro-device, and moves when the transfer stamp contacts the first micro-device and the second micro-device and the electrostatic force is greater than the force generated by the carrying unit, so that the second micro-device is picked up by the transfer stamp and transferred to a receiving unit, and the first micro-device remains on the carrying unit.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 1, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Tsung-Tien Wu, Ho-Cheng Lee, Kang-Hung Liu, Chih-Che Kuo
  • Patent number: 9697981
    Abstract: A blanking system for multi charged particle beams includes a blanking aperture array device to include a first substrate where a plurality of openings corresponding to passage positions of multi-beams are formed in a penetrating manner from the upper surface, and a plurality of electrode groups each having a pair of electrodes which are close to a corresponding one of the plurality of openings and are at opposite sides, on a same surface, of the corresponding one of the plurality of openings are arranged on the first substrate, a second substrate whose lower surface is electrically connected through a bump to the upper surface of the first substrate, and a mounting substrate whose upper surface is electrically connected through a bump to the lower surface of the second substrate.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 4, 2017
    Assignee: NuFlare Technology, Inc.
    Inventor: Hiroshi Matsumoto
  • Patent number: 9679772
    Abstract: A method including: providing a structure comprising: a spalled layer having a first side and a second side; and a tape layer provided on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range; applying a temporary substrate layer to the second side of the spalled layer, wherein the temporary substrate layer is applied at a second temperature range, and wherein at least a portion of the second temperature range is lower than the first temperature range; and after applying the temporary substrate layer, separating the tape layer from the spalled layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: June 13, 2017
    Assignees: International Business Machines Corporation, AZUR SPACE SOLAR POWER GMBH
    Inventors: Stephen W. Bedell, Tim Kubera, Chérubin Noumissing Sao
  • Patent number: 9595646
    Abstract: According to one embodiment, an electronic component includes a metal portion, a mold resin covering at least a part of the metal portion, and a molecular adhesion layer provided between a surface of the metal portion and the mold resin.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiko Happoya, Daigo Suzuki
  • Patent number: 9576932
    Abstract: In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a plurality of dice attached to die pads in the leadframe. A laser beam is used to form individual plastic capsules for each package, and a second laser beam is used to singulate the packages by severing the metal conductors, tie bars and rails between the packages. A wide variety of different types of packages, from gull-wing footed packages to leadless packages, with either exposed or isolated die pads, may be fabricated merely by varying the patterns of the openings in the mask layers and the width of the plastic trenches created by the first laser beam.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 21, 2017
    Assignee: ADVENTIVE IPBANK
    Inventors: Richard K. Williams, Keng Hung Lin
  • Patent number: 9570352
    Abstract: A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 14, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Brunnbauer, Bernhard Drummer, Korbinian Kaspar, Gunther Mackh
  • Patent number: 9543474
    Abstract: The semiconductor optical device has a chip of semiconductor lamination having a first semiconductor layer of a first conductivity type having a first surface, a second semiconductor layer of a second conductivity type opposite to the first conductivity type having a second surface, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, the chip having side surface including a first side surface which is contiguous to the second surface, forms an obtuse angle with the second surface, extends across the second semiconductor layer and the active layer, and enters the first semiconductor layer, and a cracked surface which is contiguous to the first side surface, a first conductivity type side electrode formed on the first surface, and a second conductivity type side electrode formed on the second surface, wherein in-plane size of the semiconductor lamination is 50 ?m or less.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: January 10, 2017
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Tatsuma Saito
  • Patent number: 9508595
    Abstract: A design method includes a process of preparing plural cutting members having different degrees of taper in a tip portion thereof, a process of preparing plural grooves on a front surface side having the same shape, a process of confirming a breakage status when a groove on a rear surface side is formed by the plural cutting members, and a process of selecting, when it is confirmed that both of a cutting member that causes breakage and a cutting member that does not cause the breakage are included, the degree of taper of the cutting member that does not cause the breakage as a tip shape of a cutting member to be used in a mass production process.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 29, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Takeshi Minamiru, Hiroaki Tezuka, Michiaki Murata, Kenji Yamazaki, Tsutomu Otsuka, Shuichi Yamada, Kenichi Ono
  • Patent number: 9490388
    Abstract: A method of fabricating a plurality of light emitting elements includes forming a nitride semiconductor layer on a growth substrate, the nitride semiconductor layer including at least an n-type nitride semiconductor layer, an active layer made of a nitride semiconductor, and a p-type nitride semiconductor layer stacked in this order; forming a p-electrode layer, the p-electrode layer including portions that correspond to the light emitting elements; forming a p-passivation layer that includes portions between the portions of the p-electrode layer formed on the upper surface of the nitride semiconductor layer; forming a seed layer on the p-electrode layer and the p-passivation layer; forming an insulating layer having portions formed on an upper surface of the seed layer; forming a plating layer on the seed layer; and forming a plating substrate by removing the insulating layer to form spaces between portions of the plating layer.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: November 8, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Kentaro Watanabe, Giichi Marutsuki, Yuya Yamakami
  • Patent number: 9478465
    Abstract: A method of processing a wafer having a device area where a plurality of devices are formed and a peripheral marginal area surrounding the device area on the front side of the wafer is disclosed. The devices are formed in regions defined by division lines. Each device has a plurality of bump electrodes on the front side. A first laser beam is applied through dicing tape from the back side along the boundary between the device area and the peripheral marginal area, with the focal point of the first laser beam set inside the wafer, thereby forming an annular modified layer inside the wafer. A second laser beam is applied through the dicing tape from the back side along each division line with the focal point of the second laser beam set inside the wafer, thereby forming a modified layer inside the wafer along each division line.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 25, 2016
    Assignee: Disco Corporation
    Inventors: Yohei Yamashita, Kenji Furuta, Yihui Lee
  • Patent number: 9472442
    Abstract: A wafer processing method which includes a first tape attaching step of attaching a first tape to the front side of a wafer and mounting the wafer through the first tape to a first annular frame, a separating step of holding the wafer through the first tape on a chuck table and applying a laser beam to the boundary between an annular projection formed along the outer circumference of the wafer and a device area surrounded by the annular projection to cut the wafer and the first tape along this boundary, thereby separating the device area from the annular projection, and a removing step of removing the annular projection together with the first annular frame from the device area of the wafer in the condition where the annular projection is supported through the first tape to the first annular frame.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 18, 2016
    Assignee: Disco Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 9455298
    Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via laser in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: September 27, 2016
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhi-Qi Wang, Qiong Yu, Wei Wang
  • Patent number: 9452495
    Abstract: The present invention discloses a new tool to slice crystal ingots by using laser beams. Ingot crystals of III-nitride such as GaN are immersed in alkali solutions and irradiated with scanned lines of laser beams to slice wafers out of the ingots. The method is expected to achieve approximately one order of magnitude smaller slicing loss with minimized slicing damage.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 27, 2016
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Sierra Hoff