Semiconductor Substrate Dicing Patents (Class 438/460)
  • Patent number: 11503819
    Abstract: Systems and methods for providing a combined mosquito staging and dissection system are disclosed. The system can include a mosquito staging subsystem; a robotic pick-and-place station; and a dissection, extrusion, collection, and disposal subsystem. The subsystems can include one or more stations to provide orientation, decapitation, extrusion of salivary glands, and disposal of carcasses of the mosquitoes. The resident live sporozoites from the salivary glands can be used to produce Plasmodium SPZ-based vaccines.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 22, 2022
    Assignees: Sanaria Inc., The Johns Hopkins University
    Inventors: Russell H. Taylor, Gregory Chirikjian, Iulian Iordachita, Henry Phalen, Hongtao Wu, Mengdi Xu, Shengnan Lu, Michael Aaron Pozin, Jin Seob Kim, Can Kocabalkanli, Balazs Vagvolgyi, Brian K. Chirikjian, Joshua Davis, Ting Da, John S. Chirikjian, Sumana Chakravarty, Stephen Hoffman
  • Patent number: 11488867
    Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: November 1, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Takeshi Harada, Hiroaki Ohta, Yoshihiro Matsushima
  • Patent number: 11450576
    Abstract: An inspecting device includes a stage configured to support a wafer in which a plurality of rows of modified regions are formed in a semiconductor substrate, a light source configured to output light, an objective lens configured to pass light propagated through the semiconductor substrate, a light detection part configured to detect light passing through the objective lens, and an inspection part configured to inspect whether or not there is a tip of a fracture in an inspection region between a front surface and the modified region closest to the front surface of the semiconductor substrate. The objective lens positions a virtual focus symmetrical with a focus with respect to the front surface in the inspection region. The light detection part detects light propagating from the back surface side of the semiconductor substrate to the back surface side via the front surface.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 20, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takeshi Sakamoto, Yasutaka Suzuki, Iku Sano
  • Patent number: 11404276
    Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 2, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11387145
    Abstract: Implementations of a method of singulating a plurality of semiconductor die may include forming an opening in a layer of passivation material coupled to a second side of a semiconductor substrate; etching substantially through a thickness of the semiconductor substrate at the opening in the layer of passivation material to form etched sidewalls along the thickness at a plurality of die streets; and jet ablating one or more portions of the layer of passivation material that overhangs the etched sidewalls.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: July 12, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11373982
    Abstract: A semiconductor device according to the present embodiment includes a wiring substrate having a wiring layer. A first semiconductor chip is provided above the wiring substrate. A metallic wire connects the first semiconductor chip and the wiring substrate to each other. A silicon chip is provided above the first semiconductor chip and covers above the metallic wire. A resin layer seals the first semiconductor chip and the silicon chip, and the metallic wire. The silicon chip is insulated from the wiring substrate.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Kioxia Corporation
    Inventor: Shinji Yamashita
  • Patent number: 11367656
    Abstract: Provided is a wafer processing method for dividing a wafer having devices formed on a front side thereof into individual device chips, the front side being partitioned by a plurality of crossing division lines having a testing metal pattern formed in part thereof into a plurality of regions where the respective devices are formed. The method includes a first modified layer forming step of applying a laser beam of a wavelength having a transmitting property to the wafer with a focal point of the laser beam positioned inside the wafer at a first depth from the back side, thereby forming a first modified layer along a division line, and a second modified layer forming step of applying the laser beam with the focal point positioned at a second depth shallower than the first depth, thereby forming a second modified layer along the same division line.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: June 21, 2022
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 11367655
    Abstract: A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 21, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Takeshi Sakamoto
  • Patent number: 11367654
    Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 21, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Mayer, Evelyn Napetschnig, Michael Pinczolits, Michael Sternad, Michael Roesner
  • Patent number: 11362038
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
  • Patent number: 11309345
    Abstract: A protective film composition includes a polymer having the following formula: each of a, b, and c is a mole fraction; a+b+c=1; 0.05?a/(a+b+c)?0.3; 0.1?b/(a+b+c)?0.6; 0.1?c/(a+b+c)?0.6; each of R1, R2, and R3 is a hydrogen atom or a methyl group; R4 is a hydrogen atom, a butyrolactonyl group, or a substituted or unsubstituted C3 to C30 alicyclic hydrocarbon group; and R5 is a substituted or unsubstituted C6 to C30 linear or cyclic hydrocarbon group. A method of manufacturing a semiconductor package includes forming a sawing protective film on a semiconductor structure by using the protective film composition and sawing the sawing protective film and the semiconductor structure from the sawing protective film.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: April 19, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DONGJIN SEMICHEM CO., LTD.
    Inventors: Myoung-chul Eum, Hye-kyoung Lee, Chang-kun Kang, Jae-hyun Kim, Kyeong-il Oh, Seung-keun Oh, Chi-hwan Lee
  • Patent number: 11289358
    Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11289428
    Abstract: An element chip manufacturing method including: preparing a semiconductor substrate including a first layer having a first principal surface, and a second layer having a second principal surface, the first layer provided with element regions, a dicing region, and an alignment mark, wherein the first layer includes a semiconductor layer, and the second layer includes a metal layer adjacent to the semiconductor layer; irradiating a first laser beam absorbed in the metal film and passing through the semiconductor layer, from the second principal surface side to a first region corresponding to the mark; imaging the semiconductor substrate from the second principal surface side with a camera, and then calculating a second region corresponding to the dicing region on the second principal surface; irradiating a second laser beam to the second region from the second principal surface side; and dicing the semiconductor substrate into a plurality of element chips.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyoshi Arita, Shogo Okita, Hidehiko Karasaki
  • Patent number: 11279611
    Abstract: A micro-electro mechanical system (MEMS) device includes a MEMS substrate, at least one movable element laterally confined within a matrix layer that overlies the MEMS substrate, and a cap substrate bonded to the matrix layer through bonding material portions. A first movable element selected from the at least one movable element is located inside a first chamber that is laterally bounded by the matrix layer and vertically bounded by a first capping surface that overlies the first movable element. The first capping surface includes an array of downward-protruding bumps including respective portions of a dielectric material layer. Each of the downward-protruding bumps has a vertical cross-sectional profile of an inverted hillock. The MEMS device can include, for example, an accelerometer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-wen Cheng, Chi-Hang Chin, Kuei-Sung Chang
  • Patent number: 11264299
    Abstract: An integrated circuit assembly including an integrated circuit formed on one side of a substrate and a thermal spreading layer composed of a silver ink directly printed on an opposite side of the substrate from the integrated circuit, where the thermal spreading layer removes heat generated by the integrated circuit. The assembly also includes a heat sink thermally attached to the thermal spreading layer opposite to the substrate, where the heat sink is attached to the thermal spreading layer by printing the same material on the heat sink as the thermal spreading layer and pressing the spreading layer to the heat sink.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: March 1, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Jesse Tice, Steven J. Mass, Michael T. Barako
  • Patent number: 11244940
    Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao Chun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 11227820
    Abstract: This disclosure relates to a flank wettable semiconductor device, having: a lead frame including a plurality of leads with a lead end portion and a semiconductor die mounted on the lead frame. The lead end portion comprises a recess portion having a height that corresponds to a thickness of the lead end portion, and a plate member mounted on the leadframe at the lead end portion.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: January 18, 2022
    Assignee: Nexperia B.V.
    Inventors: Kan Wae Lam, Wai Hung William Hor, Sven Walczyk, Hans-Juergen Funke
  • Patent number: 11211250
    Abstract: A laminated element manufacturing method includes a first forming step of forming a first modified region along a line to cut by irradiating a semiconductor substrate of a first wafer with a laser light along the line to cut, a first grinding step of grinding the semiconductor substrate of the first wafer, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second modified region along the line to cut by irradiating a semiconductor substrate of the second wafer with a laser light along the line to cut, and a second grinding step of grinding the semiconductor substrate of the second wafer.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 28, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takeshi Sakamoto, Ryuji Sugiura, Yuta Kondoh, Naoki Uchiyama
  • Patent number: 11195820
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 7, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Patent number: 11177142
    Abstract: A method includes attaching a first die and a second die to a carrier; forming a molding material between the first die and second die; and forming a redistribution structure over the first die, the second die and the molding material, the redistribution structure includes a first redistribution region; a second redistribution region; and a dicing region between the first redistribution region and the second redistribution region. The method further includes forming a first opening and a second opening in the dicing region, the first opening and the second opening extending through the redistribution structure and exposing the molding material; and separating the first die and the second die by cutting through a portion of the molding material aligned with the dicing region from a second side of the molding material toward the first side of the molding material, the second side opposing the first side.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Yueh-Ting Lin, An-Jhih Su, Ming Shih Yeh, Der-Chyang Yeh
  • Patent number: 11150409
    Abstract: A dicing system and methods may include a novel way to separate die on a wafer in preparation for packaging that results in smooth diced edges. This is specifically advantageous, but not limited to, edge-coupled photonic chips. This method etches from the front side of the wafer and dices from the back side of the wafer to create a complete separation of die. It creates an optically smooth surface on the front side of the wafer at the location of the optical device (waveguides or other) which enables direct mounting of adjacent devices with low coupling loss and low optical scattering. The backside dicing may be wider than the front side etch, so as to recess this sawed surface and prevent it from protruding outward, resulting in rough surfaces inhibiting a direct joining of adjacent devices.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 19, 2021
    Assignee: GenXComm, Inc.
    Inventors: Brian Mattis, Taran Huffman, Jason Andrach, Hussein Nili, George Palmer
  • Patent number: 11139276
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Patent number: 11133198
    Abstract: A method of manufacturing a packaged device chip includes the steps of forming a rewiring layer having rewiring patterns respectively in a plurality of areas demarcated on the rewiring layer by a projected dicing line on a first surface of a support member that has a second surface opposite the first surface, forming a dividing groove for dividing the rewiring layer in the rewiring layer along the projected dicing line, placing device chips in the respective areas on the rewiring layer and connecting the rewiring patterns and the device chips to each other, covering the device chips and the rewiring layer with molded resin while filling the dividing groove with the molded resin, and cutting the molded resin across an area disposed within the dividing groove and narrower than the dividing groove and forming packaged device chips.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: September 28, 2021
    Assignee: DISCO CORPORATION
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 11101151
    Abstract: A package substrate processing method for processing a package substrate having a division line, an electrode being formed on the division line includes a cutting step of cutting the package substrate along the division line by using a cutting blade and a burr removing step of removing burrs produced from the electrode in the cutting step by spraying a fluid to the package substrate along the division line after performing the cutting step. The cutting step includes a step of supplying a cutting liquid containing an organic acid and an oxidizing agent to a cutting area where the package substrate is to be cut by the cutting blade.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 24, 2021
    Assignee: DISCO CORPORATION
    Inventors: Kenji Takenouchi, Mitsutane Kokubu, Naoko Yamamoto, Chisato Yamada
  • Patent number: 11088008
    Abstract: A wafer processing method includes a wafer providing step of providing the wafer by placing either of a polyolefin sheet or a polyester sheet each of which has a size equal to or larger than that of the wafer, on a flat upper surface of a support table and positioning a front surface of the wafer on an upper surface of the sheet, a sheet thermocompression bonding step of evacuating an enclosing environment in which the wafer is provided through the sheet on the support table, heating the sheet, pressing the wafer to pressure-bond the wafer to the sheet, thereby forming a raised portion by which an outer circumference of the wafer is surrounded, a back surface processing step of processing the back surface of the wafer, and a peeling step of peeling off the wafer from the sheet.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 10, 2021
    Assignee: DISCO CORPORATION
    Inventors: Hayato Kiuchi, Keisuke Yamamoto, Taichiro Kimura
  • Patent number: 11056361
    Abstract: A laminate processing method includes a water-soluble resin filling step of filling a water-soluble resin in a division groove formed in a dividing step, a modified layer removing step of positioning a cutting blade in the division groove formed in a back surface of a wafer to cut the division groove in a state in which the water-soluble resin is solidified or half-solidified, thereby removing a modified layer, and a water-soluble resin removing step of supplying cleaning water from the back surface of the wafer with a state in which an expandable tape is expanded being maintained, thereby removing the water-soluble resin being filled in a cut groove and the division groove.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 6, 2021
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 11037814
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 15, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11038081
    Abstract: A method according to embodiments of the invention includes providing a light emitting semiconductor structure grown on a substrate. The substrate has a front side and a back side opposite the front side. Notches are formed in the substrate. The notches extend from the front side of the substrate into the substrate. After forming notches in the substrate, the back side of the substrate is thinned to expose the notches.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 15, 2021
    Assignee: Lumileds LLC
    Inventors: Filip Ilievski, Norbertus Antonius Maria Sweegers, Kwong-Hin Henry Choy, Marc Andre De Samber
  • Patent number: 11011407
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 18, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11011471
    Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Longitude Licensing Limited
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 10992102
    Abstract: A submount on which a semiconductor device is mounted and which is mounted on a base made of metal, the submount including: a substrate; a first coating layer formed on a first surface of the substrate and made of a material having a higher coefficient of thermal expansion than that of the substrate; and a second coating layer formed on a second surface, positioned on a side opposite to the first surface, of the substrate and made of a material having a higher coefficient of thermal expansion than that of the substrate, in which a coating area of the second coating layer is smaller than a coating area of the first coating layer.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 27, 2021
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Ryuichiro Minato, Yutaka Ohki
  • Patent number: 10951106
    Abstract: A semiconductor device includes a plurality of switching elements electrically connected in parallel with each other, a control unit that outputs a control signal for controlling a current supplied to each of the switching elements, and a temperature estimation unit that estimates a temperature difference between the switching elements. When an estimated temperature difference becomes equal to or higher than a predetermined threshold temperature, the control unit shifts an operation mode to a stop mode for stopping driving of a switching element having a temperature higher than the other.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 16, 2021
    Assignee: DENSO CORPORATION
    Inventor: Hironori Akiyama
  • Patent number: 10859901
    Abstract: Disclosed is a pellicle for extreme ultraviolet (EUV) lithography. The pellicle may include: a support layer pattern which is formed by etching a support layer; a pellicle layer which is formed on the support layer pattern; and an etching stop layer pattern which is formed between the support layer pattern and the pellicle layer and formed by etching an etching stop layer of stopping etching when the support layer is etched. Thus, there is provided a pellicle for EUV photomask, which maintains high transmittance with the minimum thickness for EUV exposure light, and is excellent in mechanical strength and thermal characteristics.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 8, 2020
    Assignee: S&S TECH Co., Ltd.
    Inventors: Kee-Soo Nam, Chang-Hun Lee, Ju-Hee Hong, Chul-Kyun Park
  • Patent number: 10818551
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include exposing a substrate material of a substrate in a die street through removing a metal layer in the die street coupled to the substrate, wherein only a portion of the substrate material in the die street is removed, and singulating a plurality of die included in the substrate through plasma etching the exposed substrate material of the substrate in the die street.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 27, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10796962
    Abstract: A semiconductor wafer processing method includes a step of forming a laser processed groove on the front side of a semiconductor wafer along each division line, a step of forming a mask layer on a protective layer except in an area above a metal electrode formed in each device on the front side of the wafer, a first etching step of etching the protective layer by using the mask layer to expose each metal electrode, a second etching step of etching the inner surface of each laser processed groove by using the mask layer used in the first etching step, thereby expanding each laser processed groove, and a dividing step of dividing the wafer along each laser processed groove expanded in the second etching step.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 6, 2020
    Assignee: DISCO CORPORATION
    Inventors: Masatoshi Wakahara, Frank Wei
  • Patent number: 10731053
    Abstract: A thermally reversible adhesive comprising a) a copolymer of i) a conjugated diene acrylate or methacrylate and ii) at least one acrylic monomer; and b) a bismaleimide crosslinking agent, a process for its preparation, and various end uses, are disclosed.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 4, 2020
    Assignee: Rohm and Haas Company
    Inventors: Daniel W. Himmelberger, Melinda L. Einsla, William B. Griffith, Jr., Brandon Rowe
  • Patent number: 10727128
    Abstract: A method of processing a wafer having on one side a device area with a plurality of devices includes providing a protective film and applying the protective film to the device side of the wafer or to the other side of the wafer, so that at least a central area of a front surface of the protective film is in direct contact with the device side or the other side of the wafer. The protective film is attached to the device side or to other side of the wafer, so that at least a part of a peripheral portion of the protective film is attached to at least a part of a lateral edge of the wafer along the entire circumference of the wafer. The lateral edge of the wafer extends from the device side of the wafer to the other side of the wafer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 28, 2020
    Assignee: DISCO CORPORATION
    Inventors: Karl Heinz Priewasser, Roland Zimmermann, Hitoshi Hoshino
  • Patent number: 10672661
    Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
  • Patent number: 10629462
    Abstract: A wafer processing system includes a laser processing apparatus, a grinding apparatus, a tape sticking apparatus, a first cassette placement part, a second cassette placement part, a conveying unit that conveys a wafer, and a controller that controls the respective constituent elements. The controller includes a first processing program instructing section that conveys a wafer unloaded from a first cassette in order of the laser processing apparatus, the grinding apparatus, the tape sticking apparatus, and a second cassette and sequentially carries out processing by each apparatus for the one wafer, and a second processing program instructing section that conveys the wafer unloaded from the first cassette in order of the grinding apparatus, the laser processing apparatus, the tape sticking apparatus, and the second cassette and sequentially carries out processing by each apparatus for the one wafer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 21, 2020
    Assignee: DISCO CORPORATION
    Inventors: Ken Togashi, Masahiro Tsukamoto
  • Patent number: 10586704
    Abstract: A processing method for a wafer having a plurality of streets inclined at 45° relative to a cleavage direction including a laser processing step of positioning a focusing point of a laser beam with a wavelength as to be transmitted through the wafer in the inside of the wafer, and applying the laser beam along the streets to form a plurality of modified layers, overlapping with one another in the wafer thickness direction, inside the wafer along each of the streets. In the laser processing step, m modified layers (m is a natural number not less than n·?2) are formed overlapping with one another in the wafer thickness direction, where n (n is a natural number) is the number of modified layers needing to be formed overlapping with one another in a wafer thickness direction when dividing a wafer having a plurality of streets parallel to a cleavage direction.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 10, 2020
    Assignee: DISCO CORPORATION
    Inventor: Taewoo Bae
  • Patent number: 10580698
    Abstract: A wafer processing method includes a modified layer forming step of forming a modified layer along a planned dividing line within a wafer and a dividing step of dividing the wafer along the planned dividing line with the modified layer as a starting point by applying a force to the wafer. The modified layer forming step includes a forward path modified layer forming step, a backward path modified layer forming step, and a phase shift mask reversing step of reversing a phase shift mask so as to reverse phase distribution of a laser beam applied to the wafer in an X-axis direction after the forward path modified layer forming step and before the backward path modified layer forming step, or after the backward path modified layer forming step and before the forward path modified layer forming step.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: DISCO CORPORATION
    Inventor: Atsushi Ueki
  • Patent number: 10580670
    Abstract: A controller of a laser processing apparatus includes: a storage section that stores processing conditions for forming modified layers along division lines of a wafer; and a processing line calculation section that displays a position at which the modified layer is planned to be formed and which is stored as the processing condition, on a display panel as a processing line. The processing line calculation section displays the processing line on the display panel superimposed on a first division line, in a region in which a start point or end point of the first division line is connected to a second division line. A start point or end point of a first modified layer formed along the first division line is permitted to be re-set on the display panel so as not to interfere with a second modified layer formed along the second division line.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 3, 2020
    Assignee: DISCO CORPORATION
    Inventor: Tsutomu Maeda
  • Patent number: 10546782
    Abstract: A method of processing a plate-shaped workpiece that includes layered bodies containing metal which are formed in superposed relation to projected dicing lines includes the steps of holding the workpiece on a first holding table such that the layered bodies are exposed, thereafter, cutting the workpiece along the projected dicing lines with a cutting blade to form cut grooves that sever the layered bodies, thereafter, holding the workpiece on a second holding table such that a mask disposed in areas that are exclusive of the projected dicing lines is exposed, and thereafter, performing dry etching on the workpiece through the mask to sever the workpiece along the projected dicing lines. The step of cutting the workpiece includes the step of cutting the workpiece while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: January 28, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10535563
    Abstract: A processing method for a substrate having a metal exposed and having cutting lines of a predetermined width set thereon includes: a structural body disposing step of disposing two structural bodies on the metal along respective edges in regard of the width direction of the cutting line, with a gap corresponding to the width therebetween; and a cutting step of causing a cutting blade to cut into the substrate from between the two structural bodies to cut the substrate along the cutting lines, after the structural body disposing step is carried out.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 14, 2020
    Assignee: DISCO CORPORATION
    Inventor: Makiko Ohmae
  • Patent number: 10535561
    Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, James S. Papanu, Ajay Kumar, Wei-Sheng Lei
  • Patent number: 10529635
    Abstract: A manufacturing method of a semiconductor package includes locating a plurality of semiconductor packages on a substrate, forming a resin insulating layer covering the plurality of semiconductor devices, forming grooves, in the resin insulating layer, enclosing each of the plurality of semiconductor devices and reaching the substrate, and irradiating the substrate with laser light in positional correspondence with the grooves to separate the plurality of semiconductor devices from each other.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 7, 2020
    Assignee: J-Devices Corporation
    Inventors: Hisakazu Marutani, Minoru Kai, Kazuhiko Kitano
  • Patent number: 10508052
    Abstract: With a method of cutting a tube glass (G1) according to the present invention, the tube glass (G1) is irradiated with laser light (L) having a focal point (F) adjusted to an inside of the tube glass (G1), to thereby form an inner crack region (C1) including one or more cracks in a portion of the tube glass (G1) in a circumferential direction of the tube glass (G1) through multiphoton absorption that occurs in an irradiation region of the laser light (L). Then, in the tube glass (G1), there is generated a stress that urges the one or more cracks in the inner crack region (C1) to propagate in the circumferential direction of the tube glass (G1) to cause the one or more cracks to propagate throughout an entire circumference of the tube glass (G1), to thereby cut the tube glass (G1).
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 17, 2019
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventors: Masanori Wada, Masato Inoue
  • Patent number: 10504846
    Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 10, 2019
    Assignee: Longitude Licensing Limited
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 10471546
    Abstract: A laser system is configured to produce a distribution of self-focus damage volumes through the thickness of a substrate. A laser of the laser system produces a laser beam, and an optical assembly receives the laser beam and emits a conditioned laser beam having a geometric focal region. Placing the substrate in the path of the conditioned beam shifts the focal region to an effective focal region. The optical assembly and/or optical elements thereof can be configured such that the distribution of self-focus damage volumes is uniform over the thickness of the substrate by accounting for the non-linear effects of the substrate on the light that propagates through the substrate.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 12, 2019
    Assignee: GENTEX CORPORATION
    Inventors: Kurtis L. Geerlings, Donald L. Bareman, Henry A. Luten, Niels A. Olesen, David J. Cammenga
  • Patent number: 10427936
    Abstract: A method of processing nano- and micro-pores includes washing a substrate and cleaning a surface of the substrate; spin-coating photoresist, exposing the substrate and developing to form the substrate with a pattern; 3. depositing micro-nano metal particles on the surface of the substrate; wherein the micro-nano metal particles are centered on a magnetic core; and the surface of the magnetic core is plated with a metal nano-particle coating composed of a plurality of gold, silver or aluminum nanoparticles; removing the photoresist, and maintaining dot arrays of the micro-nano metal particles; applying laser irradiation and a strong uniform magnetic field on the substrate, so that the substrate is processed to form processed structures; and after the processed structures being formed into nano-/micro-pores with targeted pore size, shape and depth, stopping the laser irradiation and removing the strong uniform magnetic field.
    Type: Grant
    Filed: December 15, 2018
    Date of Patent: October 1, 2019
    Assignee: Guangdong University of Technology
    Inventors: Yun Chen, Xin Chen, Dachuang Shi, Jian Gao, Zhengping Wang, Haidong Yang