Semiconductor Substrate Dicing Patents (Class 438/460)
  • Patent number: 11150409
    Abstract: A dicing system and methods may include a novel way to separate die on a wafer in preparation for packaging that results in smooth diced edges. This is specifically advantageous, but not limited to, edge-coupled photonic chips. This method etches from the front side of the wafer and dices from the back side of the wafer to create a complete separation of die. It creates an optically smooth surface on the front side of the wafer at the location of the optical device (waveguides or other) which enables direct mounting of adjacent devices with low coupling loss and low optical scattering. The backside dicing may be wider than the front side etch, so as to recess this sawed surface and prevent it from protruding outward, resulting in rough surfaces inhibiting a direct joining of adjacent devices.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 19, 2021
    Assignee: GenXComm, Inc.
    Inventors: Brian Mattis, Taran Huffman, Jason Andrach, Hussein Nili, George Palmer
  • Patent number: 11139276
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Patent number: 11133198
    Abstract: A method of manufacturing a packaged device chip includes the steps of forming a rewiring layer having rewiring patterns respectively in a plurality of areas demarcated on the rewiring layer by a projected dicing line on a first surface of a support member that has a second surface opposite the first surface, forming a dividing groove for dividing the rewiring layer in the rewiring layer along the projected dicing line, placing device chips in the respective areas on the rewiring layer and connecting the rewiring patterns and the device chips to each other, covering the device chips and the rewiring layer with molded resin while filling the dividing groove with the molded resin, and cutting the molded resin across an area disposed within the dividing groove and narrower than the dividing groove and forming packaged device chips.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: September 28, 2021
    Assignee: DISCO CORPORATION
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 11101151
    Abstract: A package substrate processing method for processing a package substrate having a division line, an electrode being formed on the division line includes a cutting step of cutting the package substrate along the division line by using a cutting blade and a burr removing step of removing burrs produced from the electrode in the cutting step by spraying a fluid to the package substrate along the division line after performing the cutting step. The cutting step includes a step of supplying a cutting liquid containing an organic acid and an oxidizing agent to a cutting area where the package substrate is to be cut by the cutting blade.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 24, 2021
    Assignee: DISCO CORPORATION
    Inventors: Kenji Takenouchi, Mitsutane Kokubu, Naoko Yamamoto, Chisato Yamada
  • Patent number: 11088008
    Abstract: A wafer processing method includes a wafer providing step of providing the wafer by placing either of a polyolefin sheet or a polyester sheet each of which has a size equal to or larger than that of the wafer, on a flat upper surface of a support table and positioning a front surface of the wafer on an upper surface of the sheet, a sheet thermocompression bonding step of evacuating an enclosing environment in which the wafer is provided through the sheet on the support table, heating the sheet, pressing the wafer to pressure-bond the wafer to the sheet, thereby forming a raised portion by which an outer circumference of the wafer is surrounded, a back surface processing step of processing the back surface of the wafer, and a peeling step of peeling off the wafer from the sheet.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 10, 2021
    Assignee: DISCO CORPORATION
    Inventors: Hayato Kiuchi, Keisuke Yamamoto, Taichiro Kimura
  • Patent number: 11056361
    Abstract: A laminate processing method includes a water-soluble resin filling step of filling a water-soluble resin in a division groove formed in a dividing step, a modified layer removing step of positioning a cutting blade in the division groove formed in a back surface of a wafer to cut the division groove in a state in which the water-soluble resin is solidified or half-solidified, thereby removing a modified layer, and a water-soluble resin removing step of supplying cleaning water from the back surface of the wafer with a state in which an expandable tape is expanded being maintained, thereby removing the water-soluble resin being filled in a cut groove and the division groove.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 6, 2021
    Assignee: DISCO CORPORATION
    Inventor: Masaru Nakamura
  • Patent number: 11037814
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 15, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11038081
    Abstract: A method according to embodiments of the invention includes providing a light emitting semiconductor structure grown on a substrate. The substrate has a front side and a back side opposite the front side. Notches are formed in the substrate. The notches extend from the front side of the substrate into the substrate. After forming notches in the substrate, the back side of the substrate is thinned to expose the notches.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 15, 2021
    Assignee: Lumileds LLC
    Inventors: Filip Ilievski, Norbertus Antonius Maria Sweegers, Kwong-Hin Henry Choy, Marc Andre De Samber
  • Patent number: 11011471
    Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Longitude Licensing Limited
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 11011407
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 18, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10992102
    Abstract: A submount on which a semiconductor device is mounted and which is mounted on a base made of metal, the submount including: a substrate; a first coating layer formed on a first surface of the substrate and made of a material having a higher coefficient of thermal expansion than that of the substrate; and a second coating layer formed on a second surface, positioned on a side opposite to the first surface, of the substrate and made of a material having a higher coefficient of thermal expansion than that of the substrate, in which a coating area of the second coating layer is smaller than a coating area of the first coating layer.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 27, 2021
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Ryuichiro Minato, Yutaka Ohki
  • Patent number: 10951106
    Abstract: A semiconductor device includes a plurality of switching elements electrically connected in parallel with each other, a control unit that outputs a control signal for controlling a current supplied to each of the switching elements, and a temperature estimation unit that estimates a temperature difference between the switching elements. When an estimated temperature difference becomes equal to or higher than a predetermined threshold temperature, the control unit shifts an operation mode to a stop mode for stopping driving of a switching element having a temperature higher than the other.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 16, 2021
    Assignee: DENSO CORPORATION
    Inventor: Hironori Akiyama
  • Patent number: 10859901
    Abstract: Disclosed is a pellicle for extreme ultraviolet (EUV) lithography. The pellicle may include: a support layer pattern which is formed by etching a support layer; a pellicle layer which is formed on the support layer pattern; and an etching stop layer pattern which is formed between the support layer pattern and the pellicle layer and formed by etching an etching stop layer of stopping etching when the support layer is etched. Thus, there is provided a pellicle for EUV photomask, which maintains high transmittance with the minimum thickness for EUV exposure light, and is excellent in mechanical strength and thermal characteristics.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 8, 2020
    Assignee: S&S TECH Co., Ltd.
    Inventors: Kee-Soo Nam, Chang-Hun Lee, Ju-Hee Hong, Chul-Kyun Park
  • Patent number: 10818551
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include exposing a substrate material of a substrate in a die street through removing a metal layer in the die street coupled to the substrate, wherein only a portion of the substrate material in the die street is removed, and singulating a plurality of die included in the substrate through plasma etching the exposed substrate material of the substrate in the die street.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 27, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 10796962
    Abstract: A semiconductor wafer processing method includes a step of forming a laser processed groove on the front side of a semiconductor wafer along each division line, a step of forming a mask layer on a protective layer except in an area above a metal electrode formed in each device on the front side of the wafer, a first etching step of etching the protective layer by using the mask layer to expose each metal electrode, a second etching step of etching the inner surface of each laser processed groove by using the mask layer used in the first etching step, thereby expanding each laser processed groove, and a dividing step of dividing the wafer along each laser processed groove expanded in the second etching step.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 6, 2020
    Assignee: DISCO CORPORATION
    Inventors: Masatoshi Wakahara, Frank Wei
  • Patent number: 10731053
    Abstract: A thermally reversible adhesive comprising a) a copolymer of i) a conjugated diene acrylate or methacrylate and ii) at least one acrylic monomer; and b) a bismaleimide crosslinking agent, a process for its preparation, and various end uses, are disclosed.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 4, 2020
    Assignee: Rohm and Haas Company
    Inventors: Daniel W. Himmelberger, Melinda L. Einsla, William B. Griffith, Jr., Brandon Rowe
  • Patent number: 10727128
    Abstract: A method of processing a wafer having on one side a device area with a plurality of devices includes providing a protective film and applying the protective film to the device side of the wafer or to the other side of the wafer, so that at least a central area of a front surface of the protective film is in direct contact with the device side or the other side of the wafer. The protective film is attached to the device side or to other side of the wafer, so that at least a part of a peripheral portion of the protective film is attached to at least a part of a lateral edge of the wafer along the entire circumference of the wafer. The lateral edge of the wafer extends from the device side of the wafer to the other side of the wafer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 28, 2020
    Assignee: DISCO CORPORATION
    Inventors: Karl Heinz Priewasser, Roland Zimmermann, Hitoshi Hoshino
  • Patent number: 10672661
    Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
  • Patent number: 10629462
    Abstract: A wafer processing system includes a laser processing apparatus, a grinding apparatus, a tape sticking apparatus, a first cassette placement part, a second cassette placement part, a conveying unit that conveys a wafer, and a controller that controls the respective constituent elements. The controller includes a first processing program instructing section that conveys a wafer unloaded from a first cassette in order of the laser processing apparatus, the grinding apparatus, the tape sticking apparatus, and a second cassette and sequentially carries out processing by each apparatus for the one wafer, and a second processing program instructing section that conveys the wafer unloaded from the first cassette in order of the grinding apparatus, the laser processing apparatus, the tape sticking apparatus, and the second cassette and sequentially carries out processing by each apparatus for the one wafer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 21, 2020
    Assignee: DISCO CORPORATION
    Inventors: Ken Togashi, Masahiro Tsukamoto
  • Patent number: 10586704
    Abstract: A processing method for a wafer having a plurality of streets inclined at 45° relative to a cleavage direction including a laser processing step of positioning a focusing point of a laser beam with a wavelength as to be transmitted through the wafer in the inside of the wafer, and applying the laser beam along the streets to form a plurality of modified layers, overlapping with one another in the wafer thickness direction, inside the wafer along each of the streets. In the laser processing step, m modified layers (m is a natural number not less than n·?2) are formed overlapping with one another in the wafer thickness direction, where n (n is a natural number) is the number of modified layers needing to be formed overlapping with one another in a wafer thickness direction when dividing a wafer having a plurality of streets parallel to a cleavage direction.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 10, 2020
    Assignee: DISCO CORPORATION
    Inventor: Taewoo Bae
  • Patent number: 10580670
    Abstract: A controller of a laser processing apparatus includes: a storage section that stores processing conditions for forming modified layers along division lines of a wafer; and a processing line calculation section that displays a position at which the modified layer is planned to be formed and which is stored as the processing condition, on a display panel as a processing line. The processing line calculation section displays the processing line on the display panel superimposed on a first division line, in a region in which a start point or end point of the first division line is connected to a second division line. A start point or end point of a first modified layer formed along the first division line is permitted to be re-set on the display panel so as not to interfere with a second modified layer formed along the second division line.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 3, 2020
    Assignee: DISCO CORPORATION
    Inventor: Tsutomu Maeda
  • Patent number: 10580698
    Abstract: A wafer processing method includes a modified layer forming step of forming a modified layer along a planned dividing line within a wafer and a dividing step of dividing the wafer along the planned dividing line with the modified layer as a starting point by applying a force to the wafer. The modified layer forming step includes a forward path modified layer forming step, a backward path modified layer forming step, and a phase shift mask reversing step of reversing a phase shift mask so as to reverse phase distribution of a laser beam applied to the wafer in an X-axis direction after the forward path modified layer forming step and before the backward path modified layer forming step, or after the backward path modified layer forming step and before the forward path modified layer forming step.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: DISCO CORPORATION
    Inventor: Atsushi Ueki
  • Patent number: 10546782
    Abstract: A method of processing a plate-shaped workpiece that includes layered bodies containing metal which are formed in superposed relation to projected dicing lines includes the steps of holding the workpiece on a first holding table such that the layered bodies are exposed, thereafter, cutting the workpiece along the projected dicing lines with a cutting blade to form cut grooves that sever the layered bodies, thereafter, holding the workpiece on a second holding table such that a mask disposed in areas that are exclusive of the projected dicing lines is exposed, and thereafter, performing dry etching on the workpiece through the mask to sever the workpiece along the projected dicing lines. The step of cutting the workpiece includes the step of cutting the workpiece while supplying a cutting fluid containing an organic acid and an oxidizing agent to the workpiece.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: January 28, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10535563
    Abstract: A processing method for a substrate having a metal exposed and having cutting lines of a predetermined width set thereon includes: a structural body disposing step of disposing two structural bodies on the metal along respective edges in regard of the width direction of the cutting line, with a gap corresponding to the width therebetween; and a cutting step of causing a cutting blade to cut into the substrate from between the two structural bodies to cut the substrate along the cutting lines, after the structural body disposing step is carried out.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 14, 2020
    Assignee: DISCO CORPORATION
    Inventor: Makiko Ohmae
  • Patent number: 10535561
    Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jungrae Park, James S. Papanu, Ajay Kumar, Wei-Sheng Lei
  • Patent number: 10529635
    Abstract: A manufacturing method of a semiconductor package includes locating a plurality of semiconductor packages on a substrate, forming a resin insulating layer covering the plurality of semiconductor devices, forming grooves, in the resin insulating layer, enclosing each of the plurality of semiconductor devices and reaching the substrate, and irradiating the substrate with laser light in positional correspondence with the grooves to separate the plurality of semiconductor devices from each other.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 7, 2020
    Assignee: J-Devices Corporation
    Inventors: Hisakazu Marutani, Minoru Kai, Kazuhiko Kitano
  • Patent number: 10508052
    Abstract: With a method of cutting a tube glass (G1) according to the present invention, the tube glass (G1) is irradiated with laser light (L) having a focal point (F) adjusted to an inside of the tube glass (G1), to thereby form an inner crack region (C1) including one or more cracks in a portion of the tube glass (G1) in a circumferential direction of the tube glass (G1) through multiphoton absorption that occurs in an irradiation region of the laser light (L). Then, in the tube glass (G1), there is generated a stress that urges the one or more cracks in the inner crack region (C1) to propagate in the circumferential direction of the tube glass (G1) to cause the one or more cracks to propagate throughout an entire circumference of the tube glass (G1), to thereby cut the tube glass (G1).
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 17, 2019
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventors: Masanori Wada, Masato Inoue
  • Patent number: 10504846
    Abstract: A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 10, 2019
    Assignee: Longitude Licensing Limited
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 10471546
    Abstract: A laser system is configured to produce a distribution of self-focus damage volumes through the thickness of a substrate. A laser of the laser system produces a laser beam, and an optical assembly receives the laser beam and emits a conditioned laser beam having a geometric focal region. Placing the substrate in the path of the conditioned beam shifts the focal region to an effective focal region. The optical assembly and/or optical elements thereof can be configured such that the distribution of self-focus damage volumes is uniform over the thickness of the substrate by accounting for the non-linear effects of the substrate on the light that propagates through the substrate.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 12, 2019
    Assignee: GENTEX CORPORATION
    Inventors: Kurtis L. Geerlings, Donald L. Bareman, Henry A. Luten, Niels A. Olesen, David J. Cammenga
  • Patent number: 10427936
    Abstract: A method of processing nano- and micro-pores includes washing a substrate and cleaning a surface of the substrate; spin-coating photoresist, exposing the substrate and developing to form the substrate with a pattern; 3. depositing micro-nano metal particles on the surface of the substrate; wherein the micro-nano metal particles are centered on a magnetic core; and the surface of the magnetic core is plated with a metal nano-particle coating composed of a plurality of gold, silver or aluminum nanoparticles; removing the photoresist, and maintaining dot arrays of the micro-nano metal particles; applying laser irradiation and a strong uniform magnetic field on the substrate, so that the substrate is processed to form processed structures; and after the processed structures being formed into nano-/micro-pores with targeted pore size, shape and depth, stopping the laser irradiation and removing the strong uniform magnetic field.
    Type: Grant
    Filed: December 15, 2018
    Date of Patent: October 1, 2019
    Assignee: Guangdong University of Technology
    Inventors: Yun Chen, Xin Chen, Dachuang Shi, Jian Gao, Zhengping Wang, Haidong Yang
  • Patent number: 10418267
    Abstract: A method of processing a semiconductor wafer, in which a mask is formed: by cutting, with CO2 laser, a portion corresponding to a street, out of a temporary-adhesive of a surface protective tape to protect on a patterned face; carrying out dicing with SF6 plasma; and carrying out ashing, by removing a layer of the temporary-adhesive, with O2 plasma; a semiconductor chip; and a surface protective tape.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 17, 2019
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshifumi Oka, Masami Aoyama
  • Patent number: 10410976
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: September 10, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku Asano, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
  • Patent number: 10410901
    Abstract: An electrostatic chuck table includes a plate-shaped base portion capable of transmitting a laser beam to be applied to a workpiece and an electrostatic attraction electrode portion capable of transmitting the laser beam. The laser beam has a transmission wavelength to the workpiece. The base portion has a first surface and a second surface opposite to the first surface. The electrode portion is formed on the first surface of the base portion. A method for using the electrostatic chuck table includes a workpiece holding step of applying a voltage to the electrode portion formed on the first surface to thereby electrostatically hold the workpiece on the second surface, and a modified layer forming step of applying the laser beam through the first surface to a predetermined position inside the workpiece held on the second surface to thereby form a modified layer inside the workpiece.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 10, 2019
    Assignee: DISCO CORPORATION
    Inventors: Kenji Furuta, Yuriko Sato, Sakae Matsuzaki
  • Patent number: 10403629
    Abstract: One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Randy W. Mann, Bipul C. Paul
  • Patent number: 10388814
    Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.
    Type: Grant
    Filed: June 10, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10319088
    Abstract: An inspection apparatus according to an aspect of the present invention includes an EUV light source 11, an illumination optical system 10 provided to apply the EUV light to an EUV mask 60, a concave mirror and a convex mirror 22 configured to reflect the EUV light reflected on the EUV mask 60, a camera 32 configured to detect EUV light reflected on the convex mirror 22 and thereby take an image of the EUV mask 60, an AF light source 16 configured to generate AF light having a wavelength of 450 nm to 650 nm, first and second detectors 27 and 30 configured to detect the AF light reflected on the EUV mask 60 through the concave mirror with the hole 21 and the convex mirror 22, and an processing device 31 configured to adjust a focus point of the EUV light on the EUV mask 60.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 11, 2019
    Assignee: Lasertec Corporation
    Inventors: Hiroki Miyai, Kiwamu Takehisa
  • Patent number: 10297487
    Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou
  • Patent number: 10283466
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 7, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
  • Patent number: 10269638
    Abstract: A semiconductor apparatus includes a semiconductor substrate having an upper surface on which a semiconductor element is disposed, a lower surface opposite to the upper surface, and a side surface connecting the upper surface and the lower surface. The side surface has a plurality of concavities that each extend along the edge of the upper surface and that are arranged in a direction intersecting with the upper surface and the lower surface, and a plurality of ridges that are each located at the boundary between adjacent two of the plurality of concavities. The plurality of concavities and the plurality of ridges are covered with an insulating film containing carbon and fluorine.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kunihiro Abe
  • Patent number: 10228720
    Abstract: The present application describes various embodiments of systems and methods for providing internal components for portable computing devices having a thin profile. More particularly, the present application describes internal components configured to fit within a relatively thin outer enclosure.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: March 12, 2019
    Assignee: Apple Inc.
    Inventors: Brett W. Degner, Christiaan A. Ligtenberg, Ron A. Hopkinson, Patrick Kessler, Bradley J. Hamel, Dinesh C. Mathew, John M. Brock, Keith J. Hendren, Peteris K. Augenbergs, Joss N. Giddings, Matthew C. Waldon, Cina Hazegh, Matthew P. Casebolt, Charles A. Schwalbach, Brandon S. Smith, William F. Leggett, Gavin J. Reid, Tom Tate, Gary Thomason
  • Patent number: 10217679
    Abstract: The present invention relates to a method of processing a solder masked carrier with electronic components, comprising the detection of a carrier related reference and the detection of a solder mask dependent reference, which detected reference are used for processing the position of the solder mask on the carrier. The invention also relates to an electronic component as produced with such method.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 26, 2019
    Assignee: Besi Netherlands B.V.
    Inventors: Jurgen Hendrikus Gerhardus Huisstede, Mark Hermans
  • Patent number: 10177026
    Abstract: A method of fabricating a semiconductor structure. The method includes forming a sacrificial gate structure, depositing a dielectric material, and implanting the dielectric material using a silicon cluster gas. The silicon cluster gas has two or more silicon atoms.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-wei Sung, Ming-Hui Li, Ming-Ying Tsai
  • Patent number: 10141196
    Abstract: The present application contemplates a method for manufacturing a power semiconductor device.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 27, 2018
    Assignee: ABB Schweiz AG
    Inventors: Sven Matthias, Charalampos Papadopoulos, Chiara Corvasce, Arnost Kopta
  • Patent number: 10128305
    Abstract: A semiconductor element is disclosed including a construction with electrode-dividing grooves, in which a dark current is smaller than in existing examples. A method of forming such grooves is also disclosed. In an embodiment, grooves, which electrically divide an electrode layer formed on the surface of a substrate, are formed with a V-shaped cross-sectional shape, groove side walls in the electrode layer, constituting the grooves, being sloping surfaces. An embodiment of the method of forming the grooves includes using a dicing blade having a blade distal end portion which is sharpened into a V-shape to cut a semiconductor wafer in which multiple patterns of semiconductor elements including an electrode layer on the surface of a substrate are formed, forming the grooves having a V-shaped cross-sectional shape which divide the electrode layer in each semiconductor element.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 13, 2018
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Sakari Kaneku, Yasuhiro Shuto, Akira Tachibana
  • Patent number: 10121672
    Abstract: There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 6, 2018
    Assignee: Disco Corporation
    Inventor: Koichi Shigematsu
  • Patent number: 10112256
    Abstract: An SiC wafer is produced from a single crystal SiC ingot by a method that includes forming a plurality of breakable layers constituting a separation surface in the SiC ingot, each breakable layer including a modified layer and cracks extending from the modified layer along a c-plane, and separating part of the SiC ingot along the separation surface as an interface to thereby produce the SiC wafer. In forming the separation surface, the energy density of a pulsed laser beam is set to an energy density not causing the formation of an upper damage layer above the breakable layer previously formed due to the reflection of the pulsed laser beam from the breakable layer and not causing the formation of a lower damage layer below the breakable layer previously formed due to the transmission of the pulsed laser beam through the breakable layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Disco Corporation
    Inventor: Kazuya Hirata
  • Patent number: 10115869
    Abstract: The invention relates to an optoelectronic semiconductor chip (10) comprising a carrier (2) and a semiconductor body (1) having an active layer (13) provided for generating electromagnetic radiation. Said carrier (2) has a first main surface (2A) facing the semiconductor body, a second main surface (2B) facing away from the semiconductor body, and a sidewall (2C) arranged between the first main surface and the second main surface. The carrier (2) has a structured region (21, 22, 23, 2C) for enlarging the total surface area of the sidewall, wherein the structured region has singulation traces. The invention also relates to an optoelectronic component (100) comprising such a semiconductor chip and a method for producing a plurality of such semiconductor chips are specified.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: October 30, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Mathias Kaempf, Simon Jerebic, Ingo Neudecker, Guenter Spath, Michael Huber
  • Patent number: 10103061
    Abstract: Disclosed herein is a processing method of a single-crystal substrate having a film formed on a front side or a back side thereof to divide the single-crystal substrate along a plurality of preset division lines. The method includes a film removing step of removing the film along the division lines, a shield tunnel forming step of applying a pulsed laser beam having a wavelength which permeates through the single-crystal substrate along the division lines to form shield tunnels, each including a fine hole and an amorphous region shielding the fine hole, in the single-crystal substrate along the division lines, and dividing step of exerting an external force on the single-crystal substrate to which the shield tunnel forming step is performed to divide the single-crystal substrate along the division lines.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 16, 2018
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Noboru Takeda, Takumi Shotokuji
  • Patent number: 10056285
    Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 10030174
    Abstract: A protective film-forming composite sheet 10 comprises a pressure sensitive adhesive sheet 16 in which a pressure sensitive adhesive layer 12 is provided on a base material 11, a protective film-forming film 13, and a release film 14. When ? (mN/25 mm) represents the maximum peel force between the protective film-forming film 13 and the release film 14; ? (mN/25 mm) represents the minimum peel force between the pressure sensitive adhesive sheet 16 and the protective film-forming film 13; and ? (mN/25 mm) represents the maximum peel force between the pressure sensitive adhesive sheet 16 and the protective film-forming film 13, the following relationships (1) to (3) hold for ?, ?, and ?; ??70??(1) ?/??0.50??(2) ??2000??(3).
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 24, 2018
    Assignee: LINTEC CORPORATION
    Inventors: Hiroyuki Yoneyama, Naoya Saiki