With Attachment To Temporary Support Or Carrier Patents (Class 438/464)
  • Patent number: 12165895
    Abstract: An apparatus for executing a direct transfer of a semiconductor device die from a first substrate to a second substrate. The apparatus includes a first substrate conveyance mechanism movable in two axes. A micro-adjustment mechanism is coupled with the first substrate conveyance mechanism and is configured to hold the first substrate and to make positional adjustments on a scale smaller than positional adjustments caused by the first substrate conveyance mechanism. The micro-adjustment mechanism includes a micro-adjustment actuator having a distal end and a first substrate holder frame that is movable via contact with the distal end of the micro-adjustment actuator. A second frame is configured to secure the second substrate such that a transfer surface is disposed facing the semiconductor device die disposed on a surface of the first substrate. A transfer mechanism is configured to press the semiconductor device die into contact with the transfer surface of the substrate.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: December 10, 2024
    Assignee: Cowles Semi, LLC
    Inventors: Andrew Huska, Justin Wendt, Luke Dupin, Cody Peterson
  • Patent number: 12155019
    Abstract: A light-emitting device comprises a substrate comprising a top surface and a sidewall; a semiconductor stack formed on the top surface of the substrate comprising a first semiconductor layer, an active layer and a second semiconductor layer; a dicing street surrounding the semiconductor stack and exposing the top surface of the substrate; a protective layer covering the semiconductor stack and the dicing street; a reflective layer comprising a Distributed Bragg Reflector structure and covering the protective layer; and a cap layer covering the reflective layer, wherein the reflective layer comprises an uneven portion adjacent to the sidewall of the substrate, and the uneven portion comprises an uneven thickness.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: November 26, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Ying Wang, Chih-Hao Chen, Chien-Chih Liao, Chao-Hsing Chen, Wu-Tsung Lo, Tsun-Kai Ko, Chen Ou
  • Patent number: 12148665
    Abstract: Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: November 19, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 12142499
    Abstract: A pickup apparatus for separating a semiconductor die adhered on an adhesive film therefrom includes a frame, an UV light emitting element, and a collector element. The frame is configurated to hold the adhesive film adhered with the semiconductor die thereon. The UV light emitting element is disposed inside the frame, where the adhesive film is disposed between the semiconductor die and the UV light emitting element. The collector element is disposed over the frame.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Patent number: 12131924
    Abstract: The present disclosure describes methods and systems for processing semiconductor wafers. A method for processing a wafer includes measuring one or more wafer characteristics of the wafer using a plurality of detectors. The wafer includes a device region and a perimeter region. The method also includes determining a wafer modification profile of the wafer based on the measured one or more wafer characteristics. The method further includes modifying a ring-shaped portion of the wafer within the perimeter region using the wafer modification profile. The modified ring-shaped portion has a penetration depth that is less than a thickness of the wafer. The method further includes performing a wafer thinning process on the wafer.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: October 29, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liquan Cai, Peng Chen, Houde Zhou
  • Patent number: 12128664
    Abstract: An affixing method includes a pressing step of pressing a tape against a wafer with a tape affixing roller and pressing the wafer against a suction table with the tape affixing roller, an evacuating step of evacuating a vacuum chamber that houses the suction table and the tape affixing roller therein to create a vacuum in the vacuum chamber, and an affixing step of affixing the tape to the wafer with the tape affixing roller by causing the tape affixing roller to roll on the tape while the tape affixing roller is pressing the wafer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 29, 2024
    Assignee: DISCO CORPORATION
    Inventors: Yohei Masuda, Ye Chen
  • Patent number: 12121993
    Abstract: A method of processing a plate-shaped workpiece includes a sheet affixing step of laying a thermocompression bonding sheet on a surface of the workpiece and heating and pressing the thermocompression bonding sheet against the workpiece to affix the thermocompression bonding sheet to the workpiece, a laser beam applying step of applying a laser beam having a wavelength absorbable by the workpiece to another surface of the workpiece along a projected dicing line established thereon, thereby processing the workpiece along the projected dicing line, and a sheet joining step of pressing the thermocompression bonding sheet while reheating the thermocompression bonding sheet to soften the same, so that the thermocompression bonding sheet is joined up by closing dividing grooves or through holes made in the thermocompression bonding sheet when the workpiece is processed in the laser beam applying step.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: October 22, 2024
    Assignee: DISCO CORPORATION
    Inventors: Masatoshi Nayuki, Satoshi Kumazawa, Keisuke Nishimoto
  • Patent number: 12100622
    Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: September 24, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 12094736
    Abstract: A device configured to receive a first carrier with a first receptacle; to guide a second carrier in a conveying direction with a second receptacle; to receive the first carrier with the first receptacle so that the components carried by it are oriented towards the second receptacle; to separate the components in response to information from a control unit; and convey the second carrier in its position relative to a placement position so that an electronic subassembly on the second carrier reaches the placement position. The second receptacle has a contact surface for the second carrier which is curved in the conveying direction of the second carrier and the second receptacle at least partially includes a second conveying device which occupies only part of the second receptacle transversely to the conveying direction of the second carrier.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 17, 2024
    Assignee: MUEHLBAUER GMBH & CO. KG
    Inventor: Marcel Freimuth
  • Patent number: 12077684
    Abstract: A temporary adhesive includes: a polar resin of 5 wt % to 50 wt %, a first solvent of 30 wt % to 90 wt %, and a second solvent of 5 wt % to 60 wt %, wherein the polar resin includes at least one selected from a group consisting of a phenoxy resin, a poly(ether-ether-ketone) resin, a polycarbonate resin, a modified epoxy resin, or a polyolefin resin with a modified polar group; the first solvent is used to dissolve the polar resin; and the second solvent is used to improve a leveling property of the temporary adhesive.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: September 3, 2024
    Assignee: PhiChem Corporation
    Inventors: Yaosen Wang, Xiaoyi Gao, Dongchen Ji
  • Patent number: 12068188
    Abstract: A component manufacturing method includes a step of obtaining a holding tool. The holding tool includes: a frame body having an opening; and a holding film placed on the frame body. The step is a step of placing the holding film on the frame body while stretching the holding film in at least three different directions or in all directions to the frame body. The holding film includes a base layer and a holding layer. The holding tool forming device includes: a mechanism that pushes a plain film from a base layer side to bring about a stretched state; a mechanism that fixes the plain film to the frame body such that the stretched state is maintained; and a mechanism that isolates an unnecessary portion from the plain film to obtain the holding film.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: August 20, 2024
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventor: Eiji Hayashishita
  • Patent number: 12060266
    Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: August 13, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Markus Bergmeister, Bernhard Goller, Daniel Pieber, Sokratis Sgouridis
  • Patent number: 11975519
    Abstract: Provided is a method of manufacturing plate-like members whereby shape defects in the plate-like members can be prevented to increase production yield and a laminate for use in the method of manufacturing plate-like members.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 7, 2024
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventors: Tomomichi Kunimoto, Hideki Asano
  • Patent number: 11938714
    Abstract: An electronic device may include a housing including a support member in an inner space thereof, at least one conductive pattern disposed on the support member, a cover member combined with at least a part of the housing, a first adhesive member disposed between the housing and the cover member to be overlapped at least in part with the at least one conductive pattern when the cover member is viewed from above, and a first masking film member attached to the first adhesive member and disposed between the first adhesive member and the at least one conductive pattern to be overlapped with the at least one conductive pattern when the cover member is viewed from above. A surface of the first masking film member facing the at least one conductive pattern may include a photosensitive adhesive layer containing a photo-initiator and having an adhesive force reduced or removed through irradiation of ultraviolet (UV) rays.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Daum Hwang, Sangin Baek
  • Patent number: 11915946
    Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nano structure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nano structure may be formed as the thickest of the nanostructures in the vertical stack.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11901184
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: February 13, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11901201
    Abstract: A semiconductor manufacturing apparatus includes: a sheet separation jig having contact with a rear surface of a sheet which is a surface of the sheet on a side opposite to a front surface of the sheet, wherein the sheet separation jig includes therein a plurality of support blocks each having a first suction hole formed for sucking the rear surface of the sheet and a single driving plate connected to the plurality of support blocks so that the plurality of support blocks can move in a first direction as a direction away from the sheet with a time difference, and the plurality of support blocks are disposed in the sheet separation jig along a second direction, as a direction of a separation of the semiconductor device from the sheet, intersecting the first direction.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: February 13, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shunichi Kawakami, Takaya Noguchi
  • Patent number: 11855064
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 26, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 11842926
    Abstract: This invention relates to a method of processing a substrate, having on one side a device area with a plurality of devices. The method includes attaching a first protective film to the one side of the substrate, so that at least a central area of a front surface of the first protective film is in direct contact with the one side of the substrate, and attaching a second protective film to the opposite side of the substrate. After attaching the second protective film, a laser beam is applied to the substrate from the opposite side of the substrate. The substrate and second protective film are transparent to the laser beam. The laser beam is applied to the substrate in a plurality of positions so as to form a plurality of modified regions in the substrate.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: December 12, 2023
    Assignee: DISCO CORPORATION
    Inventors: Kensuke Nagaoka, Yasuyoshi Yubira
  • Patent number: 11804397
    Abstract: A method includes transferring multiple discrete components from a first substrate to a second substrate, including illuminating multiple regions on a top surface of a dynamic release layer, the dynamic release layer adhering the multiple discrete components to the first substrate, each of the irradiated regions being aligned with a corresponding one of the discrete components. The illuminating induces a plastic deformation in each of the irradiated regions of the dynamic release layer. The plastic deformation causes at least some of the discrete components to be concurrently released from the first substrate.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: October 31, 2023
    Assignee: KULICKE & SOFFA NETHERLANDS B.V.
    Inventors: Val Marinov, Ronn Kliger, Matthew R. Semler
  • Patent number: 11798906
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-Jin Lee
  • Patent number: 11791183
    Abstract: A unit sorting system comprising: a net table for receiving units and a unit lifter for depositing said units on the net table; the net table having a first and second zone; wherein the unit lifter is arranged to engage a batch of units and then deposit a first half of the batch to the first zone and deposit a first half of the batch to the second zone.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 17, 2023
    Assignee: Rokko Systems Pte Ltd
    Inventors: Jong Jae Jung, Yun Suk Shin, Deok Chun Jang
  • Patent number: 11784093
    Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: October 10, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 11752576
    Abstract: A substrate processing system configured to process a substrate includes a modification layer forming apparatus configured to form a modification layer within the substrate along a boundary between a peripheral portion of the substrate to be removed and a central portion of the substrate; and a periphery removing apparatus configured to remove the peripheral portion starting from the modification layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 12, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hayato Tanoue
  • Patent number: 11756830
    Abstract: Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: September 12, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11756783
    Abstract: A method for creating at least one cavity in a semiconductor substrate including the steps of: (a) partially ablating the semiconductor substrate from the top side with a laser to form a trench in the semiconductor substrate surrounding a cross section of the semiconductor material having the desired shape, (b) machining the backside of the semiconductor substrate partially ablated in step (a) to reduce the semiconductor substrate to a final thickness that is equal to or less than the laser ablation depth to form a plug of semiconductor material unattached to a remainder of the semiconductor substrate; and (c) removing the plug of semiconductor material from the semiconductor substrate to form the at least one cavity with cross section of desired shape extending through the semiconductor substrate.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: September 12, 2023
    Assignee: HRL LABORATORIES, LLC
    Inventors: Eric Prophet, Joel Wong, Florian G. Herrault
  • Patent number: 11682569
    Abstract: A workpiece cutting method of cutting a workpiece along a plurality of crossing division lines formed on a front side of the workpiece, by using a cutting blade having a thickness gradually decreasing toward an outer circumference of the cutting blade. The workpiece cutting method includes a shape checking step of checking a shape of the cutting blade; a cut depth setting step of setting a cut depth by the cutting blade into the workpiece according to the shape checked in the shape checking step such that a width of a cut groove to be formed on the front side of the workpiece becomes a previously set value; and a cutting step of cutting the workpiece with the cut depth set in the cut depth setting step, by forcing the cutting blade into the workpiece from the front side thereof.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 20, 2023
    Assignee: DISCO CORPORATION
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 11664257
    Abstract: The present disclosure is directed to a wafer container including: a housing configured for transporting a plurality of wafers, wherein the plurality of wafers are stacked on a base of the housing in a first direction; a plurality of wafer separator rings; each of the wafer separator rings configured to encircle a wafer of the plurality of wafers in a second direction that is substantially perpendicular to the first direction, each of the wafer separator rings including a top surface and a bottom surface, defining a thickness there between extending in the first direction, which is about 0.3 mm-1.4 mm; and each of the wafer separator rings including an inner side wall and an outer side wall defined by an inner diameter and an outer diameter, respectively, in the second direction, wherein the inner diameter of the wafer separator ring is greater than 300 mm and configured to be spaced apart from the wafer it is encircling.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: May 30, 2023
    Assignee: INTEL CORPORATION
    Inventors: Varshalaxmi Bhatt Dhruvkumar, John Biggs, Shaw Fong Wong
  • Patent number: 11649383
    Abstract: An adhesive composition degradable by dielectric heating. The adhesive composition comprises a thermosetting polymer and a material sensitive to dielectric heating. The material sensitive to dielectric heating is selected from any one or more of hollow nanospheres, nanotubes, nanorods, nanofibres, nanosheets, graphene, graphene derivatives, nano/micro hybrids and mixtures of two or more nanoscale particles. The adhesive composition may be particularly useful in the assembly and disassembly of parts, particularly parts which have complicated and/or blocked joined surfaces. A method of joining at least two parts of an article together and a method of disassembling at least two parts of an article, using the adhesive composition are also provided. The adhesive composition may provide a reworkable nano-composite adhesive. The adhesive composition may be used to reversibly bond a biomedical or dental implant to a part of a human or animal body.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 16, 2023
    Assignee: UNIVERSITY OF LIMERICK
    Inventors: Bin Zhao, Conor McCarthy
  • Patent number: 11651978
    Abstract: A protective sheet application method for applying a protective sheet on a front surface of a substrate includes mounting the substrate on a support table in a vacuum chamber, mounting the protective sheet on the substrate to separate a space in the vacuum chamber into a first compartment and a second compartment, depressurizing the first compartment to a predetermined air pressure and also depressurizing the second compartment, opening the depressurized second compartment to the atmosphere to bring the protective sheet into close contact with the substrate by a predetermined force, and opening the depressurized first compartment to the atmosphere to separate the lower housing and the upper housing from each other. A protective sheet application apparatus for applying the protective sheet on the front surface of the substrate includes the vacuum chamber.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 16, 2023
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11605659
    Abstract: According to an aspect, a sensor packaging structure includes a sensor die having a first surface and a second surface opposite the first surface, where the sensor die defines a sensor edge disposed between the first surface and the second surface. The sensor packaging structure includes a bonding material having a first surface and a second surface opposite the second surface, where the bonding material defines a bonding material edge disposed between the first surface of the bonding material and the second surface of the bonding material. The sensor packaging structure includes a transparent material, where the bonding material couples the sensor die to the transparent material. The sealing material is disposed on an interface between the sensor die and the bonding material, and at least one of a portion of the sensor edge or a portion of the bonding material edge.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 14, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Weng-Jin Wu
  • Patent number: 11587833
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: February 21, 2023
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11587832
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyolefin sheet, pushing up each device chip through the polyolefin sheet, and picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 21, 2023
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11557715
    Abstract: A method for manufacturing a film, notably monocrystalline, on a flexible sheet, comprises the following steps: providing a donor substrate, forming an embrittlement zone in the donor substrate so as to delimit the film, forming the flexible sheet by deposition over the surface of the film, and detaching the donor substrate along the embrittlement zone so as to transfer the film onto the flexible sheet.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 17, 2023
    Assignee: Soitec
    Inventors: Bruno Ghyselen, Jean-Marc Bethoux
  • Patent number: 11551943
    Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 10, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tetsuhiro Iwai
  • Patent number: 11538711
    Abstract: Methods and apparatus for pre-treating semiconductor wafers before edge trimming to enhance wafer edge quality prior to thinning the semiconductor wafers from an initial thickness, and increasing yield post-thinning of the pre-treated, edge trimmed semiconductor wafers.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jing-Cheng Lin
  • Patent number: 11527440
    Abstract: Disclosed is a method for separating a plate into multiple individual detached components or cutting the plate into chips. The back end process for a plate includes providing a substrate; attaching the plate to the substrate using a sacrificial layer that is made of materials that in a solid state at ambient temperature and ambient pressure, and having a transformation temperature into one or more gaseous compounds at ambient pressure of between 80° C. and 600° C.; and separating the plate attached on the substrate into a plurality of plate portions; increasing temperature and/or reducing surrounding pressure to transform the sacrificial layer into one or more gaseous compounds.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 13, 2022
    Assignee: OMMIC
    Inventor: Peter Michael Frijlink
  • Patent number: 11527441
    Abstract: A method for producing a detachment area in a solid body in described. The solid body has a crystal lattice and is at least partially transparent to laser beams emitted by a laser. The method includes: modifying the crystal lattice of the solid by a laser beam, wherein the laser beam penetrates through a main surface of a detachable solid portion of the solid body, wherein a plurality of modifications are produced in the crystal lattice, wherein the modification are formed in a plane parallel to the main surface and at a distance from one another, wherein as a result of the modifications, the crystal lattice cracks the regions surrounding the modifications sub-critically in at least the one portion, and wherein the subcritical cracks are arranged in a plane parallel to the main surface.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: December 13, 2022
    Assignee: Siltectra GmbH
    Inventors: Christian Beyer, Jan Richter
  • Patent number: 11508598
    Abstract: A frame jig for manufacturing a semiconductor package includes a frame body of a rectangular shape attached to a package structure of a panel shape, wherein the frame body comprises polyphenylene sulfide.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungwan Kim, Hyunsuk Yang
  • Patent number: 11476128
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor device package. The method includes: (a) disposing a support structure on a first substrate; (b) electrically connecting a first electronic component on the first substrate, wherein a portion of the first electronic component is separated from the first substrate by the support structure; (c) heating the semiconductor device package; and (d) removing the support structure.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: October 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, An-Ping Chien
  • Patent number: 11472168
    Abstract: A laminated body for polishing a back surface of a wafer, the laminated body including an intermediate layer that is disposed between a support and a circuit surface of the wafer and peelably adheres to the support and the circuit surface, wherein the intermediate layer includes an adhesion layer in contact with the wafer and a peeling layer in contact with the support, and the peeling layer contains a novolac resin that absorbs light with a wavelength of 190 nm to 600 nm incident through the support, resulting in modification. The light transmittance of the peeling layer at a wavelength range of 190 nm to 600 nm may be 1 to 90%. The modification caused by absorption of light may be photodecomposition of the novolac resin.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 18, 2022
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Hiroshi Ogino, Hirokazu Nishimaki, Ryo Karasawa, Tetsuya Shinjo, Satoshi Kamibayashi, Shunsuke Moriya, Takahisa Okuno
  • Patent number: 11463569
    Abstract: A structural component includes a middle frame, a glass cover, and a touch control film. The glass cover and the touch control film are disposed in a stacked manner. The touch control film is disposed on a surface that is of the glass cover and that faces the middle frame, and a side edge of the touch control film and a side edge of the glass cover do not overlap completely. The glass cover is bonded using the first bonding adhesive, and the touch control film is bonded using the second bonding adhesive. The first bonding adhesive is bonded to an edge of the glass cover, and the bonding force of the first bonding adhesive is greater than the bonding force of the second bonding adhesive.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 4, 2022
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Renwei Guo, Xixiang Dai
  • Patent number: 11462433
    Abstract: An apparatus includes a transfer element that is disposed adjacent the wafer tape. A tip end of the transfer element has a footprint sized so as to span across a group of dies on the wafer tape. An actuator is connected to the transfer element to move the transfer element to a die transfer position at which the transfer element presses on the wafer tape to press the group of dies into contact with a circuit trace on the product substrate.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: October 4, 2022
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andy Huska
  • Patent number: 11462575
    Abstract: The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 4, 2022
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Brian Cobb, Neil Davies
  • Patent number: 11456214
    Abstract: A method of processing a workpiece includes a thermosetting step of heating an area of an expandable sheet around a workpiece to a predetermined temperature or higher and thereafter cooling the heated area of the expandable sheet to make the area harder than before the area has been heated, and after the thermosetting step, an expanding step of expanding the area of the expandable sheet around the workpiece in planar directions to divide the workpiece into chips or to increase distances between the adjacent chips.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 27, 2022
    Assignee: DISCO CORPORATION
    Inventor: Yoshinobu Saito
  • Patent number: 11430677
    Abstract: Wafer taping apparatuses and methods are provided for determining whether taping defects are present on a semiconductor wafer, based on image information acquired by an imaging device. In some embodiments, a method includes applying an adhesive tape on a surface of a semiconductor wafer. An imaging device acquires image information associated with the adhesive tape on the semiconductor wafer. The presence or absence of taping defects is determined by defect recognition circuitry based on the acquired image information.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yi Lee, Wen-Kuei Liu
  • Patent number: 11417576
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 11342226
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 24, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Karthik Balakrishnan, Jungrae Park, Sriskantharajah Thirunavukarasu, Eng Sheng Peh
  • Patent number: 11335564
    Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 17, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Shogo Okita
  • Patent number: 11304346
    Abstract: A method for shielding a system-in-package (SIP) assembly from electromagnetic interference (EMI) includes laminating a pre-form EMI shielding film onto the assembly in a single lamination process. The EMI shielding film may be moldable in a vacuum lamination process to cover the SIP assembly and to substantially fill trenches formed in the assembly between adjacent component modules. The SIP assembly is accordingly shielded from EMI through the application of a single EMI shielding film.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Henkel AG & Co. KGaA
    Inventors: Xuan Hong, Daniel Maslyk, Qizhuo Zhuo, Juliet Grace Sanchez