With Attachment To Temporary Support Or Carrier Patents (Class 438/464)
  • Patent number: 10727219
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 10720355
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 21, 2020
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10672630
    Abstract: Described herein is a method and system for dual stretching of wafers to create isolated segmented chip scale packages. A wafer having an array of light-emitting diodes (LEDs) is scribed into LED segments, where each LED segment includes a predetermined number of LEDs. The scribed wafer is placed on a stretchable substrate or tape. The tape is stretched and a layer of optically material is placed in the separation gaps. The stretched wafer is scribed on a LED level. The tape is stretched and another layer of optically opaque material is placed in the separation gaps. The same or different optically opaque material can be used for the layers. The two layers of optically opaque material are formed to provide electrical connectivity between the LEDs in each LED segment. In an implementation, each segment or LED is individually addressable.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 2, 2020
    Assignee: Lumileds LLC
    Inventors: Arjen Gerben Van der Sijde, Nicola Bettina Pfeffer, Brendan Moran
  • Patent number: 10668595
    Abstract: A method of using a laminated dressing board is provided. In the laminated dressing board, a shape adjustment dressing layer containing first abrasive grains and used for shape adjustment of a cutting blade and a setting dressing layer containing second abrasive grains and used for setting of the shape-adjusted cutting blade are laminated. The method includes a holding step of holding the shape adjustment dressing layer side of the laminated dressing board by a chuck table, a setting dressing step of causing the cutting blade to cut into the laminated dressing board from the setting dressing layer side to form a first groove in the setting dressing layer, and a shape adjustment dressing step of causing the cutting blade to cut into the bottom of the first groove along the first groove to form a second groove in the shape adjustment dressing layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 2, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 10665494
    Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: May 26, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Niranjan Kumar, Seshadri Ramaswami, Shay Assaf, Amikam Sade, Andy Constant, Maureen Breiling
  • Patent number: 10599038
    Abstract: Provided are a rinsing liquid which is used for rinsing a resist film obtained from an actinic ray-sensitive or radiation-sensitive composition and includes a hydrocarbon-based solvent having a branched alkyl group. The hydrocarbon-based solvent having a branched alkyl group contains at least one of isodecane or isododecane.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 24, 2020
    Assignee: FUJIFILM Corporation
    Inventors: Hideaki Tsubaki, Toru Tsuchihashi, Wataru Nihashi
  • Patent number: 10580697
    Abstract: There is provided a dividing method for dividing a plate-shaped workpiece. The dividing method includes: a starting point region forming step of forming a starting point region serving as a starting point of division along a planned dividing line set on the workpiece; a heating step of heating the workpiece after performing the starting point region forming step; a cooling step of cooling the workpiece after performing the heating step; a dividing step of dividing the workpiece along the starting point region by applying a force to the workpiece after performing the cooling step; and a sheet affixing step of affixing an expanding sheet to the workpiece before performing the dividing step; the dividing step applying the force to the workpiece by expanding the expanding sheet.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: March 3, 2020
    Assignee: DISCO CORPORATION
    Inventor: Nao Hattori
  • Patent number: 10566319
    Abstract: A semiconductor device die transfer apparatus includes a first frame to hold a wafer tape having a plurality of semiconductor device die disposed on a side of the wafer tape and a second frame to secure a product substrate having a circuit trace thereon. The second frame is configured to secure the product substrate such that the circuit trace is disposed facing the plurality of semiconductor device die on the wafer tape. Additionally, a rotary transfer collet is disposed between the wafer tape and the product substrate. The rotary transfer collet has a rotational axis allowing rotation from a first position facing the wafer tape to pick a die of the plurality of semiconductor device die to a second position facing the circuit trace on the product substrate to release the die, thereby applying the die directly on the product substrate during a transfer operation.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 18, 2020
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Clinton Adams, Sean Kupcow, Andrew Huska
  • Patent number: 10559487
    Abstract: A wafer is divided at division starting points along division lines to form a predetermined gap between adjacent chips. Next, that area of a tape to which the wafer is adhered is suction held by a table, after which the table and a ring frame holding section are relatively moved further away from each other to expand the tape in a ring shape between an outer periphery of the wafer and an inner periphery of a ring frame. Thereafter, the table and the ring frame holding section are relatively moved closer to each other to slacken the ring-shaped tape, and the ring-shaped tape is heated by a heater, to heat shrink the tape and to maintain the predetermined gap between the adjacent chips.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: February 11, 2020
    Assignee: DISCO CORPORATION
    Inventor: Atsushi Ueki
  • Patent number: 10529623
    Abstract: The method of manufacturing a light emitting element includes: temporarily fixing a semiconductor layer of a wafer including a base member and the semiconductor layer to a support base member by a double-sided tape having a loss tangent adapted to be increased by heating from an ordinary temperature; forming a cleavage starting portion for dividing the wafer into a plurality of light emitting elements at an ordinary temperature in the wafer; and singulating the wafer into a plurality of light emitting elements on the support base member while the double-sided tape is heated.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 7, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Shuichi Iwamoto, Shohei Sadamoto, Shinya Mitsuhashi
  • Patent number: 10513011
    Abstract: A noncontact support system includes a table with a port layer having a pattern of interspersed pressure ports and vacuum ports. A pressure conduit layer includes a grid pattern of pressure conduits, connectable to a pressure source, each of the pressure ports being located on an axis passing through an intersection of at least two of the pressure conduits and substantially orthogonal to the grid pattern of pressure conduits. A vacuum conduit layer includes a grid pattern of vacuum conduits, connectable to a suction source, each of the vacuum ports being located on an axis passing through an intersection of at least two of the vacuum conduits and substantially orthogonal to the grid pattern of vacuum conduits. The grid pattern of vacuum conduits is laterally offset from the grid pattern of pressure conduits such that each intersection of pressure conduits is laterally offset from all intersections of the vacuum conduits.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 24, 2019
    Assignee: Core Flow Ltd.
    Inventors: Yaacov Legerbaum, Ronen Lautman, Leonid Nosovsky, Boaz Nishri
  • Patent number: 10504804
    Abstract: A laser processing method includes irradiating a laser light into a substrate along a cutting line to form a laser-scribed layer within the substrate, irradiating an X-ray onto a first surface of the substrate along the cutting line, obtaining an image of a diffracted X-ray from the substrate, and determining whether or not the laser-scribed layer is formed along the cutting line, based on analysis of the obtained image of the diffracted X-ray.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Yeol Yang, Hyung-Su Son, Hae-Gu Lee, Dong-Su Han
  • Patent number: 10475842
    Abstract: The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Chan Kim, Yong Ho Baek
  • Patent number: 10470317
    Abstract: A method for manufacturing a circuit board includes: forming a first adhesive layer on a first surface of a vibration unit, in which the vibration unit includes at least one piezoelectric material layer; forming a first stacking structure on the first adhesive layer; and applying a voltage to the at least one piezoelectric material layer to cause the at least one piezoelectric material layer to vibrate, such that the first stacking structure is separate from the vibration unit.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: November 5, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Hsiang-Hung Huang, Chi-Min Chang
  • Patent number: 10438792
    Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 8, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 10431515
    Abstract: The present disclosure describes apparatuses and techniques for self-aligning integrated circuit (IC) dies. In some aspects, a hydrophobic material is deposited on a surface of a substrate to form a pattern on the surface of the substrate. The pattern may expose areas of the substrate surface for placement of IC dies. A water-based solution is then applied to the exposed areas such that droplets form on the exposed areas of the substrate surface. IC dies are placed on the droplets of the water-based solution, which can cause the IC dies to align with the exposed areas of the substrate surface. The droplets are then caused to evaporate such that the IC dies settle on the exposed areas of the substrate surface.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: October 1, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Long-Ching Wang, Marc Jacobs
  • Patent number: 10388526
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer
  • Patent number: 10381254
    Abstract: A wafer debonding and cleaning apparatus comprises a wafer debonding module configured to separate a semiconductor wafer from a carrier wafer. The wafer debonding and cleaning apparatus also comprises a first wafer cleaning module configured perform a first cleaning process to clean a surface of the semiconductor wafer. The wafer debonding and cleaning apparatus further comprises an automatic wafer handling module configured to transfer the semiconductor wafer from one of the wafer debonding module or the first wafer cleaning module to the other of the wafer debonding module or the first wafer cleaning module. The semiconductor wafer has a thickness ranging from about 0.20 ?m to about 3 mm.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chih Chiou, Yu-Liang Lin, Hung-Jung Tu
  • Patent number: 10366923
    Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces and a layer of material disposed along the second major surface. The method includes placing the wafer onto a carrier substrate and etching through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material. The method includes providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material. The method includes placing the wafer and the carrier substrate onto the support structure, and, in one embodiment, applying pressure and mechanical vibrations to the wafer to separate the layer of material in the singulation lines.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: July 30, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 10367926
    Abstract: A housing assembly for a terminal and a terminal are provided. The housing assembly includes a housing, an antenna radiator and a ferrite. The antenna radiator is positioned at an outer face of the housing, and has a first orthographic projection region on the outer face. The ferrite is arranged on an inner face of the housing, and has a second orthographic projection region on the outer face. The first orthographic projection region is located in the second orthographic projection region.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: July 30, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Qing Wu, Yizhou Luo, Liang Gu
  • Patent number: 10350711
    Abstract: A semiconductor device is provided with a semiconductor substrate. A semiconductor element is provided on a first face of the semiconductor substrate. An energy absorbing film is provided on the first face, to absorb optical energy to generate heat. A first insulation film is provided on the semiconductor element and on the energy absorbing film. A second insulation film is provided on a second face of the semiconductor substrate, the second face being opposite to the first face. A first modified layer is provided on a side face of the semiconductor substrate, the side face being located between an outer edge of the first face and an outer edge of the second face. A second modified layer is provided on the side face between the energy absorbing film and the first modified layer. A cleavage face is provided on the side face between the first and second modified layers.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Fujita, Akira Tomono, Takanobu Ono
  • Patent number: 10312218
    Abstract: A method for binding a micro device to a substrate is provided. The method includes: locally showering a gas on a portion of the substrate, wherein the gas has a water vapor pressure higher than an ambient water vapor pressure; and placing the micro device over the portion of the substrate after a part of water in the gas is condensed to form a liquid layer on the portion of the substrate and contacting the micro device with the liquid layer, so that the micro device is gripped by a capillary force produced by the liquid layer and is substantially held in a position within a controllable region on the substrate.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 4, 2019
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10283388
    Abstract: A detaping machine is adapted for removing a tape from a frame, the tape includes a wafer mounting area and a periphery area surrounding the wafer mounting area. The detaping machine includes a carrier and a detaping module. The carrier is for supporting the tape and the frame. The detaping module includes an elastic pressing device and a detaping head, wherein the periphery area of the tape is adapted to be pressed by the elastic pressing device, and the wafer mounting area of the tape is adapted to be pressed by the detaping head. A detaping method is further provided.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Wen-Chin Kan, Yang-Ann Chu
  • Patent number: 10263111
    Abstract: A FinFET and a method for manufacturing the same are provided. The method includes: patterning a semiconductor substrate to form a ridge; performing ion implantation such that a doped punch-through-stopper layer is formed in the ridge and a semiconductor fin is formed by a portion of the semiconductor substrate disposed above the doped punch-through-stopper layer; forming a gate stack intersecting the semiconductor fin, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin; forming a gate spacer surrounding the gate conductor; and forming source and drain regions in portions of the semiconductor fin at opposite sides of the gate stack.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 16, 2019
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Miao Xu
  • Patent number: 10236266
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou, Katsumi Takano, Mitsuru Hiroshima
  • Patent number: 10192768
    Abstract: A semiconductor processing sheet, the sheet comprising a base material and a pressure sensitive adhesive layer laminated on at least one surface of the base material, the pressure sensitive adhesive layer being formed of a pressure sensitive adhesive composition, the pressure sensitive adhesive composition containing a polymer having a salt and an energy ray curable group and an energy ray curable pressure sensitive adhesive component (excluding the above polymer). The semiconductor processing sheet can suppress contamination of an adherent at the time of peeling after energy ray irradiation while exhibiting a sufficient antistatic property.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 29, 2019
    Assignee: LINTEC CORPORATION
    Inventors: Shigeyuki Yamashita, Akinori Sato
  • Patent number: 10186495
    Abstract: A film for semiconductor device includes a base material and an adhesive layer formed over the base material. The film is divided into an adhesive area and an expansion area. The elasticity modulus of the expansion area is less than that of the adhesive area. When tensile strength is applied on the film, the expansion area is more prone to tensile deformation than the adhesive area. When this film is used for film expansion of semiconductor devices, the devices can be evenly and orderly arranged on the film.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 22, 2019
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Chen-ke Hsu, Junpeng Shi, Xiaojuan Shao, Kechuang Lin
  • Patent number: 10163807
    Abstract: A method includes forming an alignment pattern over an insulating layer formed over a carrier. A die is mounted over the carrier and encapsulated. Connectors are formed and the structure is attached to a debond tape. The carrier is removed. A cutting device is aligned to a backside of the insulating layer using the alignment pattern. The first insulating layer and encapsulant are cut from the backside of the insulating layer. Another method includes scanning a backside of a packages structure for an alignment pattern in a first package area of the packages structure. A cutting device is aligned to a cut-line in a non-package area of the packages structure based on the alignment pattern and packages are singulated. An InFO package includes an insulating layer on the backside, the insulating layer having a laser marking thereon. The InFO package also includes an alignment pattern proximate to the insulating layer.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Der-Chyang Yeh, Hsien-Wei Chen, Shih-Peng Tai
  • Patent number: 10157766
    Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Un-Byoung Kang, Joonsik Sohn, Jung-Seok Ahn, Chungsun Lee, Taeje Cho
  • Patent number: 10128326
    Abstract: A resistor comprises a substrate, an upper ohmic region disposed on a selective one of an upper surface and a lower surface of the substrate and a lower ohmic region disposed on the other one of the upper surface and the lower surface of the substrate. An upper metal conducting layer overlies on the substrate and the upper ohmic region, and a lower metal conducting layer overlies on the lower ohmic region. When the upper and lower metal conducting layers are electrified, the upper ohmic region and the lower ohmic region are electrically connected, and a contact interface between the substrate and the upper metal conducting layer forms an enlarged depletion region to block electrical conduction therebetween. As a result, a resistance value of the resistor is increased when an applied voltage on the resistor is increased.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: November 13, 2018
    Inventor: Chung Lin Wang
  • Patent number: 10049933
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 14, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Akihiro Itou, Katsumi Takano, Mitsuru Hiroshima
  • Patent number: 10037891
    Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 31, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai
  • Patent number: 9893222
    Abstract: Solar cells having a plurality of sub-cells coupled by metallization structures, and singulation approaches to forming solar cells having a plurality of sub-cells coupled by metallization structures, are described. In an example, a solar cell, includes a plurality of sub-cells, each of the sub-cells having a singulated and physically separated semiconductor substrate portion. Adjacent ones of the singulated and physically separated semiconductor substrate portions have a groove there between. The solar cell also includes a monolithic metallization structure. A portion of the monolithic metallization structure couples ones of the plurality of sub-cells. The groove between adjacent ones of the singulated and physically separated semiconductor substrate portions exposes a portion of the monolithic metallization structure.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 13, 2018
    Assignee: SunPower Corporation
    Inventors: Gabriel Harley, Michael Morse, Peter John Cousins
  • Patent number: 9880408
    Abstract: A substrate inspection device and method are disclosed. The substrate inspection device includes a conveyance stage for carrying the substrate on its surface; a region scanning camera located at a first side of the conveyance stage, provided to be opposite to the surface, and configured for inspecting standard specification of the substrate; a line scanning camera located at the first side of the conveyance stage, provided to be opposite to the surface, and configured for inspecting edge line and size of the substrate; and a light source located at a second side of the conveyance stage opposite to the first side, configured for irradiating light rays onto the substrate, so as to be utilized by the region scanning camera and the line scanning camera for inspecting the substrate.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: January 30, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yongjin Lee, Unsub Lee, Tae Hyuck Yoon
  • Patent number: 9780068
    Abstract: An adhesive composition for a pre-applied underfill sealant comprising: (a) a radical polymerizable monomer having one or more functional groups selected from the group consisting of vinyl group, maleimide group, acryloyl group, methacryloyl group and allyl group, (b) a polymer having a polar group, (c) a filler, and (d) a thermal radical initiator.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 3, 2017
    Assignees: HENKEL AG & CO. KGAA, HENKEL IP & HOLDING GMBH
    Inventors: Sugiura Yoko, Horiguchi Yusuke, Mieko Sano, Gina Hoang
  • Patent number: 9773689
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. A support structure is used to heat and/or cool at least the first carrier-substrate while the localized pressure is applied.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: September 26, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 9768049
    Abstract: A method for processing a wafer having a device region and a peripheral surplus region surrounding the device region on a front surface thereof. The method includes: preparing a support plate including a base plate in which a recess is formed in a front surface region corresponding to the device region and an annular groove is formed in a region corresponding to the peripheral surplus region and a soft member is packed in the recess of the base plate; injecting an adhesive into the annular groove of the support plate; sticking the wafer onto the support plate with the adhesive such that the device region abuts against the soft member; holding the wafer with intermediary of the support plate and performing processing on the wafer; and making a cutting blade cut into a region corresponding to the annular groove of the support plate to remove the adhesive.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 19, 2017
    Assignee: Disco Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 9768050
    Abstract: It is an object of the present invention to provide a film for semiconductor back surface having reworkability, and an application of the film. A film for semiconductor back surface has: an adhering strength at 70° C. of 7 N/10 mm or less to a wafer before the film is thermally cured; and a rupture elongation at 25° C. of 700% or less. The film for semiconductor back surface preferably has a degree of swelling due to ethanol of 1% by weight or more. The film for semiconductor back surface preferably contains an acrylic resin.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Ryuichi Kimura
  • Patent number: 9744983
    Abstract: A steering column assembly includes a jacket assembly, a mounting bracket, and a first telescope guide. The jacket assembly defines a first guide slot. The mounting bracket is disposed on the jacket assembly and has a first portion disposed opposite a second portion and a third portion extending between the first portion and the second portion. The first portion has a first rail received within the first guide slot. The first telescope guide is disposed between the first guide slot and the first rail.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 29, 2017
    Assignee: STEERING SOLUTIONS IP HOLDING CORPORATION
    Inventors: Scott A. Stinebring, Terry E. Burkhard, Robert D. Maida
  • Patent number: 9735349
    Abstract: In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: August 15, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Chul Park, Byoung-Jae Bae, Shin-Jae Kang, Young-Seok Choi
  • Patent number: 9653412
    Abstract: On a first wafer surface of a semiconductor wafer, a projection-depression shape is formed. On the first wafer surface, a resin member is so formed to have a resin outer peripheral end positioned away from a wafer outer peripheral end and expose the wafer outer peripheral end. By partially removing the semiconductor wafer, on a second wafer surface of the semiconductor wafer, formed is a recessed shape having a recessed-portion outer peripheral end positioned 0.5 mm or more inside from the resin outer peripheral end. After performing a processing on the second wafer surface, the resin member is removed.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 16, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunari Nakata
  • Patent number: 9653369
    Abstract: It is an object to provide a power semiconductor module having a case shared for base plates of different sizes and having a high-stability base plate. The power semiconductor module according to the present invention includes: a base plate; an insulating substrate disposed on a first main surface of the base plate; a semiconductor chip disposed on an insulating substrate; a case for enclosing the base plate except a second main surface of the base plate facing the first main surface, the insulating substrate, and the semiconductor chip; and a spacer provided between the outer periphery of the base plate and the inner periphery of the case and in contact with both. The spacer has a bonding surface with a side surface of the base plate and the first main surface in the contact with the outer periphery of the base plate.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 16, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshitaka Kimura, Rei Yoneyama, Ryo Goto, Akihiko Yamashita
  • Patent number: 9633887
    Abstract: A workpiece cutting method is provided. The workpiece cutting method includes an attaching step of attaching an adhesive tape to the front side or back side of a workpiece, an applying step of applying a liquid resin to the front side or back side of a support member, a pressing step of superimposing the workpiece on the support member in the condition where the liquid resin and the adhesive tape come into contact with each other, and then pressing the workpiece or the support member, a fixing step of curing the liquid resin to thereby fix the workpiece to the support member, and a cutting step of cutting the workpiece fixed to the support member by using a cutting blade.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 25, 2017
    Assignee: DISCO CORPORATION
    Inventors: Takashi Fukazawa, Hiroshi Onodera
  • Patent number: 9562172
    Abstract: An object of the present invention is to provide a photocurable sheet-type adhesive composition for optical use, which is used for bonding cover glass and a touch panel, a touch panel and a display module, or the like, and has high appearance reliability and storage stability even under high temperature and high humidity. The present invention is a photocurable sheet-shape adhesive for optical use, which contains the following components (A) to (D): (A) 100 parts by mass of a urethane (meth)acrylate oligomer having a weight average molecular weight of 20,000 to 100,000; (B) 3 to 70 parts by mass of a phenoxy resin having a glass transition temperature of 50 to 120° C.; (C) 0.1 to 10 parts by mass of a photopolymerization initiator; and (D) 1 to 50 parts by mass of a (meth)acrylate monomer which has 8 to 30 repeated blocks having an ether linkage in the molecule and containing at least one (meth)acryloyl group in the molecule.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: February 7, 2017
    Assignee: THREE BOND FINE CHEMICAL CO., LTD.
    Inventors: Yoshiaki Koga, Yoshihide Arai, Takashi Nemoto
  • Patent number: 9531154
    Abstract: In an optical device wafer, an optical device layer is formed over a front surface of an epitaxy substrate with the intermediary of a buffer layer composed of a Ga compound containing Ga. After a transfer substrate is joined to the optical device layer of the optical device wafer, a separation layer is formed at a boundary surface between the epitaxy substrate and the buffer layer by performing irradiation with a pulsed laser beam having such a wavelength as to be transmitted through the epitaxy substrate and be absorbed by the buffer layer from a back surface side of the epitaxy substrate. Thereafter, an ultrasonic horn that oscillates ultrasonic vibration is brought into contact with an outer circumferential part of the epitaxy substrate to vibrate the epitaxy substrate, and the epitaxy substrate is separated from the transfer substrate to transfer the optical device layer to the transfer substrate.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 27, 2016
    Assignee: DISCO CORPORATION
    Inventor: Tasuku Koyanagi
  • Patent number: 9515171
    Abstract: Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps of: forming fin masks on a SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins. Implementations with a bulk substrate, as well as the resulting devices, are also provided.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Philip J. Oldiges
  • Patent number: 9472438
    Abstract: A wafer processing laminate, a wafer processing member, a temporary adhering material for processing wafer, and a method for manufacturing a thin wafer using the same. The wafer processing laminate includes a support, a temporary adhesive material layer formed thereon and a wafer laminated on the temporary adhesive material layer, where the wafer has a circuit-forming front surface and a back surface to be processed. The temporary adhesive material layer includes a first temporary adhesive layer of a thermoplastic organopolysiloxane polymer layer (A) releasably adhered on a surface of the wafer, a second temporary adhesive layer of a radiation curable polymer layer (B) laminated on the first temporary adhesive layer, and a third temporary adhesive layer of a thermoplastic organopolysiloxane polymer layer (A?) laminated on the second temporary adhesive layer and releasably adhered to the support.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: October 18, 2016
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Kazunori Kondo, Hideto Kato, Michihiro Sugo, Shohei Tagami, Hiroyuki Yasuda
  • Patent number: 9431263
    Abstract: A plasma processing method to a substrate includes a first step of mounting a transfer carrier holding the substrate on a stage which is cooled and provided within a processing chamber; a second step of relatively moving the stage and a cover provided above the stage to cover a holding sheet and an annular frame of the transfer carrier with the substrate exposed from a window part formed at the cover, a third step of carrying out plasma processing on the substrate, a fourth step of cooling the cover, and a fifth step of unloading the transfer carrier holding the substrate from the processing chamber.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 30, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Noriyuki Matsubara, Mitsuru Hiroshima
  • Patent number: 9368404
    Abstract: The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a first surface and a second surface wherein the second surface is opposed to the first surface. A mask layer is provided on the first surface of the substrate and a thin film layer is provided on the second surface of the substrate. The first surface of the substrate is diced through the mask layer to expose the thin film layer on the second surface of the substrate. A fluid from a fluid jet is applied to the thin film layer on the second surface of the substrate after the thin film layer has been exposed by the dicing step.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: June 14, 2016
    Assignee: Plasma-Therm LLC
    Inventors: Peter Falvo, Linnell Martinez, David Pays-Volard, Rich Gauldin, Russell Westerman
  • Patent number: 9362105
    Abstract: A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 7, 2016
    Assignee: Henkel IP & Holding GmbH
    Inventors: Gina Hoang, YounSang Kim, Rose Guino