With Attachment To Temporary Support Or Carrier Patents (Class 438/464)
  • Patent number: 11557715
    Abstract: A method for manufacturing a film, notably monocrystalline, on a flexible sheet, comprises the following steps: providing a donor substrate, forming an embrittlement zone in the donor substrate so as to delimit the film, forming the flexible sheet by deposition over the surface of the film, and detaching the donor substrate along the embrittlement zone so as to transfer the film onto the flexible sheet.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 17, 2023
    Assignee: Soitec
    Inventors: Bruno Ghyselen, Jean-Marc Bethoux
  • Patent number: 11551943
    Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 10, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tetsuhiro Iwai
  • Patent number: 11538711
    Abstract: Methods and apparatus for pre-treating semiconductor wafers before edge trimming to enhance wafer edge quality prior to thinning the semiconductor wafers from an initial thickness, and increasing yield post-thinning of the pre-treated, edge trimmed semiconductor wafers.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jing-Cheng Lin
  • Patent number: 11527440
    Abstract: Disclosed is a method for separating a plate into multiple individual detached components or cutting the plate into chips. The back end process for a plate includes providing a substrate; attaching the plate to the substrate using a sacrificial layer that is made of materials that in a solid state at ambient temperature and ambient pressure, and having a transformation temperature into one or more gaseous compounds at ambient pressure of between 80° C. and 600° C.; and separating the plate attached on the substrate into a plurality of plate portions; increasing temperature and/or reducing surrounding pressure to transform the sacrificial layer into one or more gaseous compounds.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 13, 2022
    Assignee: OMMIC
    Inventor: Peter Michael Frijlink
  • Patent number: 11527441
    Abstract: A method for producing a detachment area in a solid body in described. The solid body has a crystal lattice and is at least partially transparent to laser beams emitted by a laser. The method includes: modifying the crystal lattice of the solid by a laser beam, wherein the laser beam penetrates through a main surface of a detachable solid portion of the solid body, wherein a plurality of modifications are produced in the crystal lattice, wherein the modification are formed in a plane parallel to the main surface and at a distance from one another, wherein as a result of the modifications, the crystal lattice cracks the regions surrounding the modifications sub-critically in at least the one portion, and wherein the subcritical cracks are arranged in a plane parallel to the main surface.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: December 13, 2022
    Assignee: Siltectra GmbH
    Inventors: Christian Beyer, Jan Richter
  • Patent number: 11508598
    Abstract: A frame jig for manufacturing a semiconductor package includes a frame body of a rectangular shape attached to a package structure of a panel shape, wherein the frame body comprises polyphenylene sulfide.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungwan Kim, Hyunsuk Yang
  • Patent number: 11472168
    Abstract: A laminated body for polishing a back surface of a wafer, the laminated body including an intermediate layer that is disposed between a support and a circuit surface of the wafer and peelably adheres to the support and the circuit surface, wherein the intermediate layer includes an adhesion layer in contact with the wafer and a peeling layer in contact with the support, and the peeling layer contains a novolac resin that absorbs light with a wavelength of 190 nm to 600 nm incident through the support, resulting in modification. The light transmittance of the peeling layer at a wavelength range of 190 nm to 600 nm may be 1 to 90%. The modification caused by absorption of light may be photodecomposition of the novolac resin.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 18, 2022
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Hiroshi Ogino, Hirokazu Nishimaki, Ryo Karasawa, Tetsuya Shinjo, Satoshi Kamibayashi, Shunsuke Moriya, Takahisa Okuno
  • Patent number: 11476128
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor device package. The method includes: (a) disposing a support structure on a first substrate; (b) electrically connecting a first electronic component on the first substrate, wherein a portion of the first electronic component is separated from the first substrate by the support structure; (c) heating the semiconductor device package; and (d) removing the support structure.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: October 18, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, An-Ping Chien
  • Patent number: 11462433
    Abstract: An apparatus includes a transfer element that is disposed adjacent the wafer tape. A tip end of the transfer element has a footprint sized so as to span across a group of dies on the wafer tape. An actuator is connected to the transfer element to move the transfer element to a die transfer position at which the transfer element presses on the wafer tape to press the group of dies into contact with a circuit trace on the product substrate.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: October 4, 2022
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andy Huska
  • Patent number: 11462575
    Abstract: The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 4, 2022
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Richard Price, Brian Cobb, Neil Davies
  • Patent number: 11463569
    Abstract: A structural component includes a middle frame, a glass cover, and a touch control film. The glass cover and the touch control film are disposed in a stacked manner. The touch control film is disposed on a surface that is of the glass cover and that faces the middle frame, and a side edge of the touch control film and a side edge of the glass cover do not overlap completely. The glass cover is bonded using the first bonding adhesive, and the touch control film is bonded using the second bonding adhesive. The first bonding adhesive is bonded to an edge of the glass cover, and the bonding force of the first bonding adhesive is greater than the bonding force of the second bonding adhesive.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 4, 2022
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Renwei Guo, Xixiang Dai
  • Patent number: 11456214
    Abstract: A method of processing a workpiece includes a thermosetting step of heating an area of an expandable sheet around a workpiece to a predetermined temperature or higher and thereafter cooling the heated area of the expandable sheet to make the area harder than before the area has been heated, and after the thermosetting step, an expanding step of expanding the area of the expandable sheet around the workpiece in planar directions to divide the workpiece into chips or to increase distances between the adjacent chips.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 27, 2022
    Assignee: DISCO CORPORATION
    Inventor: Yoshinobu Saito
  • Patent number: 11430677
    Abstract: Wafer taping apparatuses and methods are provided for determining whether taping defects are present on a semiconductor wafer, based on image information acquired by an imaging device. In some embodiments, a method includes applying an adhesive tape on a surface of a semiconductor wafer. An imaging device acquires image information associated with the adhesive tape on the semiconductor wafer. The presence or absence of taping defects is determined by defect recognition circuitry based on the acquired image information.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yi Lee, Wen-Kuei Liu
  • Patent number: 11417576
    Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
  • Patent number: 11342226
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 24, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Karthik Balakrishnan, Jungrae Park, Sriskantharajah Thirunavukarasu, Eng Sheng Peh
  • Patent number: 11335564
    Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: May 17, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Toshiyuki Takasaki, Shogo Okita
  • Patent number: 11304346
    Abstract: A method for shielding a system-in-package (SIP) assembly from electromagnetic interference (EMI) includes laminating a pre-form EMI shielding film onto the assembly in a single lamination process. The EMI shielding film may be moldable in a vacuum lamination process to cover the SIP assembly and to substantially fill trenches formed in the assembly between adjacent component modules. The SIP assembly is accordingly shielded from EMI through the application of a single EMI shielding film.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Henkel AG & Co. KGaA
    Inventors: Xuan Hong, Daniel Maslyk, Qizhuo Zhuo, Juliet Grace Sanchez
  • Patent number: 11289381
    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma
  • Patent number: 11289348
    Abstract: A workpiece processing method is provided for processing a workpiece including a device region, a peripheral surplus region surrounding the device region, and key patterns being arranged on a top surface side in the peripheral surplus region so as to correspond to a plurality of planned dividing lines, the method including: a resin sheet sticking step of sticking a resin sheet to the top surface side of the workpiece, and transferring the key patterns onto the resin sheet; a peripheral surplus region removing step of dividing the peripheral surplus region from the workpiece, and peeling off the peripheral surplus region from the resin sheet; and a device region processing step of identifying a position of at least one planned dividing line by using, as marks, traces of the key patterns exposed in the peripheral surplus region removing step, and processing the device region along the plurality of planned dividing lines.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 29, 2022
    Assignee: DISCO CORPORATION
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 11264262
    Abstract: The present disclosure, in some embodiments, relates to a debonding and cleaning apparatus. The apparatus has a debonding module configured to separate semiconductor substrates from carrier substrates. A first cleaning module is configured to clean surfaces of a first plurality of the semiconductor substrates and a second cleaning module is configured to clean surfaces of a second plurality of the semiconductor substrates. The apparatus also has a first substrate handling module including a first robotic arm in communication with the debonding module and a second substrate handling module including a second robotic arm that is located between the first cleaning module and the second cleaning module. The second substrate handling module is configured to transfer the first plurality of the semiconductor substrates to first cleaning module and to transfer the second plurality of the semiconductor substrates to the second cleaning module.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Yu-Liang Lin, Hung-Jung Tu
  • Patent number: 11171056
    Abstract: A cutting method includes: disposing a dicing tape on a back surface of a wafer; holding the wafer on a chuck table through the dicing tape; causing a cutting blade to cut into the wafer held on the chuck table until the tip of the cutting blade reaches the dicing tape to form cut grooves; imaging the cut groove from the front surface side of the wafer by a first imaging section to form a picked-up image of a front surface portion of the cut groove, and imaging the cut groove from the front surface side of the wafer by a second imaging section to form a picked-up image of a back surface portion of the cut groove, thereby checking the picked-up images of the front surface portion and the back surface portion of the cut groove.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: November 9, 2021
    Assignee: DISCO CORPORATION
    Inventor: Naoko Yamamoto
  • Patent number: 11164829
    Abstract: Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 11152309
    Abstract: A method of fabricating a semiconductor package may include forming a lower redistribution layer, forming a stack on a portion of the lower redistribution layer, and stacking a semiconductor chip on a top surface of the lower redistribution layer. The forming of the stack may include coating a photo imagable dielectric material to form a first insulating layer on the top surface of the lower redistribution layer, forming a first via to penetrate the first insulating layer, coating a photo imagable dielectric material to form a second insulating layer on a top surface of the first insulating layer, and forming a second via to penetrate the second insulating layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoung Lim Suk
  • Patent number: 11114307
    Abstract: A method of producing a wafer includes a peel-off layer forming step to form a peel-off layer in a hexagonal single-crystal ingot by applying a laser beam having a wavelength transmittable through the hexagonal single-crystal ingot while positioning a focal point of the laser beam in the hexagonal single-crystal ingot at a depth corresponding to the thickness of a wafer to be produced from an end face of the hexagonal single-crystal ingot, an ultrasonic wave generating step to generate ultrasonic waves from an ultrasonic wave generating unit positioned in facing relation to the wafer to be produced across a water layer interposed therebetween, thereby to break the peel-off layer, and a peel-off detecting step to detect when the wafer to be produced is peeled off the hexagonal single-crystal ingot by positioning an image capturing unit sideways of the wafer to be produced.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 7, 2021
    Assignee: DISCO CORPORATION
    Inventor: Ryohei Yamamoto
  • Patent number: 11105752
    Abstract: An inspecting apparatus for inspecting a test piece. The inspecting apparatus includes a test piece holding mechanism for holding the test piece, the test piece holding mechanism having a mounting portion formed from a transparent member having upper and lower exposed surfaces, the upper exposed surface of the transparent member functioning as a mounting surface for mounting the test piece, whereby the test piece mounted on the mounting surface of the mounting portion is adapted to be held by the test piece holding mechanism. The inspecting apparatus further includes an imaging mechanism for imaging the test piece held by the test piece holding mechanism, the imaging mechanism having a first imaging unit provided above the mounting portion, a second imaging unit provided below the mounting portion, and a connecting portion for connecting the first imaging unit and the second imaging unit.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 31, 2021
    Assignee: DISCO CORPORATION
    Inventors: Tomoaki Sugiyama, Hirohiko Kozai, Naoki Morikawa
  • Patent number: 11094858
    Abstract: A tape includes at least one tape unit. The tape unit includes a base structure having a first portion and a second portion. The first portion has a first surface and a second surface opposite to the first surface. The second portion protrudes from the second surface of the first portion, and has a third surface opposite to the first surface of the first portion and a lateral surface extending between the second surface and the third surface. An area of the first portion from a top view is greater than an area of the second portion from a top view.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jenchun Chen
  • Patent number: 11056390
    Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 6, 2021
    Assignee: INVENSAS CORPORATION
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram
  • Patent number: 11037919
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: June 15, 2021
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 10879226
    Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Arkalgud R. Sitaram, Paul Enquist
  • Patent number: 10867985
    Abstract: A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
  • Patent number: 10858547
    Abstract: Provided is a film for manufacturing a semiconductor part in which an evaluation step accompanied with a temperature change, a segmenting step, and a pickup step can be commonly performed, a method for manufacturing a semiconductor part, a semiconductor part, and an evaluation method. The film includes a base layer, and an adhesive layer disposed on one surface side of the base layer, wherein the ratio RE (=E?(160)/E?(?40)) of the elastic modulus of the base layer at 160° C. to the elastic modulus of the base layer at ?40° C. is RE?0.01, and the elastic modulus E?(?40) is 10 MPa to less than 1000 MPa. The method includes bonding the adhesive layer to a back surface of a semiconductor wafer, separating the semiconductor wafer into segments to obtain semiconductor parts, and separating the semiconductor parts from the adhesive layer, and includes a step of evaluating.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 8, 2020
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventor: Eiji Hayashishita
  • Patent number: 10857773
    Abstract: Transfer of nanoscale elements from a substrate on which they were manufactured or transferred to a flexible sheet may be performed by local and progressive deformation of the flexible sheet over the surface of the substrate to attach and lift the nanoscale elements from the substrate with controlled inter-element registration.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: December 8, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Kevin Thomas Turner, David Scott Grierson
  • Patent number: 10777460
    Abstract: A processing method of a workpiece for processing the workpiece including a substrate and a film made on a back surface of the substrate is provided. The processing method includes a sheet sticking step of sticking a sheet to the film, a protective film forming step of forming a protective film that covers the front surface side of the substrate, a mask pattern forming step of removing a part corresponding to planned dividing lines in the protective film and forming a mask pattern on the front surface side, an etching step of carrying out dry etching for the substrate from the front surface side and forming etching grooves and a film dividing step of dividing the film along the etching grooves by pressing the workpiece by an edge of a tip part of a pressing member having the tip part in which the edge has a curved shape.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 15, 2020
    Assignee: DISCO CORPORATION
    Inventors: Yukiko Matsumoto, Meiyu Piao
  • Patent number: 10741448
    Abstract: A method of fabricating a semiconductor package includes providing a substrate on a stage, the substrate including semiconductor dies and a modified layer along a partition lane and sequentially having an adhesive film and a base film on a surface thereof so that bottom surfaces of the adhesive film and the base film face the stage and top surfaces of the adhesive film and the base film face away from the stage and the bottom surface of the adhesive film faces the top surface of the base film; separating the semiconductor dies from each other by applying a force to the substrate in a lateral direction; applying a gas pressure to a top surface of each of the semiconductor dies; and irradiating ultraviolet rays toward the adhesive film after applying the gas pressure on the top surface of each of the semiconductor dies.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byong-gook Jeong, Byung-ho Kim, Youn-jo Mun, Jeong-cheol An, Sung-il Cho, Dae-sang Chun, Man-hee Han
  • Patent number: 10727219
    Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
  • Patent number: 10720355
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 21, 2020
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10672630
    Abstract: Described herein is a method and system for dual stretching of wafers to create isolated segmented chip scale packages. A wafer having an array of light-emitting diodes (LEDs) is scribed into LED segments, where each LED segment includes a predetermined number of LEDs. The scribed wafer is placed on a stretchable substrate or tape. The tape is stretched and a layer of optically material is placed in the separation gaps. The stretched wafer is scribed on a LED level. The tape is stretched and another layer of optically opaque material is placed in the separation gaps. The same or different optically opaque material can be used for the layers. The two layers of optically opaque material are formed to provide electrical connectivity between the LEDs in each LED segment. In an implementation, each segment or LED is individually addressable.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 2, 2020
    Assignee: Lumileds LLC
    Inventors: Arjen Gerben Van der Sijde, Nicola Bettina Pfeffer, Brendan Moran
  • Patent number: 10668595
    Abstract: A method of using a laminated dressing board is provided. In the laminated dressing board, a shape adjustment dressing layer containing first abrasive grains and used for shape adjustment of a cutting blade and a setting dressing layer containing second abrasive grains and used for setting of the shape-adjusted cutting blade are laminated. The method includes a holding step of holding the shape adjustment dressing layer side of the laminated dressing board by a chuck table, a setting dressing step of causing the cutting blade to cut into the laminated dressing board from the setting dressing layer side to form a first groove in the setting dressing layer, and a shape adjustment dressing step of causing the cutting blade to cut into the bottom of the first groove along the first groove to form a second groove in the shape adjustment dressing layer.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 2, 2020
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 10665494
    Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: May 26, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Niranjan Kumar, Seshadri Ramaswami, Shay Assaf, Amikam Sade, Andy Constant, Maureen Breiling
  • Patent number: 10599038
    Abstract: Provided are a rinsing liquid which is used for rinsing a resist film obtained from an actinic ray-sensitive or radiation-sensitive composition and includes a hydrocarbon-based solvent having a branched alkyl group. The hydrocarbon-based solvent having a branched alkyl group contains at least one of isodecane or isododecane.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 24, 2020
    Assignee: FUJIFILM Corporation
    Inventors: Hideaki Tsubaki, Toru Tsuchihashi, Wataru Nihashi
  • Patent number: 10580697
    Abstract: There is provided a dividing method for dividing a plate-shaped workpiece. The dividing method includes: a starting point region forming step of forming a starting point region serving as a starting point of division along a planned dividing line set on the workpiece; a heating step of heating the workpiece after performing the starting point region forming step; a cooling step of cooling the workpiece after performing the heating step; a dividing step of dividing the workpiece along the starting point region by applying a force to the workpiece after performing the cooling step; and a sheet affixing step of affixing an expanding sheet to the workpiece before performing the dividing step; the dividing step applying the force to the workpiece by expanding the expanding sheet.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: March 3, 2020
    Assignee: DISCO CORPORATION
    Inventor: Nao Hattori
  • Patent number: 10566319
    Abstract: A semiconductor device die transfer apparatus includes a first frame to hold a wafer tape having a plurality of semiconductor device die disposed on a side of the wafer tape and a second frame to secure a product substrate having a circuit trace thereon. The second frame is configured to secure the product substrate such that the circuit trace is disposed facing the plurality of semiconductor device die on the wafer tape. Additionally, a rotary transfer collet is disposed between the wafer tape and the product substrate. The rotary transfer collet has a rotational axis allowing rotation from a first position facing the wafer tape to pick a die of the plurality of semiconductor device die to a second position facing the circuit trace on the product substrate to release the die, thereby applying the die directly on the product substrate during a transfer operation.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 18, 2020
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Clinton Adams, Sean Kupcow, Andrew Huska
  • Patent number: 10559487
    Abstract: A wafer is divided at division starting points along division lines to form a predetermined gap between adjacent chips. Next, that area of a tape to which the wafer is adhered is suction held by a table, after which the table and a ring frame holding section are relatively moved further away from each other to expand the tape in a ring shape between an outer periphery of the wafer and an inner periphery of a ring frame. Thereafter, the table and the ring frame holding section are relatively moved closer to each other to slacken the ring-shaped tape, and the ring-shaped tape is heated by a heater, to heat shrink the tape and to maintain the predetermined gap between the adjacent chips.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: February 11, 2020
    Assignee: DISCO CORPORATION
    Inventor: Atsushi Ueki
  • Patent number: 10529623
    Abstract: The method of manufacturing a light emitting element includes: temporarily fixing a semiconductor layer of a wafer including a base member and the semiconductor layer to a support base member by a double-sided tape having a loss tangent adapted to be increased by heating from an ordinary temperature; forming a cleavage starting portion for dividing the wafer into a plurality of light emitting elements at an ordinary temperature in the wafer; and singulating the wafer into a plurality of light emitting elements on the support base member while the double-sided tape is heated.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 7, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Shuichi Iwamoto, Shohei Sadamoto, Shinya Mitsuhashi
  • Patent number: 10513011
    Abstract: A noncontact support system includes a table with a port layer having a pattern of interspersed pressure ports and vacuum ports. A pressure conduit layer includes a grid pattern of pressure conduits, connectable to a pressure source, each of the pressure ports being located on an axis passing through an intersection of at least two of the pressure conduits and substantially orthogonal to the grid pattern of pressure conduits. A vacuum conduit layer includes a grid pattern of vacuum conduits, connectable to a suction source, each of the vacuum ports being located on an axis passing through an intersection of at least two of the vacuum conduits and substantially orthogonal to the grid pattern of vacuum conduits. The grid pattern of vacuum conduits is laterally offset from the grid pattern of pressure conduits such that each intersection of pressure conduits is laterally offset from all intersections of the vacuum conduits.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 24, 2019
    Assignee: Core Flow Ltd.
    Inventors: Yaacov Legerbaum, Ronen Lautman, Leonid Nosovsky, Boaz Nishri
  • Patent number: 10504804
    Abstract: A laser processing method includes irradiating a laser light into a substrate along a cutting line to form a laser-scribed layer within the substrate, irradiating an X-ray onto a first surface of the substrate along the cutting line, obtaining an image of a diffracted X-ray from the substrate, and determining whether or not the laser-scribed layer is formed along the cutting line, based on analysis of the obtained image of the diffracted X-ray.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Yeol Yang, Hyung-Su Son, Hae-Gu Lee, Dong-Su Han
  • Patent number: 10475842
    Abstract: The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Chan Kim, Yong Ho Baek
  • Patent number: 10470317
    Abstract: A method for manufacturing a circuit board includes: forming a first adhesive layer on a first surface of a vibration unit, in which the vibration unit includes at least one piezoelectric material layer; forming a first stacking structure on the first adhesive layer; and applying a voltage to the at least one piezoelectric material layer to cause the at least one piezoelectric material layer to vibrate, such that the first stacking structure is separate from the vibration unit.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: November 5, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Hsiang-Hung Huang, Chi-Min Chang
  • Patent number: 10438792
    Abstract: A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer encapsulating the polycrystalline substrate, and a bonding layer coupled to the barrier layer. The method further includes forming a first silicon layer coupled to the bonding layer, forming a dielectric layer coupled to the first silicon layer, forming a second silicon layer coupled to the dielectric layer, removing a portion of the second silicon layer and a corresponding portion of the dielectric layer to expose a portion of the first silicon layer, forming a gallium nitride (GaN) layer coupled to the exposed portion of the first silicon layer, forming a gallium nitride (GaN) based device coupled to the GaN layer, and forming a silicon-based device coupled to a remaining portion of the second silicon layer.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: October 8, 2019
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 10431515
    Abstract: The present disclosure describes apparatuses and techniques for self-aligning integrated circuit (IC) dies. In some aspects, a hydrophobic material is deposited on a surface of a substrate to form a pattern on the surface of the substrate. The pattern may expose areas of the substrate surface for placement of IC dies. A water-based solution is then applied to the exposed areas such that droplets form on the exposed areas of the substrate surface. IC dies are placed on the droplets of the water-based solution, which can cause the IC dies to align with the exposed areas of the substrate surface. The droplets are then caused to evaporate such that the IC dies settle on the exposed areas of the substrate surface.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: October 1, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Long-Ching Wang, Marc Jacobs