With Attachment To Temporary Support Or Carrier Patents (Class 438/464)
  • Patent number: 8835283
    Abstract: A fabrication method for producing semiconductor chips with enhanced die strength comprises following steps: forming a semiconductor wafer with enhanced die strength by comprising the substrate, the active layer on the front side of the substrate and the backside metal layer on the backside of the substrate, wherein at least one integrated circuit forms in the active layer; forming a protection layer on a front side of the semiconductor wafer; dicing the semiconductor wafer by at least one laser dicing process and removing the laser dicing residues and removing said protection layer by at least one etching process, whereby plural semiconductor chips with enhanced die strength are produced, and wherein the backside metal layer of said semiconductor chip fully covers the backside of said semiconductor chip after dicing.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 16, 2014
    Assignee: WIN Semiconductors Corp.
    Inventor: Chang-Hwang Hua
  • Patent number: 8828848
    Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ying-Da Wang, Li-Chung Kuo, Szu Wei Lu
  • Patent number: 8822310
    Abstract: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 2, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerald Lackner, Christian Maier, Francisco Javier Santos Rodriguez
  • Patent number: 8822305
    Abstract: A plurality of single crystal semiconductor substrates having a rectangular shape are disposed on a tray. Depression portions are provided in the tray so that the single crystal semiconductor substrates can fit in. The single crystal semiconductor substrates disposed on the tray are doped with hydrogen ions, so that damaged regions are formed at a desired depth. A bonding layer is formed on surfaces of the single crystal semiconductor substrates. The plurality of single crystal semiconductor substrates in each of which the damaged region is formed and on which the bonding layer is formed are disposed on the tray and bonded to the base substrate. By heat treatment, the single crystal semiconductor substrates are separated at the damaged regions; accordingly, a plurality of single crystal semiconductor layers which are thinned are formed over the base substrate.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20140242781
    Abstract: A method for preparing a semiconductor wafer into individual semiconductor dies uses both a dicing before grinding step and/or via hole micro-fabrication step, and an adhesive coating step.
    Type: Application
    Filed: May 6, 2014
    Publication date: August 28, 2014
    Inventors: Hwang Kyu Yun, Jeffrey Leon, Raj Peddi, YounSang Kim
  • Patent number: 8815706
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming a trench from a top surface of a substrate having a device region. The device region is adjacent to the top surface than an opposite bottom surface. The trench surrounds the sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. The adhesive layer is removed and adhesive is etched to expose a sidewall of the device region.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Michael Roesner, Manfred Engelhardt
  • Patent number: 8815644
    Abstract: A wafer processing method for processing a wafer having a device area and a peripheral marginal area surrounding the device area. The method includes: (i) attaching an adhesive tape having an annular adhesive layer only in a peripheral area thereof to the front side of the wafer, whereby the front side of the wafer is fully covered with the adhesive tape and the annular adhesive layer is positioned to correspond to the peripheral marginal area of the wafer, without the annular adhesive layer making contact with the device area; (ii) applying a laser beam to the wafer along division lines to thereby form a plurality of modified layers inside the wafer; (iii) attaching a protective tape to the back side of the wafer and peeling the adhesive tape from the front side of the wafer; and (iv) applying an external force to the wafer to divide the wafer.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: August 26, 2014
    Assignee: Disco Corporation
    Inventor: Karl Priewasser
  • Patent number: 8815707
    Abstract: A device fabrication method includes: (1) providing a growth substrate including a base and an oxide layer disposed over the base; (2) forming a metal layer over the oxide layer; (3) forming a stack of device layers over the metal layer; (4) performing interfacial debonding of the metal layer to separate the stack of device layers and the metal layer from the growth substrate; and (5) affixing the stack of device layers to a target substrate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: August 26, 2014
    Assignee: Board of Trustess of the Leland Stanford Junior University
    Inventors: Chi-Hwan Lee, Dong Rip Kim, Xiaolin Zheng
  • Patent number: 8809166
    Abstract: Embodiments of methods and systems for processing a semiconductor wafer are described. In one embodiment, a method for processing a semiconductor wafer involves performing laser stealth dicing on the semiconductor wafer to form a stealth dicing layer within the semiconductor wafer and after performing laser stealth dicing, cleaning the semiconductor wafer from a back-side surface of the semiconductor wafer with a blade to remove at least a portion of the stealth dicing layer. Other embodiments are also described.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 19, 2014
    Assignee: NXP B.V.
    Inventors: Hartmut Buenning, Sascha Moeller, Martin Lapke, Guido Albermann, Thomas Rohleder
  • Patent number: 8802469
    Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: August 12, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Chen-Fu Chu, Trung Tri Doan, Hao-Chun Cheng, Feng-Hsu Fan, Fu-Hsien Wang
  • Patent number: 8802545
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
  • Patent number: 8803302
    Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
  • Patent number: 8796115
    Abstract: A light-emitting diode arrangement comprising a plurality of semiconductor chips which are provided for emitting electromagnetic radiation from their front side and which are fixed by their rear side—opposite the front side—on a first main face of a common carrier body, wherein the semiconductor chips consist of a respective substrateless semiconductor layer stack and are fixed to the common carrier body without an auxiliary carrier, and to a method for producing such a light-emitting diode arrangement.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: August 5, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jörg Erich Sorg, Stefan Gruber, Siegfried Herrmann, Berthold Hahn
  • Patent number: 8796050
    Abstract: Methods and apparatus for manufacturing a semiconductor light-emitting device that emits white light by forming a phosphor layer on an emission surface of the semiconductor light-emitting device at a wafer-level. The method includes: forming a plurality of light-emitting devices on a wafer; thinning the wafer, on which the plurality of light-emitting devices are formed; disposing the thinned wafer on a carrier film; and forming a phosphor layer on an emission surface of the plurality of light-emitting devices on the wafer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-jun Yoo, Seong-jae Hong, Tsuyoshi Tsutsui, Shin-kun Kim
  • Patent number: 8796114
    Abstract: A method for slicing a monocrystalline semiconductor layer (116) from a semiconductor single crystal (100) comprising: providing a semiconductor single crystal (100) having a uniform crystal structure; locally modifying the crystal structure within a separating plane (104) in the semiconductor single crystal (100) into an altered microstructure state by means of irradiation using a laser (106); and removing the modified separating plane (104) by means of selective etching.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: August 5, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Patent number: 8796154
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: August 5, 2014
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
  • Patent number: 8790996
    Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Invensas Corporation
    Inventor: Pezhman Monadgemi
  • Publication number: 20140203458
    Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: NITTO DENKO CORPORATION
    Inventors: Naohide TAKAMOTO, Goji SHIGA, Fumiteru ASAI, Toshimasa SUGIMURA
  • Patent number: 8785296
    Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a center area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 22, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Ping Huang, Yueh-Se Ho
  • Patent number: 8785332
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 22, 2014
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, Linnell Martinez, David Pays-Volard, Rich Gauldin, Russell Westerman, Gordon M. Grivna
  • Patent number: 8785299
    Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8778735
    Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: July 15, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ping Huang, Lei Shi, Lei Duan, Yuping Gong
  • Patent number: 8772136
    Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chine-Li Wang, Chun-Yen Chen, Wei-Hua Fang, Hung-Hsien Chang, Yung-Chin Yen
  • Patent number: 8772133
    Abstract: The various aspects comprise methods and devices for processing a wafer. An aspect of this disclosure includes a wafer. The wafer comprises a plurality of die regions; a plurality of kerf regions between the plurality of die regions; and a metallization area on the plurality of die regions.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Martin Zgaga, Karl Adolf Mayer, Gudrun Stranzl
  • Patent number: 8765579
    Abstract: A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 1, 2014
    Assignee: Disco Corporation
    Inventors: Youngsuk Kim, Shigenori Harada
  • Patent number: 8765580
    Abstract: A method for fabricating semiconductor devices includes: (a) forming a layered structure that includes a temporary substrate, a plurality of spaced apart sacrificial film regions on the temporary substrate, and a plurality of valley-and-peak areas among the sacrificial film regions; (b) growing laterally and epitaxially an epitaxial film layer over the sacrificial film regions and the valley-and-peak areas, wherein gaps are formed among the epitaxial film layer and the valley-and-peak areas; (c) forming a conductive layer to contact the epitaxial film layer; (d) forming a plurality of grooves to divide the epitaxial film layer and the conductive layer into a plurality of epitaxial structures on the temporary substrate; and (e) removing the temporary substrate and the sacrificial film regions from the epitaxial structures by etching the sacrificial film regions through the gaps and the grooves.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 1, 2014
    Assignee: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng
  • Patent number: 8759951
    Abstract: The present invention provides a method for selectively transferring elements such as monocrystalline Si thin films or elements made of monocrystalline Si from a base substrate (100) onto an insulating substrate without the use of an intermediate substrate. The base substrate (first substrate) (100) in which the elements are formed is selectively irradiated with a laser having a multiphoton absorption wavelength. Thus, elements to be transferred out of the elements and corresponding thin films on the base substrate (100) are transferred onto a transfer destination substrate (second substrate) (200).
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 24, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 8753923
    Abstract: A wafer processing method of dividing a wafer along streets. The wafer processing method includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, a modified layer forming step of holding the wafer through the protective tape on a chuck table of a laser processing apparatus under suction and next applying a laser beam having a transmission wavelength to the wafer from the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and a wafer dividing step of canceling suction holding of the wafer by the chuck table and next applying an air pressure to the wafer now placed on the holding surface in the condition where horizontal movement of the wafer is limited, thereby dividing the wafer along each street where the modified layer is formed, thus obtaining individual devices.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 17, 2014
    Assignee: Disco Corporation
    Inventors: Satoshi Kobayashi, Jinyan Zhao
  • Publication number: 20140162434
    Abstract: A dicing tape integrated adhesive sheet including a substrate, a dicing tape in which a pressure-sensitive adhesive layer is laminated on the substrate, and an adhesive sheet formed on the pressure-sensitive adhesive layer, wherein a peeling force between the pressure-sensitive adhesive layer and the adhesive sheet is 0.02 to 0.5 N/20 mm obtained with a peeling test at a peeling rate of 10 m/minute and a peeling angle of 150°, and an absolute value of a peeling electrification voltage is 0.5 kV or less when the pressure-sensitive adhesive layer and the adhesive sheet are peeled off under conditions of the peeling test.
    Type: Application
    Filed: October 17, 2013
    Publication date: June 12, 2014
    Applicant: NITTO DENKO CORPORATION
    Inventors: Goji SHIGA, Koji MIZUNO, Naohide TAKAMOTO
  • Patent number: 8748289
    Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 10, 2014
    Assignee: Ebara Corporation
    Inventors: Masayuki Nakanishi, Tetsuji Togawa, Kenya Ito, Masaya Seki, Kenji Iwade, Takeo Kubota
  • Patent number: 8748297
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gudrun Stranzl, Martin Zgaga, Markus Kahn, Guenter Denifl
  • Patent number: 8748231
    Abstract: A method of attaching a die to a carrier using a temporary attach material is disclosed. The method comprises attaching the temporary attach material between a surface of the die and a surface of the carrier. The temporary attach material attaches the die to the carrier. The method comprises bonding at least one connector to the die and the carrier. The connector includes a first end bonded to the carrier and a second end bonded to the die. The method further comprises encapsulating at least a portion of the die and at least a portion of the at least one connector by an encapsulation material.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: June 10, 2014
    Assignee: Amphenol Thermometrics, Inc.
    Inventors: Elizabeth Anne Logan, Terry Lee Marvin Cookson, Sisira Kankanam Gamage, Ronald Almy Hollis
  • Patent number: 8735218
    Abstract: A method of producing an electronic module with at least one electronic component and one carrier. A structure is provided on the carrier so that the electronic component can take a desired target position relative to the structure. The structure is coated with a liquid meniscus suitable for receiving the electronic component. Multiple electronic components are provided at a delivery point for the electronic components. The carrier, with the structure, is moved nearby and opposite to the delivery point, where the delivery point delivers one of the electronic components without contact, while the structure on the carrier is moving near the delivery point, so that after a phase of free movement the electronic component at least partly touches the material, and the carrier, with the structure, is moved to a downstream processing point, while the electronic component aligns itself to the structure on the liquid meniscus.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 27, 2014
    Assignee: Muehlbauer AG
    Inventors: Michael Max Mueller, Helfried Zabel, Hans-Peter Monser
  • Patent number: 8735262
    Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hermann Gruber, Thomas Gross, Andreas Peter Meiser, Markus Zundel
  • Patent number: 8732923
    Abstract: A method for manufacturing an acoustic wave device includes: adhering wafer-shaped first and second piezoelectric substrates to a front face of a first and second adhesive sheet respectively and dividing the first and the second piezoelectric substrates into rectangles; adhering a third and fourth adhesive sheet to the first and second piezoelectric substrates respectively and moving at least one divided portions of the first and second piezoelectric substrates selectively to the third and fourth adhesive sheet respectively; moving the first piezoelectric substrate on the first adhesive sheet to the fourth adhesive sheet; and moving the second piezoelectric substrate on the second adhesive sheet to the third adhesive sheet.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Kazunori Inoue, Tsutomu Miyashita, Kazuhiro Matsumoto
  • Publication number: 20140138813
    Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gopalakrishnan Trichy Rengarajan, Armin Tilke
  • Patent number: 8728910
    Abstract: To provide an olefinic expandable substrate and a dicing film that exhibits less contamination characteristics, high expandability without necking, which cannot be achieved by conventional olefinic expandable substrates. In order to achieve the object, an expandable film comprises a 1-butene-?-olefin copolymer (A) having a tensile modulus at 23° C. of 100 to 500 MPa and a propylenic elastomer composition (B) comprising a propylene-?-olefin copolymer (b1) and having a tensile modulus at 23° C. of 10 to 50 MPa, wherein the amount of the component (B) is 30 to 70 weight parts relative to 100 weight parts in total of components (A) and (B).
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 20, 2014
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Eiji Hayashishita, Katsutoshi Ozaki, Mitsuru Sakai, Setsuko Oike
  • Patent number: 8728915
    Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 20, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin Tsai, Cheng-I Huang, Yao-Hui Hu
  • Publication number: 20140134828
    Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
  • Patent number: 8722460
    Abstract: In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of sticky material. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: May 13, 2014
    Inventor: Mitsumasa Koyanagi
  • Patent number: 8722517
    Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: May 13, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai, Toshimasa Sugimura
  • Publication number: 20140127885
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. Heat is applied to the first carrier substrate while the localized pressure is applied.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 8, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8715802
    Abstract: The invention provides a transferring apparatus for a flexible electronic device and method for fabricating a flexible electronic device. The transferring apparatus for the flexible electronic device includes a carrier substrate. A release layer is disposed on the carrier substrate. An adhesion layer is disposed on a portion of the carrier substrate, surrounding the release layer and adjacent to a sidewall of the release layer. A flexible electronic device is disposed on the release layer and the adhesion layer, wherein the flexible electronic device includes a flexible substrate.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 6, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Pao-Ming Tsai, Liang-You Jiang, Yu-Yang Chang, Hung-Yuan Li
  • Patent number: 8715457
    Abstract: The detachment and removal of a semiconductor chip from a foil occurs in accordance with the invention in three phases. In the first phase there is a partial detachment of the semiconductor chip from the foil with mechanical means, but without the participation of a chip gripper. In the second phase the semiconductor chip is further detached from the foil, with the semiconductor chip being held by the chip gripper. In the third phase the chip gripper is lifted and moved away.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 6, 2014
    Assignee: Esec AG
    Inventor: Stefan Behler
  • Publication number: 20140117503
    Abstract: Compositions suitable for temporarily bonding two surfaces, such as a wafer active side and a substrate, are disclosed. Methods of temporarily bonding two surfaces, such as the active side of a wafer and a substrate using the compositions disclosed herein are also provided.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Mark S. OLIVER, Michael K. GALLAGHER
  • Publication number: 20140117504
    Abstract: Compositions containing an adhesive material and a release additive are suitable for temporarily bonding two surfaces, such as a wafer active side and a substrate. These compositions are useful in the manufacture of electronic devices where a component, such as an active wafer, is temporarily bonded to a substrate, followed by further processing of the active wafer.
    Type: Application
    Filed: October 22, 2013
    Publication date: May 1, 2014
    Inventors: Mark S. OLIVER, Michael K. GALLAGHER, Karen R. BRANTL
  • Patent number: 8710458
    Abstract: A method of forming an integrated circuit includes providing a wafer, and a tape adhered to the wafer, wherein the tape has a main surface perpendicular to a first direction. The tape is exposed to a light to cause the tape to lose adhesion. In the step of exposing the tape, the wafer and the tape are rotated, and/or the light is tilt projected onto the tape, wherein a main projecting direction of the light and the first direction form a tilt angle greater than zero degrees and less than 90 degrees.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chen-Fa Lu, Chung-Shi Liu
  • Patent number: 8710683
    Abstract: According to example embodiments, a wafer level mold may be formed by a method including attaching a substrate to a lower side of a wafer on which a semiconductor chip is arranged, applying molding liquid to an upper and at least one lateral side of the semiconductor chip and an upper side of the wafer where the semiconductor chip is not arranged, loading a fiber onto the applied liquid, forming a mold layer by compression-molding and curing the liquid loaded with the fiber, and separating the substrate from the wafer.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae Hwan Kim
  • Patent number: 8703585
    Abstract: An adhesive composition for a semiconductor includes an acrylic polymer (A), an epoxy-based heat curable resin (B), a heat curing agent (C), a silane compound (D) having an organic functional group, molecular weight of 300 or more and an alkoxy equivalent of larger than 13 mmol/g, and a silane compound (E) having an organic functional group, molecular weight of 300 or less and an alkoxy equivalent of 13 mmol/g or less.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: April 22, 2014
    Assignee: LINTEC Corporation
    Inventors: Isao Ichikawa, Masaaki Furudate, Mikihiro Kashio, Sou Miyata, Kaisuke Yanagimoto, Yuichi Kozone
  • Patent number: 8703583
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo