Abstract: Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps of: forming fin masks on a SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins. Implementations with a bulk substrate, as well as the resulting devices, are also provided.

Abstract: A wafer processing laminate, a wafer processing member, a temporary adhering material for processing wafer, and a method for manufacturing a thin wafer using the same. The wafer processing laminate includes a support, a temporary adhesive material layer formed thereon and a wafer laminated on the temporary adhesive material layer, where the wafer has a circuit-forming front surface and a back surface to be processed. The temporary adhesive material layer includes a first temporary adhesive layer of a thermoplastic organopolysiloxane polymer layer (A) releasably adhered on a surface of the wafer, a second temporary adhesive layer of a radiation curable polymer layer (B) laminated on the first temporary adhesive layer, and a third temporary adhesive layer of a thermoplastic organopolysiloxane polymer layer (A?) laminated on the second temporary adhesive layer and releasably adhered to the support.

Abstract: A plasma processing method to a substrate includes a first step of mounting a transfer carrier holding the substrate on a stage which is cooled and provided within a processing chamber; a second step of relatively moving the stage and a cover provided above the stage to cover a holding sheet and an annular frame of the transfer carrier with the substrate exposed from a window part formed at the cover, a third step of carrying out plasma processing on the substrate, a fourth step of cooling the cover, and a fifth step of unloading the transfer carrier holding the substrate from the processing chamber.

Abstract: The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a first surface and a second surface wherein the second surface is opposed to the first surface. A mask layer is provided on the first surface of the substrate and a thin film layer is provided on the second surface of the substrate. The first surface of the substrate is diced through the mask layer to expose the thin film layer on the second surface of the substrate. A fluid from a fluid jet is applied to the thin film layer on the second surface of the substrate after the thin film layer has been exposed by the dicing step.

Abstract: A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.

Abstract: A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.

Abstract: Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

Abstract: A curable composition that can be released from a mold simply within a short period of time after photo-curing by a small mold-releasing force is provided. The curable composition contains a gas-generating agent that generates a gas by pressure application. A method of forming a pattern is also provided. In the method, the mold can be released with a small force.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an adaptive optics-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: An assembly including a liquid thermal interface material for surface tension adhesion and thermal control used during electrical/thermal test of a 3D wafer and methods of use. The method includes temporarily attaching a thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the thinned wafer and the blank silicon-based carrier wafer together.

Abstract: A wafer processing laminate, a wafer processing member, a temporary adhering material for processing a wafer, and a method for manufacturing a thin wafer, which facilitates to establish a temporary adhering the wafer and the support, enables to form a layer of uniform thickness on a heavily stepped substrate, and is compatible with the TSV formation and wafer back surface interconnect forming steps, and the wafer processing laminate includes a support, a temporary adhesive material layer formed thereon and a wafer laminated on the temporary adhesive material layer, where the wafer has a circuit-forming front surface and a back surface to be processed, wherein the temporary adhesive material layer includes a three-layered structure composite temporary adhesive material layer.

Abstract: Methods and systems of laser and plasma etch wafer dicing using UV-curable adhesive films. A method includes forming a mask covering ICs formed on the wafer. The semiconductor wafer is coupled to a film frame by a UV-curable adhesive film. A pre-cure of the UV-curable adhesive film cures a peripheral portion of the adhesive extending beyond an edge of the wafer to improve the exposed adhesive material's resistance to plasma etch and reduce hydrocarbon redeposition within the etch chamber. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the ICs. A center portion of the UV-curable adhesive is then cured and the singulated ICs detached from the film.

Abstract: A wafer processing method including a mask forming step of forming a mask for covering a region corresponding to each device on a functional layer formed on the front side of a substrate constituting a wafer, a groove forming step of spraying a fluid containing abrasive grains against the front side of the wafer to thereby form a groove for dividing the functional layer along each street, and an etching step of performing dry etching from the front side of the wafer to thereby form an etched groove along each street. Accordingly, it is possible to prevent that the functional layer may be separated to cause damage to each device. Furthermore, a wide area of the wafer can be processed at a time, so that the productivity can be improved.

Abstract: Provided is a delamination device of delaminating a laminated substrate obtained by bonding a first substrate and a second substrate, the laminated substrate being disposed in an opening of a frame, the opening having a diameter larger than that of the laminated substrate, and the laminated substrate being held by the frame with a non-bonding surface of the first substrate attached to a tape provided in the opening. The delamination device includes: a first holding unit configured to hold the second substrate of the laminated substrate from above; a second holding unit configured to hold the first substrate of the laminated substrate from below through the tape; and a moving mechanism configured to move the first holding unit in a direction away from the second holding unit.

Abstract: A break separation apparatus and method are provided. The apparatus comprises a vibration stage for holding at least one liquid crystal panel to be separated and vibrating the liquid crystal panel so that glass substrate of the liquid crystal panel breaks along a cutting groove. According to the apparatus and method, the cutting grooves cut on the glass substrate are substantially extended in thickness direction of the glass substrate by vibration method so as to achieve separation, which can be readily controlled and avoid contamination and damage to the liquid crystal panel.

Abstract: A hybrid laminated body is provided that includes a light-transmitting support, a latent release layer disposed upon the light-transmitting support, a joining layer disposed upon the latent release layer, and a polyamide thermoplastic priming layer disposed upon the joining layer. The hybrid laminated body can further include a substrate to be processed such as, for example, a silicon wafer to be ground. Also provided is a method for manufacturing the provided laminated body.

Abstract: The adhesive sheet for manufacturing a semiconductor device is an adhesive sheet for manufacturing a semiconductor device used when a semiconductor element is adhered to an adherend and the semiconductor element is wire-bonded, and is a peelable adhesive sheet in which the 180 degree peeling adhesive strength against a silicon wafer is 5 (N/25 mm width) or less.

Abstract: A resin sealing sheet is cut into an adhesive sheet piece having an outer shape smaller than that of a wafer. The adhesive sheet piece is joined to a supporting adhesive tape together with a ring frame. The adhesive tape between the ring frame and the adhesive sheet piece is sandwiched by upper and lower housings to form a chamber. The wafer with a support board placed on a wafer holding table within the chamber faces to the adhesive sheet piece closely. The chamber is divided into two spaces by the adhesive tape. Differential pressure generated within the two spaces causes the adhesive tape and the adhesive sheet piece to cave and bend toward the wafer, whereby the adhesive sheet piece is joined to the wafer.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber. A bipolar electrostatic chuck is disposed below the plasma source. The bipolar electrostatic chuck is sized to support a substrate carrier having a tape and tape frame. The bipolar electrostatic chuck is configured to control a backside temperature of the substrate carrier prior to and during plasma processing.

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.

Abstract: Provided is a method for disassembling a bonded body, whereby the bonded body can be easily disassembled and peeled. The method for disassembling a bonded body formed by bonding substrates with an adhesive comprises irradiating light having a wavelength of 280 nm or more such that irradiation energy is 1000-5000000 mJ/cm2 at a wavelength of 365 nm while heating the bonded body to 150° C.-300° C.

Abstract: The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die.

Abstract: A wafer processing method transfers an optical device layer (ODL) in an optical device wafer (ODW) to a transfer substrate. The ODL is formed on the front side of an epitaxy substrate through a buffer layer, and is partitioned by a plurality of crossing streets to define a plurality of regions where optical devices are formed. The transfer substrate is bonded to the front side of the ODL. The transfer substrate and the ODL are cut along the streets. The transfer substrate is attached to a supporting member, and a laser beam is applied to the epitaxy substrate from the back side of the epitaxy substrate to the unit of the ODW and the transfer substrate. The focal point of the laser beam is set in the buffer layer, thereby decomposing the buffer layer. The epitaxy substrate is then peeled off from the ODL.

Abstract: A wafer processing method for dividing a wafer into individual devices along a plurality of crossing division lines includes preparing a frame having a plurality of crossing partitions corresponding to the division lines of the wafer, spreading a liquid resin on the front side or back side of the wafer and positioning the partitions of the frame in alignment with the division lines of the wafer, thereby covering with the liquid resin the regions on the front side or back side of the wafer other than the regions corresponding to the division lines, curing the liquid resin supplied to the front side or back side of the wafer and next removing the frame, thereby masking the regions other than the regions corresponding to the division lines, and plasma-etching the wafer processed by the masking to thereby divide the wafer into the individual devices along the division lines.

Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Abstract: A method of manufacturing a semiconductor device include preparing an initial substrate including an edge region and a central region in which circuit patterns are formed, forming a reforming region in the edge region of the initial substrate, grinding the initial substrate to form a substrate, and cutting the substrate to form a semiconductor chip including each of the circuit patterns. A crystal structure of the reforming region is different from that of the initial substrate.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.

Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.

Abstract: Disclosed is a singulation apparatus, comprising: at least one chuck station to which a workpiece is securable, the at least one chuck station being configured to move along a feed direction; a bridge extending above the at least one chuck station, the bridge having a first side and a second side opposite the first side; a first cutting device members mounted to the bridge and being independently movable along the first side, transversely to the feed direction; and a second cutting device members mounted to the bridge and being independently movable along the second side, transversely to the feed direction, the first and second cutting devices being for cutting the workpiece. A singulation method is also disclosed.

Abstract: A method for handling and supporting a device wafer during a wafer thinning process and the resulting device are provided. Embodiments include forming a plurality of solder bumps on a first surface of a substrate having a first and a second surface; removing a portion from a periphery of the first surface of the substrate; forming a temporary bonding material on a first carrier; bonding the first surface of the substrate with the temporary bonding material of the first carrier; affixing the second surface of the substrate to a second carrier; and removing the temporary bonding material.

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate.

Abstract: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.

Abstract: Disclosed is a wafer process body, a temporary adhesive layer is formed on a supporting body, and a wafer having a circuit-formed front surface and a to-be-processed back surface is stacked on the temporary adhesive layer, wherein the temporary adhesive layer is provided with a first temporary adhesive layer including a non-aromatic saturated hydrocarbon group-containing organopolysiloxane layer (A) which is adhered to the front surface of the wafer so as to be detachable and a second temporary adhesive layer comprised of a thermosetting-modified siloxane polymer layer (B) which is stacked on the first temporary adhesive layer and adhered to the supporting body so as to be detachable. Thus, temporary adhesion of a wafer with a supporting body may become easy, process conformity with the TSV formation process and with the wafer-back surface-wiring process may become high, and removal may be done easily, with high productivity.

Abstract: A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.

Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a dicing tape and an anchoring material. The anchoring material and the wafer are cut with the sawing blade. During the cutting operation, the anchoring material reduces backside chipping of the die and eliminates fly-away die. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.

Abstract: A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion.

Abstract: System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.

Abstract: A method for manufacturing a semiconductor light-emitting device includes forming a multilayer body including a first semiconductor layer having a first major surface and a second major surface which is an opposite side from the first major surface, a second semiconductor layer including a light-emitting layer laminated on the second major surface of the first semiconductor layer, and electrodes formed on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer. The method includes forming a groove through the first semiconductor layer. The method includes forming a phosphor layer on the first major surface and on a side surface of the first semiconductor layer in the groove.

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask, patterning the mask with a femtosecond laser scribing process to provide a patterned mask with gaps, and ablating through an entire thickness of a semiconductor substrate to singulate the IC. Following laser-based singulation, a plasma etch is performed to remove a layer of semiconductor sidewall damaged by the laser scribe process. In the exemplary embodiment, a femtosecond laser is utilized and a 1-3 ?m thick damage layer is removed with the plasma etch. Following the plasma etch, the mask is removed, rendering the singulated die suitable for assembly/packaging.

Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.

Abstract: A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards.

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract: A package for a plurality of semiconductor devices having: an electrical interconnect structure, comprising: an electrical interconnect structure; and an active device structure, comprising the plurality of semiconductor devices on an active device substrate. The electrical interconnect structure is bonded to the active device structure and the electrical interconnect structure provides electrical interconnection among the semiconductor devices.

Abstract: Laser and plasma etch wafer dicing using UV-curable adhesive films. A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a carrier substrate by a double-sided UV-curable adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the ICs. The UV-curable adhesive film is partially cured by UV irradiation through the carrier. The singulated ICs are then detached from the partially cured adhesive film still attached to the carrier substrate, for example individually by a pick and place machine. The UV-curable adhesive film may then be further cured for the film's complete removal from the carrier substrate.

Abstract: In a wafer processing method, grooves are formed on the front side of a wafer along all division lines extending in a first direction and along all division lines extending in a second direction perpendicular to the first direction. Each groove has a depth corresponding to a finished thickness of each device in the wafer. The wafer is cut into four sectorial wafer quarters. A protective member is provided on the front side of each wafer quarter; and the back side of the wafer quarter is ground to reduce the thickness of the wafer quarter to the finished thickness until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.