With Attachment To Temporary Support Or Carrier Patents (Class 438/464)
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Patent number: 8703584Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface has a multilayered structure including a wafer adhesion layer and a laser mark layer, the wafer adhesion layer is formed of a resin composition containing a thermosetting resin component and, as an optional component, a thermoplastic resin component in an amount of less than 30% by weight relative to the whole amount of resin components, and the laser mark layer is formed of a resin composition containing a thermoplastic resin component in an amount of 30% by weight or more relative to the whole amount of resin components and, as an optional component, a thermosetting resin component.Type: GrantFiled: May 28, 2010Date of Patent: April 22, 2014Assignee: Nitto Denko CorporationInventors: Sadahito Misumi, Naohide Takamoto
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Publication number: 20140106137Abstract: A wafer processing laminate, a wafer processing member, a temporary adhering material for processing wafer, and a method for manufacturing a thin wafer using the same. The wafer processing laminate includes a support, a temporary adhesive material layer formed thereon and a wafer laminated on the temporary adhesive material layer, where the wafer has a circuit-forming front surface and a back surface to be processed. The temporary adhesive material layer includes a first temporary adhesive layer of a thermoplastic organopolysiloxane polymer layer (A) releasably adhered on a surface of the wafer, a second temporary adhesive layer of a radiation curable polymer layer (B) laminated on the first temporary adhesive layer, and a third temporary adhesive layer of a thermoplastic organopolysiloxane polymer layer (A?) laminated on the second temporary adhesive layer and releasably adhered to the support.Type: ApplicationFiled: October 1, 2013Publication date: April 17, 2014Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Kazunori KONDO, Hideto KATO, Michihiro SUGO, Shohei TAGAMI, Hiroyuki YASUDA
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Patent number: 8691666Abstract: A method for producing a chip (13) in which a die bonding adhesive layer (24) and a wafer (1) are laminated on a close-contact layer (31) of a fixing jig (3), the chip is formed by completely cutting the wafer and the die bonding adhesive layer and then the chip is picked up together with the die bonding adhesive layer from the fixing jig by deforming the close-contact layer of the fixing jig. In the method the fixing jig is provided with the close-contact layer and a jig base (30) that is provided with a plurality of protrusions (36) on one side and a sidewall (35) at the outer circumference section of the one side. The close-contact layer is laminated on the surface of the jig base provided with the protrusions and is bonded on the upper surface of the sidewall. On the surface of the jig base provided with the protrusions, a partitioned space is formed by the close-contact layer, the protrusions, and the sidewall.Type: GrantFiled: April 15, 2008Date of Patent: April 8, 2014Assignee: Lintec CorporationInventors: Takeshi Segawa, Naofumi Izumi
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Patent number: 8691702Abstract: The present invention provides a method for plasma processing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing a cover ring above the work piece, the cover ring having at least one perforated region, and at least one non-perforated region; generating a plasma using the plasma source; and processing the work piece using the generated plasma.Type: GrantFiled: March 14, 2013Date of Patent: April 8, 2014Assignee: Plasma-Therm LLCInventors: Dwarakanath Geerpuram, David Pays-Volard, Linnell Martinez, Chris Johnson, David Johnson, Russell Westerman
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Publication number: 20140087542Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: Semiconductor Components Industries, LLCInventor: GORDON M. GRIVNA
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Publication number: 20140080287Abstract: A method relates to separating a component composite into a plurality of component regions, wherein the component composite is provided having a semiconductor layer sequence comprising a region for generating or for receiving electromagnetic radiation. The component composite is mounted on a rigid subcarrier. The component composite is separated into the plurality of component regions, wherein one semiconductor body is produced from the semiconductor layer sequence for each component region. The component regions are removed from the subcarrier.Type: ApplicationFiled: March 16, 2012Publication date: March 20, 2014Applicant: OSRAM Opto Semiconductors GmbHInventors: Heribert Zull, Korbinian Perzlmaier, Andreas Ploessl, Thomas Veit, Mathias Kampf, Jens Dennemarck, Bernd Bohm
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Patent number: 8664025Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.Type: GrantFiled: July 20, 2011Date of Patent: March 4, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel Richter, Frank Kuechenmeister
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Patent number: 8664089Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Patent number: 8658515Abstract: The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T2/T1 is 0.04 or more, wherein T1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.Type: GrantFiled: March 8, 2012Date of Patent: February 25, 2014Assignee: Nitto Denko CorporationInventors: Koichi Inoue, Miki Morita, Yuichiro Shishido
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Patent number: 8658436Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.Type: GrantFiled: April 19, 2011Date of Patent: February 25, 2014Assignee: Tokyo Electron LimitedInventors: Masahiro Yamada, Kenya Iwasaki, Hiroshi Nishikawa
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Patent number: 8652942Abstract: A method for manufacturing electronic parts, which is characteristic in that it permits reduction of contamination to the semi-cured adhesive layer formed on semiconductor wafer and the cohesive sheet used therein is superior in adhesiveness for example to the lead frame, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer by coating a pasty adhesive entirely over the rear face of a wafer and curing the pasty adhesive partially by radiation-ray irradiation or heating into the sheet shape, a fixing step of fixing the semi-cured adhesive layer formed on a wafer and a ring frame by bonding them to the cohesive layer of a cohesive sheet, a dicing step of dicing the wafer together with the semi-cured adhesive layer with a dicing blade into semiconductor chips, and a pick-up step of picking up the chips carrying the semi-cured adhesive layer from the cohesive layer of the cohesive sheet after radiation-ray irradiation, wherein the photopolymerization initiator in thType: GrantFiled: September 14, 2011Date of Patent: February 18, 2014Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Takeshi Saito, Tomomichi Takatsu
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Patent number: 8647966Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.Type: GrantFiled: June 9, 2011Date of Patent: February 11, 2014Assignee: National Semiconductor CorporationInventors: Ken Fei Lim, You Chye How, Kooi Choon Ooi
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Patent number: 8647901Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.Type: GrantFiled: June 11, 2008Date of Patent: February 11, 2014Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
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Publication number: 20140038357Abstract: A method and apparatus is described for forming and using a stiffener for the production of thinned integrated circuits. In one embodiment, a handle can be bonded to an integrated circuit wafer before the wafer is thinned. Electrical couplings such as mounting balls can be attached to the wafer. Individual dice can be singulated from the wafer by dicing through the wafer and the handle, producing a wafer/handle assembly. The wafer/handle assembly can be mounted to a printed circuit board before the handle is de-bonded.Type: ApplicationFiled: September 5, 2012Publication date: February 6, 2014Applicant: Apple Inc.Inventors: Shawn X. ARNOLD, Matthew E. LAST, Shankar S. PENNATHUR, Tan ZHANG
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Patent number: 8643177Abstract: A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the thinned wafer opposite the front side, and the back side layer may be configured to counter stress on the front side of the wafer including the plurality of integrated circuit devices thereon. After providing the back side layer, the plurality of integrated circuit devices may be separated. Related structures are also discussed.Type: GrantFiled: December 15, 2010Date of Patent: February 4, 2014Assignee: Amkor Technology, Inc.Inventors: Glenn A. Rinne, Kevin Engel, Julia Roe, Christopher John Berry
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Patent number: 8642445Abstract: Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.Type: GrantFiled: May 21, 2012Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Tse Chen, Hui-Min Huang, Chun-Cheng Lin, Chih-Chun Chiu, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 8637967Abstract: A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.Type: GrantFiled: November 15, 2010Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Markus Menath, Hermann Wendt, Berthold Schuderer
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Patent number: 8633086Abstract: A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.Type: GrantFiled: December 31, 2009Date of Patent: January 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Liang-Kai Han, Uway Tseng, Yuan-Chih Hsieh, Hung-Hua Lin
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Patent number: 8629043Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.Type: GrantFiled: November 16, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
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Patent number: 8628998Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.Type: GrantFiled: May 22, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Lin, Cheng-Jung Sung, Yu-Sheng Wang, Shiu-Ko JangJian, Wei-Ming You, Chih-Cherng Jeng, Ching-Hwanq Su
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Patent number: 8623744Abstract: A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.Type: GrantFiled: April 16, 2013Date of Patent: January 7, 2014Assignee: Sandia CorporationInventors: Thomas P. Swiler, Ernest J. Garcia, Kathryn M. Francis
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Patent number: 8618621Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.Type: GrantFiled: November 3, 2010Date of Patent: December 31, 2013Assignee: Infineon Technologies AGInventors: Klaus-Guenter Oppermann, Martin Franosch, Martin Handtmann
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Patent number: 8614139Abstract: The present invention provides a dicing film with a protecting film that enables to paste a dicing film to a semiconductor wafer without a shift in position while reducing a downtime. There is provided a dicing film with a protecting film in which a dicing film and a protecting film are laminated, wherein the difference between the transmittance of the protecting film and the transmittance of the dicing film with a protecting film at a portion of the dicing film where light for detecting a film transmits first is 20% or more in a wavelength of 600 to 700 nm.Type: GrantFiled: March 8, 2012Date of Patent: December 24, 2013Assignee: Nitto Denko CorporationInventors: Yuichiro Shishido, Takeshi Matsumura
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Publication number: 20130334713Abstract: The present disclosure relates to the field of fabricating microelectronic devices, wherein a microelectronic device substrate, such as a microelectronic wafer, may be thinned by a backgrinding process using a patterned adhesive tape that reduces slurry seepage and adhesive contamination while also reducing the potential of electrostatic discharge damage. The patterned adhesive tape may comprise a base film and adhesive material patterned on the base film such that an edge or periphery portion of the microelectronic device substrate may contact the adhesive material, but substantially no adhesive material contacts interconnectors formed on the microelectronic device substrate. The base film of the patterned adhesive tape may have an electrically conductive coating or layer, or may be electrically conductive itself to reduce the potential of electrostatic discharge damage during the backgrinding process.Type: ApplicationFiled: December 22, 2011Publication date: December 19, 2013Inventors: Dingying D. Xu, Wen Feng, Xavier Brun, Sandeep Iyer, Aaron Reichman
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Patent number: 8609513Abstract: A method for manufacturing a semiconductor device includes the steps of: preparing a combined wafer; obtaining a first intermediate wafer by forming an active layer; obtaining a second intermediate wafer by forming a front-side electrode on the first intermediate wafer; supporting the second intermediate wafer by adhering an adhesive tape at the front-side electrode side; removing the supporting layer while supporting the second intermediate wafer using the adhesive tape; forming a backside electrode on the main surfaces of SiC substrates exposed by the removal of the supporting layer; adhering an adhesive tape at the backside electrode side and removing the adhesive tape at the front-side electrode side so as to support the plurality of SiC substrates using the adhesive tape; and obtaining a plurality of semiconductor devices by cutting the SiC substrates with the SiC substrates being supported by the adhesive tape provided at the backside electrode side.Type: GrantFiled: July 21, 2011Date of Patent: December 17, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Taku Horii
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Patent number: 8609514Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.Type: GrantFiled: May 24, 2013Date of Patent: December 17, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
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Patent number: 8603351Abstract: An object to be processed is reliably cut along a line to cut. An object to be processed is irradiated with laser light while locating a converging point at the object, so as to form a modified region in the object along a line to cut. The object formed with the modified region is subjected to an etching process utilizing an etching liquid exhibiting a higher etching rate for the modified region than for an unmodified region, so as to etch the modified region. This can etch the object selectively and rapidly along the line to cut by utilizing a higher etching rate in the modified region.Type: GrantFiled: May 23, 2008Date of Patent: December 10, 2013Assignee: Hamamatsu Photonics K.K.Inventors: Takeshi Sakamoto, Hideki Shimoi, Naoki Uchiyama
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Patent number: 8586415Abstract: A dicing/die-bonding film including a pressure-sensitive adhesive layer (2) on a supporting base material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein a releasability in an interface between the pressure-sensitive adhesive layer (2) and the die-bonding adhesive layer (3) is different between an interface (A) corresponding to a work-attaching region (3a) in the die-bonding adhesive layer (3) and an interface (B) corresponding to a part or a whole of the other region (3b), and the releasability of the interface (A) is higher than the releasability of the interface (B). The dicing/die-bonding film is excellent in balance between retention in dicing a work and releasability in releasing its diced chipped work together with the die-bonding adhesive layer.Type: GrantFiled: December 14, 2011Date of Patent: November 19, 2013Assignee: Nitto Denko CorporationInventors: Takeshi Matsumura, Masaki Mizutani
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Patent number: 8587130Abstract: A die-sorting sheet includes a pressure-sensitive adhesive layer exposed on an outer periphery of the carrier sheet, and a base film exposed on a central area that is inside the outer periphery. A method for transporting a chip having an adhesive layer includes the steps of: providing the above die-sorting sheet that is fixed with a frame through the pressure-sensitive adhesive layer on the outer periphery; temporarily attaching a picked up chip through an adhesive layer thereof onto the base film exposed on the die-sorting sheet; and transporting the die-sorting sheet to a subsequent step while the chip is temporarily attached on the sheet through the adhesive layer.Type: GrantFiled: October 12, 2007Date of Patent: November 19, 2013Assignee: Lintec CorporationInventors: Akie Hamasaki, Shino Moritani, Mikio Komiyama
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Patent number: 8580615Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.Type: GrantFiled: February 17, 2012Date of Patent: November 12, 2013Assignee: Applied Materials, Inc.Inventors: Klaus Schuegraf, Seshadri Ramaswami, Michael R. Rice, Mohsen S. Salek, Claes H. Bjorkman
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Publication number: 20130295747Abstract: The present invention relates to an adhesive composition for a wafer processing film, a wafer processing film, and a semiconductor wafer processing method. In the semiconductor wafer processing process such as a dicing process or a back grinding process, a delaminating force with respect to a wafer to be attached may be effectively reduced to improve process efficiency and prevent the wafer from being warped or cracked.Type: ApplicationFiled: March 7, 2012Publication date: November 7, 2013Applicant: LG HAUSYS, LTD.Inventor: Jang-Soon Kim
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Patent number: 8573469Abstract: A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate.Type: GrantFiled: March 30, 2012Date of Patent: November 5, 2013Assignee: LuxVue Technology CorporationInventors: Hsin-Hua Hu, Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law
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Patent number: 8561664Abstract: An object of the present invention is to provide a pickup device that can securely peel a die or to provide a reliable die bonder or a pickup method using the pickup device. To achieve the object, the present invention is provided with a characteristic that when a die to be peeled out of plural dies (semiconductor chips) applied to a dicing film is thrust up and is peeled from the dicing film, the dicing film in a predetermined part in a circumference of the die is thrust up and a peeling starting point is formed, the dicing film in a part except the predetermined part is thrust up, and the die is peeled from the dicing film.Type: GrantFiled: September 13, 2010Date of Patent: October 22, 2013Assignee: Hitachi High-Tech Instruments Co., Ltd.Inventors: Hiroshi Maki, Naoki Okamoto
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Patent number: 8563361Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.Type: GrantFiled: July 12, 2012Date of Patent: October 22, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ping Huang, Lei Shi, Lei Duan, Yuping Gong
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Patent number: 8563402Abstract: A method includes providing a donor substrate comprising single crystal silicon and having a surface region, a cleave region, and a thickness of material to be removed between the surface region and the cleave region. The method also includes introducing through the surface region a plurality of hydrogen particles within a vicinity of the cleave region using a high energy implantation process. The method further includes applying compressional energy to cleave the semiconductor substrate and remove the thickness of material from the donor substrate.Type: GrantFiled: August 13, 2011Date of Patent: October 22, 2013Assignee: Silicon Genesis CorporationInventor: Francois J. Henley
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Patent number: 8563405Abstract: A method for manufacturing semiconductor device includes the following steps. First, a carrier substrate and a plurality of pieced segments of wafer are provided. Each of the pieced segments of wafer has an active surface and a back surface on opposite sides thereof. Further, there is at least a bonding pad disposed on the active surface. Next, an adhering layer is formed between the carrier substrate and the active surfaces of the pieced segments of wafer, so as to make the pieced segments of wafer adhere to the carrier substrate. Next, a through silicon via is formed in each of the pieced segments of wafer to electrically connect to the bonding pad correspondingly. Then, the pieced segments of wafer are separated from the carrier substrate.Type: GrantFiled: May 6, 2010Date of Patent: October 22, 2013Assignee: Ineffable Cellular Limited Liability CompanyInventor: Wen-Hsiung Chang
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Publication number: 20130273718Abstract: In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release substrate from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased and the wafer processing tape can be suppressed from being peeled off from the wafer ring during processes.Type: ApplicationFiled: October 12, 2011Publication date: October 17, 2013Applicant: HITACHI CHEMICAL COMPANY, LTD.Inventors: Kouhei Taniguchi, Takayuki Matsuzaki, Shinya Katou, Kouji Komorida, Michio Mashino, Tatsuya Sakuta, Rie Katou
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Patent number: 8557637Abstract: The disclosure provides a method for fabricating the flexible electronic devices, including: providing a first rigid carrier substrate and a second rigid carrier substrate, wherein at least one flexible electronic device is formed between the first rigid carrier substrate and the second rigid carrier substrate, and a plurality of first de-bonding areas, a first flexible substrate, the flexible electronic device, a second flexible substrate, a plurality of second de-bonding areas and the second rigid carrier substrate are formed on the first rigid carrier substrate; performing a first cutting step to cut through the first de-bonding areas; separating the first rigid carrier substrate from the first de-bonding areas; removing the first rigid carrier substrate from the first de-bonding areas; and performing a second cutting step to cut through the second de-bonding areas; separating and removing the second rigid carrier substrate from the second de-bonding areas.Type: GrantFiled: June 21, 2012Date of Patent: October 15, 2013Assignee: Industrial Technology Research InstituteInventors: Kuang-Jung Chen, Isaac Wing-Tak Chan
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Patent number: 8558371Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.Type: GrantFiled: January 21, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: JiSun Hong, Taeje Cho, Un-Byoung Kang, Hyuekjae Lee, Youngbok Kim, Hyung-sun Jang
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Publication number: 20130264686Abstract: One embodiment of a method of processing a semiconductor wafer having a peripheral portion includes providing external support structure and restraining radially inward displacement of the wafer peripheral portion with the external support structure.Type: ApplicationFiled: April 5, 2012Publication date: October 10, 2013Applicant: Texas Instruments IncorporatedInventors: Iriguchi Shoichi, Sada Hiroyuki, Yano Genki
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Publication number: 20130256843Abstract: A wafer sawing method comprises steps as follows: A wafer having a first surface and a second surface is firstly provided. An integrated circuit fabricating process is performed on the first surface of the wafer to define a first integrated circuit region and a periphery region surrounding around the first integrated circuit region, wherein the integrated circuit fabricating process includes an etching process used to form a first deep trench having an aspect ratio larger than 10 as well as a depth substantially ranging from one-third to two-third thickness of the wafer on the periphery region. Subsequently, an adhesive tape is disposed on the first surface at least covering the first integrated circuit region and the periphery region. A tensile stress is then imposed on the adhesive tape in order to make the wafer broken off along the first deep trench.Type: ApplicationFiled: April 3, 2012Publication date: October 3, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Hsin-Yu CHEN, Home-Been Cheng, Ching-Li Yang
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Patent number: 8541290Abstract: A method of fabricating a device by providing an auxiliary substrate having a metal nitride layer disposed thereon where the nitride layer has a nitrogen face and an opposite face and a dislocation density that is less than about 106, with the nitrogen face of the nitride layer facing the auxiliary substrate; depositing at least one epitaxial nitride layer on the exposed opposite face of the nitride layer of the structure; depositing a further metal layer over at least a portion of the epitaxial nitride layer(s); bonding a final substrate on the deposited metal layer; and removing the auxiliary substrate to form the device from the final substrate and deposited layers. Preferably, the device that is formed includes a LED or laser.Type: GrantFiled: June 7, 2011Date of Patent: September 24, 2013Assignee: SoitecInventors: Fabrice Letertre, Bruce Faure
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Patent number: 8541291Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.Type: GrantFiled: June 14, 2011Date of Patent: September 24, 2013Assignee: Ultratech, Inc.Inventors: Bruce K. Furman, Jae-Woong Nah
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Patent number: 8541289Abstract: The present invention relates to a dicing die bonding film, which is able to maintain good workability and reliability in any semiconductor packaging process, such as adhesive property, gap filling property and pick-up property, while controlling burr incidence in a dicing process and thus contamination of die, and a dicing method. Specifically, the present invention is characterized by optimizing tensile characteristics of the dicing die bonding film, or carrying out the dicing on the parts of the die bonding film in the dicing process and separating it through an expanding process. Therefore, the present invention may regulate physical properties of films so as to have the maximized adhesive property, pick-up property and gap filling property without any specific restriction, while controlling burr incidence in the dicing process and contamination of die. As a result, workability and reliability in a packaging process may be excellently maintained.Type: GrantFiled: October 15, 2008Date of Patent: September 24, 2013Assignee: LG Chem, Ltd.Inventors: Jong Wan Hong, Jang Soon Kim, Hyo Soon Park, Hyun Jee Yoo, Dong Han Kho, Hyo Sook Joo
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Patent number: 8536445Abstract: A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell comprising providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on said substrate having a first band gap; forming a second solar subcell over said first subcell having a second band gap smaller than said first band gap; and forming a grading interlayer over said second subcell having a third band gap larger than said second band gap forming a third solar subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mismatched with respect to said second subcell.Type: GrantFiled: June 2, 2006Date of Patent: September 17, 2013Assignee: Emcore Solar Power, Inc.Inventors: Arthur Cornfeld, Mark A. Stan
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Patent number: 8536023Abstract: A method of manufacturing semiconductor wafers, the method including: providing a donor wafer including a semiconductor substrate; performing a lithography step and processing the donor wafer; and performing at least two subsequent steps of layer transfer out of the donor wafer, each layer transfer step producing a transferred layer, where each of the transferred layers had been affected by the lithography step, and where each of the transferred layer includes a plurality of transistors with side gates, and where the layer transfer includes an ion-cut, the ion-cut including an ion implant thru the transistors.Type: GrantFiled: November 22, 2010Date of Patent: September 17, 2013Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20130234313Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Cooper Wainerdi, Luigi Colombo, John Paul Tellkamp, Robert Reid Doering
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Publication number: 20130230974Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.Type: ApplicationFiled: March 6, 2013Publication date: September 5, 2013Applicant: Plasma-Therm LLCInventors: Linnell Martinez, David Pays-Volard, Chris Johnson, David Johnson, Russell Westerman
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Publication number: 20130230972Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.Type: ApplicationFiled: February 11, 2013Publication date: September 5, 2013Applicant: Plasma-Therm LLCInventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman
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Publication number: 20130230973Abstract: The present invention provides a method for plasma dicing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing a work piece onto the work piece support, said work piece having a support film, a frame and the substrate; loading the work piece onto the work piece support; applying a tensional force to the support film; clamping the work piece to the work piece support; generating a plasma using the plasma source; and etching the work piece using the generated plasma.Type: ApplicationFiled: February 14, 2013Publication date: September 5, 2013Applicant: Plasma-Therm LLCInventors: Rich Gauldin, Chris Johnson, David Johnson, Linnell Martinez, David Pays-Volard, Russell Westerman