Having A Perfecting Coating Patents (Class 438/465)
  • Patent number: 11183469
    Abstract: A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: November 23, 2021
    Assignee: Kioxia Corporation
    Inventors: Yusuke Akada, Rina Kadowaki, Hiroyuki Maeda
  • Patent number: 10950491
    Abstract: A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 16, 2021
    Assignees: Soitec, COMMISSARIAT Á L'ÈNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frederic Mazen, Damien Massy, Shay Reboh, Francois Rieutord
  • Patent number: 10923571
    Abstract: A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first conductivity type, formed at a surface layer portion of the semiconductor layer, a second impurity region of a second conductivity type, formed at a surface layer portion of the first impurity region and defining the active region, and a well region of the second conductivity type, formed along a periphery of the second impurity region at the surface layer portion of the first impurity region and having an inner side edge portion positioned at the second impurity region side, and an outer side edge portion positioned at an opposite side with respect to the second impurity region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the inner side edge portion.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: February 16, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10276440
    Abstract: A method for temporarily protecting a semiconductor device wafer during processing includes preparing a solution including poly(vinyl alcohol) and water, coating the device wafer with the prepared solution, baking the coated device wafer to form a protective layer, processing the baked device wafer, and dissolving the protective layer from the processed wafer with a solvent at a temperature not less than 65° C. The solvent includes water. The baking is at a temperature from 150° C. to 170° C. The protective layer remains on the baked device wafer during processing. The poly(vinyl alcohol) has a degree of hydrolysis greater than or equal to 93%.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 30, 2019
    Assignee: Honeywell International Inc.
    Inventors: Desaraju Varaprasad, Ronald R. Katsanes
  • Patent number: 9589830
    Abstract: A method for transferring a useful layer onto a support includes the following processes: formation of a fragilization plane through the implantation of light species into a first substrate in such a way as to form a useful layer between this plane and a surface of the first substrate; application of the support onto the surface of the first substrate to form an assembly to be fractured having two exposed sides; thermal fragilization treatment of the assembly to be fractured; and initiation and self-sustained propagation of a fracture wave in the first substrate along the fragilization plane. At least one of the sides of the assembly to be fractured is in close contact, over a contact zone, with an absorbent element suitable for capturing and dissipating acoustic vibrations emitted during the initiation and/or propagation of the fracture wave.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 7, 2017
    Assignees: Soitec, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Damien Massy, Frederic Mazen, Francois Rieutord
  • Patent number: 9318386
    Abstract: A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface of the wafer. The molding compound covers a center region of the wafer, and leaves an edge ring of the wafer not covered. An opening is formed to extend from the front surface of the wafer into the wafer, wherein the opening is in the edge ring of the wafer. A backside grinding is performed on the wafer until the opening is revealed through a back surface of the wafer. The method further includes determining a position of a scribe line of the wafer using the opening as an alignment mark, and sawing the wafer from a backside of the wafer by sawing through the scribe line.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9108269
    Abstract: A method for manufacturing a light-absorbing substrate having a surface with depressions and projections comprises a first step of irradiating a substrate with a laser light so as to form a plurality of modified regions arranged two-dimensionally along a surface of the substrate within the substrate and cause at least one of each modified region and a fracture generated from the modified region to reach the surface of the substrate and a second step of etching the surface of the substrate after the first step so as to form depressions and projections on the surface of the substrate.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 18, 2015
    Assignee: HAMAMATSU PHOTONICS K. K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 9105706
    Abstract: A semiconductor device fabrication method includes preparing a semiconductor wafer having a plurality of chip areas formed with semiconductor elements and a scribe area having a dicing area in said scribe area for separating said plurality of chip areas, wherein in said scribe area a groove forming area is defined to surround each chip area at a position outside of the dicing area, disposing a multilayer wiring structure including dummy wirings above said semiconductor wafer, said multilayer wiring structure having interlayer insulating films and wiring layers alternately formed, forming a cover layer including a passivation layer, said cover layer covering said multilayer wiring structure, and forming a groove in each said groove forming area, said groove surrounding each of said plurality of chip areas and extending from a surface of said semiconductor wafer and at least through said passivation layer.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: August 11, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Satoshi Otsuka
  • Patent number: 9064785
    Abstract: An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 23, 2015
    Assignee: Freesacle Semiconductor, Inc.
    Inventors: Bradley P. Smith, Edward O. Travis
  • Patent number: 9048198
    Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 2, 2015
    Assignee: IMEC
    Inventors: Maria Op De Beeck, Eric Beyne, Philippe Soussan
  • Publication number: 20150132925
    Abstract: A wafer processing method including a mask forming step of forming a mask for covering a region corresponding to each device on a functional layer formed on the front side of a substrate constituting a wafer, a groove forming step of spraying a fluid containing abrasive grains against the front side of the wafer to thereby form a groove for dividing the functional layer along each street, and an etching step of performing dry etching from the front side of the wafer to thereby form an etched groove along each street. Accordingly, it is possible to prevent that the functional layer may be separated to cause damage to each device. Furthermore, a wide area of the wafer can be processed at a time, so that the productivity can be improved.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 14, 2015
    Inventors: Sakae Matsuzaki, Hiroyuki Takahashi
  • Patent number: 9006051
    Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Masayuki Kajiwara, Masataka Nakada, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 8999818
    Abstract: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Takahashi, Daiki Yamada, Yohei Monma, Hiroki Adachi, Shunpei Yamazaki
  • Patent number: 8999816
    Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
  • Patent number: 8993414
    Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Brad Eaton, Saravjeet Singh, Wei-Sheng Lei, Madhava Rao Yalamanchili, Tong Liu, Ajay Kumar
  • Patent number: 8980727
    Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 8962451
    Abstract: In a wafer processing method, grooves are formed on the front side of a wafer along all division lines extending in a first direction and along all division lines extending in a second direction perpendicular to the first direction. Each groove has a depth corresponding to a finished thickness of each device in the wafer. The wafer is cut into four sectorial wafer quarters. A protective member is provided on the front side of each wafer quarter; and the back side of the wafer quarter is ground to reduce the thickness of the wafer quarter to the finished thickness until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 24, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8956957
    Abstract: In a wafer processing method, a wafer is cut along a division line extending in a first direction through the center of the wafer and along a division line extending in a second direction through the center of the wafer, thereby generating four sectorial wafer quarters. Grooves are formed on the front side of each wafer quarter along other division lines extending in a grid, each groove having a depth corresponding to a finished thickness of each device formed on the wafer quarter. A protective member is provided on the front side of each wafer quarter; and the wafer quarter is held through the protective member on a chuck table. The back side is then ground to reduce the thickness of the wafer quarter until the grooves are exposed to the back side of the wafer quarter, thereby dividing the wafer quarter into the individual devices.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 17, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8956956
    Abstract: A wafer processing method includes: a protective member providing step of providing a protective member on the front side of a wafer; a wafer quarter generating step of cutting the wafer along the division line extending in a first direction through the center of the wafer and along the division line extending in a second direction perpendicular to the first direction through the center of the wafer, thereby generating four sectorial wafer quarters; a back grinding step of grinding the back side of each wafer quarter to reduce the thickness of the wafer quarter; a frame providing step of supporting the wafer quarter through an adhesive tape to an annular frame; and a wafer quarter dividing step of fully cutting the wafer quarter along all of the division lines extending in the first and second directions, thereby dividing the wafer quarter into the individual devices.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 17, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8951890
    Abstract: Provided is an actinic-ray- or radiation-sensitive resin composition including (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, (B) an onium salt containing a nitrogen atom in its cation moiety, which onium salt when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, and (C) a compound that when exposed to actinic rays or radiation, generates an acid, the compound being any of compounds of general formulae (1-1) and (1-2) below.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 10, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Kei Yamamoto, Mitsuhiro Fujita, Tomoki Matsuda
  • Patent number: 8940619
    Abstract: Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Saravjeet Singh, Todd Egan, Ajay Kumar, Seshadri Ramaswami
  • Patent number: 8928120
    Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 8916403
    Abstract: A method for producing a plurality of optoelectronic semiconductor chips includes providing a carrier wafer having a first surface and a second surface opposite the first surface, wherein a plurality of individual component layer sequences spaced apart from one another in a lateral direction are applied on the first surface, the component layer sequences being separated from one another by separation trenches; introducing at least one crystal imperfection in at least one region of the carrier wafer which at least partly overlaps a separation trench in a vertical direction; singulating the carrier wafer along the at least one crystal imperfection into individual semiconductor chips.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: December 23, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Ewald K. M. Günther, Mathias Kämpf, Jens Dennemarck, Nikolaus Gmeinwieser
  • Publication number: 20140361443
    Abstract: An object of the present invention is to provide a method of manufacturing a flip-chip type semiconductor device with a simplified process, in which various types of information are supplied in a visually recognizable manner. The present invention relates to a method of manufacturing a flip-chip type semiconductor device comprising: a step A of laminating on a semiconductor wafer a film for the backside of a flip-chip type semiconductor, in which the film is to be formed on the backside of a semiconductor element that is flip-chip connected onto an adherend; a step B of dicing the semiconductor wafer; and a step C of laser marking the film for the backside of a flip-chip type semiconductor, wherein the film for the backside of a flip-chip type semiconductor in the step C is uncured.
    Type: Application
    Filed: January 15, 2013
    Publication date: December 11, 2014
    Inventors: Goji Shiga, Fumiteru Asai, Naohide Takamoto
  • Patent number: 8900998
    Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: December 2, 2014
    Assignee: University of Windsor
    Inventors: Mordechay Schlesinger, Robert Andrew Petro
  • Patent number: 8895409
    Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Trent S. Uehling
  • Patent number: 8889526
    Abstract: A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: November 18, 2014
    Assignee: Advanced Inquiry Systems, Inc.
    Inventor: Morgan T. Johnson
  • Patent number: 8889525
    Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yoshimaro Fujii, Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama
  • Patent number: 8883615
    Abstract: Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming an underfill material layer between and covering metal pillar/solder bump pairs of the integrated circuits. The method also involves forming a mask layer on the underfill material layer. The method also involves laser scribing mask layer and the underfill material layer to provide scribe lines exposing portions of the semiconductor wafer between the integrated circuits. The method also involves removing the mask layer. The method also involves, subsequent to removing the mask layer, plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the second insulating layer protects the integrated circuits during at least a portion of the plasma etching.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: James Matthew Holden, Wei-Sheng Lei, James S. Papanu, Ajay Kumar
  • Patent number: 8871614
    Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-joon Kim, Hyeoung-won Seo
  • Patent number: 8865570
    Abstract: A method of making an edge-reinforced microelectronic element is disclosed. The steps include mechanically cutting along dicing lanes of a substrate at least partially through a thickness thereof to form a plurality of edge surfaces extending away from a front surface thereof and forming a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces and extends onto the front surface. The front surface may have a plurality of contacts thereat and the substrate may embody a plurality of microelectronic elements.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: October 21, 2014
    Assignee: Invensas Corporation
    Inventor: Ilyas Mohammed
  • Patent number: 8865566
    Abstract: Multiphoton absorption is generated, so as to form a part which is intended to be cut 9 due to a molten processed region 13 within a silicon wafer 11, and then an adhesive sheet 20 bonded to the silicon wafer 11 is expanded. This cuts the silicon wafer 11 along the part which is intended to be cut 9 with a high precision into semiconductor chips 25. Here, opposing cut sections 25a, 25a of neighboring semiconductor chips 25, 25 are separated from each other from their close contact state, whereby a die-bonding resin layer 23 is also cut along the part which is intended to be cut 9. Therefore, the silicon wafer 11 and die-bonding resin layer 23 can be cut much more efficiently than in the case where the silicon wafer 11 and die-bonding resin layer 23 are cut with a blade without cutting a base 21.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 21, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama, Ryuji Sugiura
  • Patent number: 8859398
    Abstract: Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tobias Letz, Frank Feustel, Kai Frohberg
  • Patent number: 8835283
    Abstract: A fabrication method for producing semiconductor chips with enhanced die strength comprises following steps: forming a semiconductor wafer with enhanced die strength by comprising the substrate, the active layer on the front side of the substrate and the backside metal layer on the backside of the substrate, wherein at least one integrated circuit forms in the active layer; forming a protection layer on a front side of the semiconductor wafer; dicing the semiconductor wafer by at least one laser dicing process and removing the laser dicing residues and removing said protection layer by at least one etching process, whereby plural semiconductor chips with enhanced die strength are produced, and wherein the backside metal layer of said semiconductor chip fully covers the backside of said semiconductor chip after dicing.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 16, 2014
    Assignee: WIN Semiconductors Corp.
    Inventor: Chang-Hwang Hua
  • Patent number: 8828848
    Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ying-Da Wang, Li-Chung Kuo, Szu Wei Lu
  • Patent number: 8822275
    Abstract: A composite wafer includes a molded wafer and a second wafer. The molded wafer includes a plurality of first components, and the second wafer includes a plurality of second components. The second wafer is combined with the molded wafer to form the composite wafer. At least one of the first components is aligned with at least one of the second components to form a multi-component element. The multi-component element is singulatable from the composite wafer.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 2, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael Renne Ty Tan, Georgios Panotopoulos, Paul Kessler Rosenberg, Sagi Varghese Mathai, Wayne Victor Sorin, Susant K Patra
  • Patent number: 8802545
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
  • Patent number: 8802507
    Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 12, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
  • Patent number: 8802543
    Abstract: A laser processing method which can highly accurately cut objects to be processed having various laminate structures is provided. An object to be processed comprising a substrate and a laminate part disposed on the front face of the substrate is irradiated with laser light L while a light-converging point P is positioned at least within the substrate, so as to form a modified region due to multiphoton absorption at least within the substrate, and cause the modified region to form a starting point region for cutting. When the object is cut along the starting point region for cutting, the object 1 can be cut with a high accuracy.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 12, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Patent number: 8796154
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: August 5, 2014
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
  • Patent number: 8785299
    Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 8778806
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: July 15, 2014
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
  • Patent number: 8772136
    Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chine-Li Wang, Chun-Yen Chen, Wei-Hua Fang, Hung-Hsien Chang, Yung-Chin Yen
  • Patent number: 8772133
    Abstract: The various aspects comprise methods and devices for processing a wafer. An aspect of this disclosure includes a wafer. The wafer comprises a plurality of die regions; a plurality of kerf regions between the plurality of die regions; and a metallization area on the plurality of die regions.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Martin Zgaga, Karl Adolf Mayer, Gudrun Stranzl
  • Patent number: 8765578
    Abstract: A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. La Tulipe, Jr., Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
  • Publication number: 20140170836
    Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gunther Mackh, Gerhard Leschik, Adolf Koller, Harald Seidl
  • Patent number: 8728866
    Abstract: A method for manufacturing a semiconductor device comprises: forming a circuit pattern and a first metal film on a first major surface of a body wafer; forming a through-hole penetrating the body wafer from a second major surface of the body wafer and reaching the first metal film; forming a second metal film on a part of the second major surface of the body wafer, on an inner wall of the through-hole, and on the first metal film exposed in the through-hole; forming a recess on a first major surface of a lid wafer; forming a third metal film on the first major surface of the lid wafer including inside the recess of the lid wafer; with the recess facing the circuit pattern, and the first metal film contacting the third metal film, joining the lid wafer to the body wafer; and dicing the joined body wafer and lid wafer along the through-hole.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ko Kanaya, Yoshihiro Tsukahara, Shinsuke Watanabe
  • Patent number: 8722514
    Abstract: In one embodiment, a semiconductor device includes a glass substrate, a semiconductor substrate disposed on the glass substrate, and a magnetic sensor disposed within and/or over the semiconductor substrate.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: May 13, 2014
    Assignee: Infineon Technologies AG
    Inventors: Carsten von Koblinski, Volker Strutz, Manfred Engelhardt
  • Patent number: 8716066
    Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Leo M. Higgins, III
  • Patent number: 8691666
    Abstract: A method for producing a chip (13) in which a die bonding adhesive layer (24) and a wafer (1) are laminated on a close-contact layer (31) of a fixing jig (3), the chip is formed by completely cutting the wafer and the die bonding adhesive layer and then the chip is picked up together with the die bonding adhesive layer from the fixing jig by deforming the close-contact layer of the fixing jig. In the method the fixing jig is provided with the close-contact layer and a jig base (30) that is provided with a plurality of protrusions (36) on one side and a sidewall (35) at the outer circumference section of the one side. The close-contact layer is laminated on the surface of the jig base provided with the protrusions and is bonded on the upper surface of the sidewall. On the surface of the jig base provided with the protrusions, a partitioned space is formed by the close-contact layer, the protrusions, and the sidewall.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: April 8, 2014
    Assignee: Lintec Corporation
    Inventors: Takeshi Segawa, Naofumi Izumi