Abstract: A buried oxide layer of an SOI substrate beneath a structure electrically isolated from the rest of a semiconductor device is made to break down so as to open a bias path for the substrate through the structure. It then suffices to connect the electrical ground of the semiconductor device to this bias path so that the ions flow away into the substrate during a focused ion beam treatment of the semiconductor device.

Abstract: A method of hydrogenating a poly-silicon layer is disclosed, which is used to improve characteristics of a thin film transistor (TFT) having a poly-silicon thin film. In the method, the poly-silicon layer is first subject to a plasma pre-process and then a hydrogenating process is undertaken thereon where a hydrogen-containing silicon-based compound is deposited over the poly-silicon layer having being pre-processed by the plasma and thermal treated. As such, the hydrogen atoms in the hydrogen-containing silicon-based compound may diffuse into the poly-silicon layer and the hydrogen atoms at a surface of the poly-silicon layer may further diffuse into where need to be filled to promote the hydrogenation effect of the poly-silicon layer, i.e., the hydrogenation may be completed in a shorter time.

Abstract: The present invention provides an improved surface P-channel transistor and a method of making the same. A preferred embodiment of the method of the present invention includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the method of the present invention does not require nitrogen implantation through the polysilicon layer overlying the gate oxide and provides a surface P-channel transistor having a polysilicon electrode free of nitrogen and a hardened gate oxide layer characterized by a large concentration of nitrogen at the polysilicon electrode/gate oxide interface and a small concentration of nitrogen at the gate oxide/semiconductor substrate interface.

Abstract: Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.

Abstract: Disclosed is a method for forming a bottle shaped trench. The method of the present invention includes steps of providing a substrate; forming a plurality of operation layers on the substrate; forming a photoresist layer on the operation layers to define a predetermined position; forming a trench according to the predetermined position; implanting predetermined ions, which reduces oxidizing rate of the sidewall of the trench, into the upper sidewall of the trench; oxidizing the sidewall of the trench to form an oxide layer, in which the portion of the oxide layer formed at the portion of the sidewall implanted with the ions is thin, while the portion of the oxide layer formed at the portion of the sidewall not implanted with the ions is thick; and removing the oxide layer to form a bottle shaped trench.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.

Abstract: The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

Abstract: A method is provided for fabricating molecular electronic devices comprising at least a bottom electrode and a molecular switch film on the bottom electrode. The method includes forming the bottom electrode by a process including: cleaning portions of the substrate where the bottom electrode is to be deposited; pre-sputtering the portions; depositing a conductive layer on at least the portions; and cleaning the top surface of the conductive layer. Advantageously, the conductive electrode properties include: low or controlled oxide formation (or possibly passivated), high melting point, high bulk modulus, and low diffusion. Smooth deposited film surfaces are compatible with Langmuir-Blodgett molecular film deposition. Tailored surfaces are further useful for SAM deposition. The metallic nature gives high conductivity connection to molecules. Barrier layers may be added to the device stack, i.e., Al2O3 over the conductive layer.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: A method of bonding a germanium (Ge) wafer to a semiconductor wafer. A Ge wafer having a cleaving plane defined by ion implantation is provided. A surface activation on at least one surface of the Ge wafer is performed. A semiconductor wafer is provided. A surface activation on at least one surface of the semiconductor wafer is performed. The Ge wafer is bonded to the semiconductor wafer to form a bonded wafer pair. A first annealing is performed to the bonded wafer pair. The first annealing occurs at a temperature approximately between 50-100° C. A second annealing is performed to the bonded wafer pair. The second annealing occurs at a temperature approximately between 110-170° C. The second annealing cleaves the Ge wafer at the cleaving plane.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

Abstract: A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.

Abstract: The present invention provides an improved surface P-channel transistor and a method of making the same. A preferred embodiment of the method of the present invention includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the method of the present invention does not require nitrogen implantation through the polysilicon layer overlying the gate oxide and provides a surface P-channel transistor having a polysilicon electrode free of nitrogen and a hardened gate oxide layer characterized by a large concentration of nitrogen at the polysilicon electrode/gate oxide interface and a small concentration of nitrogen at the gate oxide/semiconductor substrate interface.

Abstract: The present invention, in one embodiment, relates to a process for fabricating a semiconductor device that is less susceptible to performance degradation caused by hydrogen contamination. The method includes the steps for removing unwanted hydrogen bonds by exposing the hydrogen bonds to ultraviolet radiation sufficient to break the bond and annealing in an atmosphere comprising at least one gas having at least one atom capable of forming bonds that replace the hydrogen bonds.

Abstract: Within a Czochralski method for fabricating a silicon substrate wafer which employs pulling a silicon monocrystal ingot from a silicon melt and slicing therefrom the silicon substrate wafer, at least one of: (1) the silicon melt has introduced therein a halogen getter material from an extrinsic source; and (2) the silicon substrate wafer is further treated with a plasma. In accord with the method, the silicon substrate wafer is provided with attenuated defects.

Abstract: A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process surface to include exposure of the process surface to a hydrofluorocarbon containing plasma; and heating the process surface according to a temperature profile to reduce a fluorine contamination level.

Abstract: A structure for doping of III-V compounds is provided. The structure is a multi-layered structure in which layers of dopant are alternated with layers of initially undoped III-V compound. Dopant diffuses from the layers of dopant into the layers of III-V compound. The structure does not facilitate the introduction of impurities into the III-V compound during the diffusion of the dopant.

Abstract: Catalytic elements such as Ni are intentionally combined with defects that remain inside of a semiconductor substrate or thin film so that the energy state of the defects comes to a stable state. In this state, a heat treatment is conducted in an atmosphere containing halogen element or XV element, and gettering is conducted in such a manner that the catalytic element is taken in an oxide film. The bonds which are divided by separating the catalytic element are recombined through a heat treatment, thereby being capable of improving crystalline property of the semiconductor substrate or thin film remarkably.

Abstract: The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a mask is formed over a monocrystalline silicon substrate. A neutral-conductivity-type dopant is implanted through an opening in the mask and into a section of the substrate to produce a damage region. A first boundary extends around the damage region. The masking layer is removed, and epitaxial silicon is formed over the substrate. An array of devices is formed to be supported by the epitaxial silicon. The array is bounded by a second boundary. The first boundary extends less than or equal to 100 microns beyond the second boundary.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: The present invention is intended to detect defects in a circuit pattern formed on a semiconductor wafer by a circuit pattern forming process, to facilitates the extraction and observation of the defects, to improve the accuracy of analysis of the causes of the defects, and to determine the causes of the defects and to take measures to eliminate the causes of the defects in a greatly reduced time after the formation of the defects. A method of inspecting a circuit pattern for defects and analyzing defects, comprising locating a defect in a circuit pattern formed on a wafer by using an electron beam, specifying a chip having the defect on the basis of position data on the defect, cutting out the chip from the semiconductor wafer, thinning a portion of the chip to form a thin portion, and observing the thin portion of the chip under a transmission electron microscope to determine the causes of the defect.

Abstract: To provide a method of removing a catalyst element from a crystalline silicon film obtained by solid phase growth using the catalyst element promoting crystallization, phosphorus is implanted selectively to the crystalline silicon film having the catalyst element whereby a portion of the silicon film implanted with phosphorus is made amorphous, and when a thermal annealing treatment is performed and the silicon film is heated, the catalyst element is moved to an amorphous portion implanted with phosphorus having large getting capacity by which the concentration of the catalyst element in the silicon film is lowered and a semiconductor device is fabricated by using the silicon film.

Abstract: A method is disclosed for removal of free halogen from a semiconductor device insulating layer, in particular, a halogen-containing polymer insulating layer. The free halogen is removed by contacting the insulating material with hydrogen ions under conditions which generate gaseous hydrogen halide which is then removed. A semiconductor device containing such treated insulating materials is also disclosed. The invention is particularly useful in removing free fluorine from fluorinated polymer insulating layers.

Abstract: A method for fabricating an ultra-shallow semiconductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Abstract: A process for forming a non-porous dielectric diffusion barrier layer on etched via and trench sidewall surfaces in a layer of porous low k dielectric material comprises exposing such etched surfaces to a plasma formed from one or more gases such as, for example, O2; H2; Ar; He; SiH4; NH3; N2; CHxFy, where x=1-3 and y=4-y; H2O; and mixtures of same, for a period of time sufficient to form from about 1 nanometer (nm) to about 20 nm of the non-porous dielectric diffusion barrier layer which prevents adsorption of moisture and other process gases into the layer of porous low k dielectric material, and prevents degassing from the porous low k dielectric material during subsequent processing.

Abstract: A method for forming a silicon on insulator substrate includes the step of dissociating a plasma of molecules including at least any one of oxygen and nitrogen to obtain ions. The ions are accelerated by passage through gaps between acceleration electrodes at a predetermined acceleration energy for irradiation of the accelerated ions onto a silicon substrate which is heated to form an insulation film within the silicon substrate.

Abstract: Within a Czochralski method for fabricating a silicon substrate wafer which employs pulling a silicon monocrystal ingot from a silicon melt and slicing therefrom the silicon substrate wafer, at least one of: (1) the silicon melt has introduced therein a halogen getter material from an extrinsic source; and (2) the silicon substrate wafer is further treated with a plasma. In accord with the method, the silicon substrate wafer is provided with attenuated defects.

Abstract: In manufacturing compound semiconductor device, a plasma treatment is carried out by exposing surface of compound semiconductor material including AlAs or InAs exposing in atmosphere at manufacturing process in plasma of gas including any of P, N, H, and Ar at substrate temperature of less than 200° C. Desirably a second plasma treatment is carried out by exposing said compound semiconductor material in plasma of gas including p at higher substrate temperature continuously after said plasma treatment without taking the substrate out in air.

Abstract: A method of preparing a semiconductor wafer having a integrated circuits formed on it that have pads formed of copper includes the steps of removing oxide from the copper pads and then the vacuum packing the wafer in a shock-proof container. The oxide may be removed from the copper pads in a number of ways. A first way includes cleaning the wafer in an alkaline solution, performing acid neutralization on the cleaned wafer, and then drying the wafer. A second way includes cleaning the wafer with an acid solution, rinsing the acid cleaned wafer with water, applying an anti-oxidant activator to the surface of the copper pads, rinsing the wafer with water after the application of the anti-oxidant activator, and then drying the water rinsed wafer. Yet a third way includes plasma cleaning the copper pads using a combination of about 5-10% Hydrogen and about 90-95% Argon and then sputtering a very thin layer of aluminum on a surface of the copper pads. The layer of aluminum has a thickness of about 1-5 nanometers.

Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.

Abstract: A semiconductor product includes a silicon-containing functional layer, an insulating layer made of silicon dioxide, and a stop layer made of silicon nitride, which is disposed between the functional layer and the insulating layer and bonds the functional layer to the insulating layer. The stop layer acts as a diffusion barrier between the functional layer and the insulating layer. A method for fabricating this product starts out with a blank part having the functional layer and the insulating layer. The stop layer is formed by implanting nitrogen into the insulating layer and subsequently heat treating the blank part. As a result of the heat treatment the nitrogen diffuses to the functional layer where it bonds to the silicon in order to form the stop layer.

Abstract: A process is provided for producing coated synthetic bodies during which, before the coating, the surface to be coated is subjected to a pretreatment in an excited gas atmosphere. The surface is then coated. The gas atmosphere is predominantly formed of a noble gas and nitrogen and/or hydrogen, and the ionic energy in the gas atmosphere and in the are of the surface to be coated is not more than 50 eV. The ionic energy is selected to be not more than 20 eV, preferable not more than 10 eV. The gas atmosphere is excited by means of a plasma discharge or by means of UV radiation.

Abstract: There is prepared a wafer (10) having a gettering capability such as PBS wafer having deposition of polysilicon on the back surface thereof, IG wafer containing oxygen precipitates therein, or the like. An element separation silicon oxide film (2) is formed on the wafer (10), and a first silicon oxide film (3) is formed on the wafer (10). Then the wafer (10) is gradually cooled to a low temperature, or the wafer (10) is cooled to a low temperature and then kept at the low temperature for a fixed time. Thereafter, the first silicon oxide film (3) is removeed from the wafer (10) and then the wafer (30) is cleaned. Thereafter, a gate silicon oxide film (4) and a gate electrode (5) are formed. Subsequently, ion implantation to form a source (6) and a drain (7) and a heat treatment to activate implanted impurities are performed to form a basic MOS transistor.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: The present invention provides an improved surface P-channel transistor and a method of making the same. A preferred embodiment of the method of the present invention includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the method of the present invention does not require nitrogen implantation through the polysilicon layer overlying the gate oxide and provides a surface P-channel transistor having a polysilicon electrode free of nitrogen and a hardened gate oxide layer characterized by a large concentration of nitrogen at the polysilicon electrode/gate oxide interface and a small concentration of nitrogen at the gate oxide/semiconductor substrate interface.

Abstract: Compound semiconductor light emitting devices capable of suppressing the surface state density on the facets of semiconductor light emitting devices such as semiconductor lasers for a long time and stable operating even when the passivation layer diffuses can be easily obtained. Compound semiconductor light emitting devices with an emission wavelength of &lgr; (nm) wherein a first conduction type of clad layer, an active layer and a second conduction type of clad layer are grown on a substrate and two facets are opposite to each other so as to form a cavity, characterized in that said active layer is transparent to the emission wavelength in the vicinities of the facets and that the surfaces of the first conduction type of clad layer, active layer and second conduction type of clad layer forming said facets are each coated with a passivation layer.

Abstract: A method for implanting a substrate face using a plasma processing apparatus (10). The method includes providing a substrate (e.g., wafer, panel) (22) on a face of a susceptor. The substrate has an exposed face, which has a substrate diameter that extends from a first edge of the substrate to a second edge of the substrate across a length of the substrate. The method also includes forming a plasma sheath (26) around the face of the substrate. The plasma sheath has a dark space distance “D” that extends in a normal manner from the exposed face to an edge of the plasma sheath. The dark space distance and the substrate diameter comprise a ratio between the dark space distance and the substrate diameter. The ratio is about one half and less, which provides a substantially uniform implant.

Abstract: A method is disclosed for improving the bonding strength of wire bonds on semiconductor chips. Aluminum-silicon-copper is employed as the metal for wire bonding-pads. Openings are formed in the passivation layer over the bonding-pads. The exposed metal in the openings is treated with a fluorine containing F-plasma. A thin passivation film, with C, F, and O content is formed over the metal bonding pads. This protective film prevents the formation of pitting and staining of the bonding-pads when the wafer is subjected to repeated developing solutions during the color filter process performed for the CMOS image sensors, for example. Consequently, the wire bonds formed during the packaging of the chips are stronger and more reliable.

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

Abstract: In a method of manufacturing a semiconductor device including a semiconductor element formed on a semiconductor substrate, an SiOF film is formed at least on the top surfaces of metal wirings under condition that an in-chamber pressure is 5 mTorr or lower. The SiOF film can thus be buried into a space between the metal wirings without causing any void and the capacitance between the wirings can be prevented from increasing, while preventing the metal wirings from being damaged and preventing the aspect ratio from increasing.

Abstract: A system and method for using a nitrous oxide plasma treatment to eliminate defects at an interface between a stop layer and an integral layered dielectric. The system and method provide a reliable and simplified technology that eliminates the small bubble-like defects that can be common to thin nitride layers. The system includes a plasma device and a processing chamber. The method encompasses the steps of preparing a first integral layered dielectric on a substrate before depositing a stop layer thereupon. A plasma gas is then ionized. Preferably, the plasma gas is composed of nitrogen and oxygen. The stop layer is then exposed to the plasma gas until a primary surface of the stop layer is bombarded plane. A second integral layered dielectric is then formed on the primary surface. A top surface of the second integral layered dielectric is generally plane and parallel to the primary surface.

Abstract: The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.

Abstract: A getter pump module includes a number of getter disks provided with axial holes, and a heating element which extends through the holes to support and heat the getter disks. The getter disks are preferably solid, porous, sintered getter disks that are provided with a titanium hub that engages the heating element. A thermally isolating shield is provided to shield the getter disks from heat sources and heat sinks within the chamber, and to aid in the rapid regeneration of the getter disks. In certain embodiments of the present invention the heat shields are fixed, and in other embodiments the heat shield is movable. In one embodiment, a focus shield is provided to reflect thermal energy to the getter material from an external heater element and provide high pumping speeds. An embodiment of the present invention also provides for a rotating getter element to enhance getter material utilization.

Abstract: An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Abstract: A method and an apparatus for endpoint determination when milling an integrated circuit disposed in a substrate. In one embodiment, the substrate is charged to a first polarity while the well regions and active diffusion regions of the integrated circuit are charged to another polarity thus resulting in an electrical bias at the P-N junctions in the substrate. By powering up the integrated circuit in this fashion during milling, endpoint detection can be accurately determined by using a voltage contrast mechanism such as the imaging detector of a focused ion beam (FIB) milling tool. A diffusion boundary can also be determined in accordance with the teachings of the invention by the use of the stage current monitor of the FIB milling tool.

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

Abstract: Apparatus controls a wafer potential in a plasma system when the plasma is off to keep the wafer slightly negative at all times in order to reduce and eliminate the collection of charged particles on the wafer. The apparatus allows the wafer bias to be reduced to a small negative voltage and then holds that voltage. This greatly reduces the net positive flux to the wafer. A diode and a programmed power supply hold a minimum negative voltage on the back of the wafer electrode when the plasma density is decaying to zero.