And Subsequent Doping Of Polycrystalline Semiconductor Patents (Class 438/491)
  • Patent number: 9087694
    Abstract: A seed layer structure is annealed. The seed layer structure comprises a crystallization catalyst material on a seed semiconductor over a substrate. The seed semiconductor comprises an amorphous portion. Annealing of the seed layer structure converts the amorphous portion into a crystalline portion. The crystalline portion is connected to the substrate by subsurface crystal legs. The crystallization catalyst material formed underneath the crystalline portion by annealing is removed from the underneath of the crystalline portion.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 21, 2015
    Assignees: Silicon Solar Solutions, LLC, Board of Trustees of the University of Arkansas
    Inventors: Douglas Arthur Hutchings, Seth Daniel Shumate, Hameed Naseem
  • Patent number: 9007584
    Abstract: A plurality of overlay errors in a structure is determined using a target that includes a plurality of diffraction based overlay pads. Each diffraction based overlay pad has the same number of periodic patterns as the structure under test. Additionally, each diffraction based overlay pad includes a programmed shift between each pair of periodic patterns. The pads are illuminated and the resulting light is detected and used to simultaneously determine the plurality of overlay errors in the structure based on the programmed shifts. The overlay errors may be determined using a subset of elements of the Mueller matrix or by using the resulting spectra from the pads.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: April 14, 2015
    Assignee: Nanometrics Incorporated
    Inventor: Jie Li
  • Publication number: 20150093886
    Abstract: A plasma processing method of one embodiment of the present invention is disclosed for growing a polycrystalline silicon layer on a base material to be processed. The plasma processing method includes: (a) a step for preparing, in a processing container, the base material to be processed; and (b) a step for growing the polycrystalline silicon layer on the base material by introducing microwaves for plasma excitation into the processing container, and introducing a silicon-containing raw material gas into the processing container.
    Type: Application
    Filed: April 23, 2013
    Publication date: April 2, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Minoru Honda, Toshio Nakanishi, Daisuke Katayama
  • Patent number: 8956890
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein a p-cladding layer has a uniform Mg concentration. A p-cladding layer having a superlattice structure in which AlGaN and InGaN are alternately and repeatedly deposited is formed in two stages of the former process and the latter process where the supply amount of the Mg dopant gas is different. The supply amount of the Mg dopant gas in the latter process is half or less than that in the former process. The thickness of a first p-cladding layer formed in the former process is 60% or less than that of the p-cladding layer, and 160 ? or less.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Atsushi Miyazaki, Koji Okuno
  • Patent number: 8932943
    Abstract: A method of manufacturing a nitride semiconductor light emitting device which includes forming an n-type semiconductor layer, forming an active layer on the n-type semiconductor layer, forming a superlattice layer by alternately stacking at least two nitride layers made of InxAlyGa(1-x-y)N (0?x?1, 0?y?1, and 0?x+y?1) having different energy bandgaps from each other and doped with a p-type dopant, and forming a p-type semiconductor layer on the superlattice layer. The forming of the superlattice layer is performed by adjusting a flow rate of a p-type dopant source gas to reduce the flow rate in a growth termination period of the superlattice layer by no greater than about half of the flow rate in a growth initiation period of the superlattice layer while being doped with the p-type dopant.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Cheon, Yu Ri Sohn
  • Patent number: 8846508
    Abstract: Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald England, Andrew M. Waite, Simon Ruffell
  • Patent number: 8841199
    Abstract: A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yongdon Kim
  • Patent number: 8765582
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Chia-Chen Chen, Tzung-Chi Fu, Tzu-Wei Kao, Yu Chao Lin
  • Publication number: 20140061655
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Hsu, Chia-Chen Chen, Tzung-Chi Fu, Tzu-Wei Kao, Yu Chao Lin
  • Publication number: 20140054532
    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.
    Type: Application
    Filed: December 13, 2012
    Publication date: February 27, 2014
    Applicant: SK HYNIX INC.
    Inventors: Young Ho LEE, Keum Bum LEE, Min Yong LEE, Hyung Suk LEE, Seung Beom BAEK
  • Publication number: 20140043096
    Abstract: Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The polysilicon diode is comprised of three portions, a lightly doped portion flanked by a more heavily doped portion on each end.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Inventor: Adrian FINNEY
  • Patent number: 8603896
    Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 10, 2013
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Carlos Mazure
  • Patent number: 8569150
    Abstract: A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler
  • Patent number: 8507369
    Abstract: The invention provides a method for producing silicon nanowire devices, including the following steps: growing SiNW on a substrate; depositing an amorphous carbon layer and dielectric anti-reflectivity coating orderly; removing part of dielectric anti-reflectivity coating and amorphous carbon layer above the SiNW through dry etching to expose the SiNW device area; depositing an oxide film on the surface of the above structure; forming a metal pad connected with the SiNW in the SiNW device area; depositing a passivation layer on the surface of the above structure; applying photolithography and etching technology to form contact holes on the metal pad and to remove the passivation layer, the oxide film and the dielectric anti-reflectivity coating above the SiNW outside the device area, stopping on the amorphous carbon layer; removing the amorphous carbon layer above the SiNW outside the device area through ashing process to expose the SiNW.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: August 13, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Xubin Jing, Bin Yang, Mingsheng Guo
  • Publication number: 20130164921
    Abstract: Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.
    Type: Application
    Filed: February 25, 2013
    Publication date: June 27, 2013
    Applicant: SANDISK 3D LLC
    Inventor: SanDisk 3D LLC
  • Patent number: 8415218
    Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: April 9, 2013
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fumitake Mieno
  • Publication number: 20130032801
    Abstract: The electronic device includes a substrate, a first electrode formed over a surface of the substrate, a second electrode located on an opposite side of the first electrode from the substrate so as to face the first electrode, and a functional layer interposed between the first electrode and second electrode and formed by means of anodizing a first polycrystalline semiconductor layer in an electrolysis solution so as to contain a plurality of semiconductor nanocrystals. The electronic device further includes a second polycrystalline semiconductor layer interposed between the first electrode and the functional layer so as to be in close contact with the functional layer. The second polycrystalline semiconductor layer has an anodic oxidization rate in the electrolysis solution lower than that of the first polycrystalline semiconductor layer so as to function as a stop layer for exclusively anodizing the first polycrystalline semiconductor layer.
    Type: Application
    Filed: March 31, 2011
    Publication date: February 7, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Tsutomu Ichihara, Kenji Tsubaki, Masao Kubo, Nobuyoshi Koshida
  • Patent number: 8367527
    Abstract: A method of fabricating a polycrystalline silicon thin that includes a metal layer forming operation of forming a metal layer on an insulating substrate, a first silicon layer forming operation of stacking a silicon layer on the metal layer formed in the metal layer forming operation, a first annealing operation of forming a silicide layer using by moving catalyst metal atoms from the metal layer to the silicon layer using an annealing process, a second silicon layer forming operation of stacking an amorphous silicon layer on the silicide layer, and a crystallization operation of crystallizing the amorphous silicon layer into crystalline silicon through the medium of particles of the silicide layer.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 5, 2013
    Assignee: Nokord Co., Ltd.
    Inventors: Won Tae Lee, Han Sick Cho, Hyung Su Kim
  • Publication number: 20130029480
    Abstract: A method of making a three-dimensional structure in semiconductor material includes providing a substrate (20) is provided having at least a surface including semiconductor material. Selected areas of the surface of the substrate are exposed to a focussed ion beam whereby the ions are implanted in the semiconductor material in the selected areas. Several layers of a material selected from the group consisting of mono-crystalline, poly-crystalline or amorphous semiconductor material, are deposited on the substrate surface and between depositions focussed ion beam is used to expose the surface so as to define a three-dimensional structure. Material not part of the final structure (30) defined by the focussed ion beam is etched away so as to provide a three-dimensional structure on the substrate (20).
    Type: Application
    Filed: April 5, 2011
    Publication date: January 31, 2013
    Inventors: Frank Niklaus, Andreas Fischer
  • Publication number: 20120276702
    Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.
    Type: Application
    Filed: April 26, 2012
    Publication date: November 1, 2012
    Inventors: Jun-kyu YANG, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim
  • Patent number: 8242002
    Abstract: A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10?7/° C. and less than or equal to 38×10?7/° C. The heated layer including the semiconductor film is irradiated with a pulsed ultraviolet laser beam having a width of less than or equal to 100 ?m, a ratio of width to length of 1:500 or more, and a full width at half maximum of the laser beam profile of less than or equal to 50 ?m, so that a crystalline semiconductor film is formed. As the layer including the semiconductor film formed over the glass substrate, a layer whose total stress after heating is ?500 N/m to +50 N/m, inclusive is formed.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hidekazu Miyairi, Yasuhiro Jinbo
  • Patent number: 8236603
    Abstract: A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: August 7, 2012
    Assignees: Solexant Corp., Rochester Institute of Technology
    Inventors: Leslie G. Fritzemeier, Ryne P. Raffaelle, Christopher Leitz
  • Patent number: 8093634
    Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: January 10, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Anthony Mowry, Andy Wei, Andreas Gehring, Casey Scott
  • Patent number: 8067277
    Abstract: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN diode. This avoids the exposure of the amorphous silicon to high temperature processing. The TFT comprises doped source/drain regions (16a,17a), one of which (17a) may also provide the n-type or p-type doped region for the diode. Advantageously, the requirement to provide a separate doped region for the photodiode is removed, thereby saving processing costs. A second TFT (10b) having a doped source/drain region (16b,17b) of the opposite conductivity type may provide the other doped region (16b) for the diode, wherein the intrinsic region (25) is disposed laterally between the two TFTs, overlying each of the respective polysilicon islands.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: November 29, 2011
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Steven C. Deane
  • Publication number: 20110287615
    Abstract: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
    Type: Application
    Filed: August 1, 2011
    Publication date: November 24, 2011
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Patent number: 8039330
    Abstract: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure and a source/drain region is formed in the substrate adjacent to the spacer but away from the gate structure. A bevel carbon implantation process is performed to implant a plurality carbon atoms into the substrate and a metal silicide layer is formed on the gate structure and the source/drain region.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: October 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng
  • Patent number: 8030653
    Abstract: Embodiments relate to an image sensor that may include transistors, a first dielectric, a crystalline semiconductor layer on and/or over the first dielectric, a photodiode, a dummy region, via contacts, and a second dielectric. A photodiode may be formed by implanting impurity ions into a crystalline semiconductor layer to correspond the pixel region. A dummy region may be formed in the crystalline semiconductor layer excepting a region for the photodiode. Via contacts may penetrate the dummy region, and may be connected to the first metal interconnections. A second dielectric may include a plurality of second metal interconnections on and/or over the crystalline semiconductor layer. The plurality of second metal interconnections may electrically connect the via contacts to the photodiode.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: October 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hag-Dong Kim
  • Patent number: 8017508
    Abstract: A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10?7/° C. and less than or equal to 38×10?7/° C. The heated layer including the semiconductor film is irradiated with a pulsed ultraviolet laser beam having a width of less than or equal to 100 ?m, a ratio of width to length of 1:500 or more, and a full width at half maximum of the laser beam profile of less than or equal to 50 ?m, so that a crystalline semiconductor film is formed. As the layer including the semiconductor film formed over the glass substrate, a layer whose total stress after heating is ?500 N/m to +50 N/m, inclusive is formed.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: September 13, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hidekazu Miyairi, Yasuhiro Jinbo
  • Patent number: 8003423
    Abstract: A method for manufacturing a poly-crystal silicon photovoltaic device using horizontal metal induced crystallization comprises the steps of forming at least one layer of an amorphous silicon thin film on a substrate, forming at least one groove of which depth is less than or equal to that of the thin film on the amorphous silicon thin film, and horizontally crystallizing the amorphous silicon thin film by forming a metal layer on an upper portion of the groove. Since a crystal shape and a growth direction of the photovoltaic device can be adjusted by the method, a poly-crystal silicon thin film for improving current flow can be formed at a low-temperature.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: August 23, 2011
    Assignee: LG Electronics Inc.
    Inventors: Jung-Heum Yun, Kwy-Ro Lee, Don-Hee Lee, Heon-Min Lee
  • Patent number: 7977218
    Abstract: Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: July 12, 2011
    Assignee: Spansion LLC
    Inventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
  • Patent number: 7959733
    Abstract: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 14, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Pao-Hwa Chou, Chaeho Kim
  • Patent number: 7923305
    Abstract: A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, etching the first sacrificial layer using both the first and the second photoresist features as a mask to form first sacrificial features, forming a spacer layer over the first sacrificial features, etching the spacer layer to form spacer features and to expose the sacrificial features, removing the first sacrificial features, and etching at least part of the underlying layer using the spacer features as a mask.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: April 12, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen
  • Patent number: 7923356
    Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: April 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Kengo Akimoto
  • Patent number: 7842595
    Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: November 30, 2010
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Nick Sauer, Nils Weimann, Liming Zhang
  • Patent number: 7838442
    Abstract: A method for producing a solar cell including the steps of forming a p-type microcrystalline silicon oxide layer on a glass substrate using a PECVD method and raw gases comprising Silane gas, Diborane gas, Hydrogen gas and Carbon Dioxide gas. The method may employ a frequency of between about 13.56-60 MHz. The PECVD method may be performed at a power density of between about 10-40 mW/cm2 and a pressure of between about 0.5-2 Torr, and with a ratio of Carbon Dioxide to Silane of between about 0.10-0.24; a ratio of Diborane to Silane of 0.10 or less, and a ratio of Silane to Hydrogen of 0.01 or less. A tandem solar cell structure may be formed by forming top and bottom layers by the method described above, and placing the top layer over the bottom layer.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: November 23, 2010
    Assignee: National Science and Technology Development Agency
    Inventors: Porponth Sichanugrist, Nirut Pingate, Decha Yotsaksri
  • Patent number: 7833864
    Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Chul Oh, Wook-Je Kim, Nak-Jin Son, Se-Myeong Jang, Gyo-Young Jin
  • Patent number: 7755093
    Abstract: A nonvolatile semiconductor storage device is provided in which memory cells comprising PN junction diodes having satisfactory rectifying characteristics are arranged in three dimensions. The semiconductor storage device includes: a first wire which extends in one direction; a second wire which extends in a direction intersecting the first wire; and a memory cell which is positioned at a portion of intersection of the first wire with the second wire between the first wire and the second wire, the memory cell comprising a storage element and a PN junction diode connected thereto, positioned on a side of the second wire used in selecting the memory cell, and a P-type semiconductor forming the PN junction diode forms a portion of the second wire, wherein a plurality of structures, each structure comprising the first wire, the second wire, and the memory cell is provided three-dimensionally.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 13, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Shinji Ohara
  • Publication number: 20100173449
    Abstract: Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Carl John Radens, William Robert Tonti
  • Publication number: 20100155728
    Abstract: An epitaxial wafer and method for fabricating the same can prevent a bowing phenomenon of the epitaxial wafer. The epitaxial wafer includes a substrate configured to be doped in a first doping concentration; an epitaxial layer configured to be formed over a first side of the substrate and doped in a second doping concentration lower than the first doping concentration; and a back seal layer configured to be formed over a second side of the substrate and include a layer having a tensile stress, wherein the second side is opposite to the first side, of the substrate.
    Type: Application
    Filed: November 16, 2009
    Publication date: June 24, 2010
    Inventor: Han-Seob Cha
  • Patent number: 7718518
    Abstract: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: May 18, 2010
    Assignee: ASM International N.V.
    Inventors: Peter Marc Zagwijn, Theodorus Gerardus Maria Oosterlaken, Steven R. A. Van Aerde, Pamela René Fischer
  • Publication number: 20100112792
    Abstract: The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 ?m to 40 ?m on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Keith E. Fogel, Daniel A. Inns, Devendra K. Sadana, Katherine L. Saenger
  • Publication number: 20090304034
    Abstract: Electrically pumped mid-IR semiconductor lasers that are operable at room temperature and possess a range of tunability up to 1100 nm, which constitutes a revolutionary (1-2 orders of magnitude) improvement in the range of tunability over existing semiconductor laser technology utilizing Doped quantum confined host material (DQCH) with characteristic spatial dimension of the confinement tuned to enable the overlap of the discrete levels of the host and impurity ions and efficient energy transfer from the separated host carriers to the impurity, wherein: said DQCH material has the formula TM:MeZ and/or MeX2Z4, wherein Me is selected from the group consisting of Zn, Cd, Ca, Mg, Sr, Ba, Hg, Pb, Cu, Al, Ga, In; Z is selected from the group consisting of S, Se, Te, O, N, P, As, Sb and their mixtures; X being selected from the group consisting of Ga, In, and Al; and TM is selected from the group consisting from V, Cr, Mn, Fe, Co, and Ni.
    Type: Application
    Filed: March 12, 2007
    Publication date: December 10, 2009
    Inventors: Sergey B. Mirov, Vladimir V. Fedorov, Dmitri Martyshkin
  • Publication number: 20090294860
    Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.
    Type: Application
    Filed: February 27, 2009
    Publication date: December 3, 2009
    Inventors: Anthony Mowry, Andy Wei, Andreas Gehring, Casey Scott
  • Publication number: 20090261343
    Abstract: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.
    Type: Application
    Filed: June 3, 2009
    Publication date: October 22, 2009
    Applicant: SanDisk 3D LLC
    Inventors: S. Brad Herner, Maitreyee Mahajani
  • Publication number: 20090221135
    Abstract: The present process for rapidly heating and cooling a target material without damaging the substrate upon which it has been deposited. More specifically, target material is coated onto a first substrate. A self-propagating nanoenergetic material is selected that combusts at temperatures sufficient to change the target material and creates a flame front that propagates sufficiently quickly that the first substrate is not substantially heated. The nanoenergetic material is deposited on the target material, such that the target material and the nanoenergetic material is sandwiched between the substrate and the target material. The nanoenergetic material is ignited and the flame front of the nanoenergetic material is allowed to propagate over the second substrate and change the target material.
    Type: Application
    Filed: October 27, 2006
    Publication date: September 3, 2009
    Inventors: Shubhra Gangopadhyay, Maruf Hossain, Keshab Gangopadhyay, Rajesh Shende
  • Patent number: 7569462
    Abstract: The present invention provides a method of recrystallizing a silicon sheet, and in particular recrystallizing a small grained silicon sheet to improve material properties such as grain size and orientation. According to one aspect, the method includes using rapid thermal processing (RTP) to melt and recrystallize one or more entire silicon sheet(s) in one heating sequence. According to another aspect, the method includes directionally controlling a temperature drop across the thickness of the sheet so as to facilitate the production of a small number of nuclei in the melted material and their growth into large grains. According to a further aspect, the invention includes a re-crystallization chamber in an overall process flow that enables high-throughput processing of silicon sheets having desired properties for applications such as photovoltaic modules.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: August 4, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V. Rana, Robert Z. Bachrach
  • Publication number: 20090166623
    Abstract: A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 2, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kimitoshi SATO, Mika OKUMURA, Yasuo YAMAGUCHI, Makio HORIKAWA
  • Publication number: 20090121224
    Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.
    Type: Application
    Filed: January 2, 2008
    Publication date: May 14, 2009
    Inventor: Young Hoon KIM
  • Patent number: 7521303
    Abstract: A method of crystallizing an amorphous semiconductor thin film used for a thin film transistor (TFT) is provided. The method includes the steps of: forming first and second crystallization induced metal patterns locally in respective portions of a source region and a drain region of the TFT on an amorphous semiconductor thin film; and crystallizing an amorphous semiconductor via independent two-times heat treatment using the first and second crystallization induced metal patterns. In this case, the independent two-times heat treatment is executed before and after ions of impurities are injected, respectively. In this way, a metal induced lateral crystallization double heat treatment is executed before and after ions of impurities are injected, respectively. As a result, the entire crystallization heat treatment time necessary for crystallizing the amorphous semiconductor thin film can be greatly reduced, and a poly-crystalline TFT having low leakage current can be obtained.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: April 21, 2009
    Inventor: Woon Suh Paik
  • Patent number: RE43045
    Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: December 27, 2011
    Assignee: Cree, Inc.
    Inventor: David Todd Emerson