Polycrystalline Semiconductor Patents (Class 438/488)
  • Patent number: 10559571
    Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunjung Kim, Daeik Kim, Bong-Soo Kim, Jemin Park, Semyeong Jang, Yoosang Hwang
  • Patent number: 10483340
    Abstract: A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: November 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyuk Soon Kwon
  • Patent number: 10411133
    Abstract: A manufacturing method of a polysilicon layer of a thin film transistor of a display device, includes: irradiating a first excimer laser beam having a first energy density to an amorphous silicon layer including an oxidation layer thereon, to form a first polysilicon layer including thereon portions of the oxidation layer at grain boundaries of the first polysilicon layer; removing the portions of the oxidation layer at the grain boundaries of the first polysilicon layer; and irradiating a second excimer laser beam having a second energy density of 80% to 100% of the first energy density to the first polysilicon layer from which the portions of the oxidation layer at the grain boundaries thereof are removed, to form a second polysilicon layer as the polysilicon layer of the thin film transistor.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Oh Seo, Byung Soo So, Dong-Min Lee, Dong-Sung Lee
  • Patent number: 10269984
    Abstract: The present application discloses A thin film transistor (TFT), including: a substrate; a source-drain layer comprising a source electrode and a drain electrode over the substrate; and an active layer comprising a poly-Si pattern and an amorphous-Si pattern having contact with the poly-Si pattern over the substrate. The amorphous-Si pattern is between the poly-Si pattern and the source-drain layer; the source electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in a direction substantially perpendicular to a surface of the substrate; and the drain electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in the direction substantially perpendicular to the surface of the substrate.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 23, 2019
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinchao Bai, Huibin Guo, Xiangqian Ding, Jing Wang
  • Patent number: 10236394
    Abstract: The present application discloses A thin film transistor (TFT), including: a substrate; a source-drain layer comprising a source electrode and a drain electrode over the substrate; and an active layer comprising a poly-Si pattern and an amorphous-Si pattern having contact with the poly-Si pattern over the substrate. The amorphous-Si pattern is between the poly-Si pattern and the source-drain layer; the source electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in a direction substantially perpendicular to a surface of the substrate; and the drain electrode overlaps with the poly-Si pattern and the amorphous-Si pattern respectively in the direction substantially perpendicular to the surface of the substrate.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 19, 2019
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinchao Bai, Huibin Guo, Xiangqian Ding, Jing Wang
  • Patent number: 9793337
    Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 17, 2017
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Patent number: 9728452
    Abstract: A method for depositing one or more polycrystalline silicon layers (230c) on a substrate (210) by a chemical vapor deposition in a reactor, includes adjusting a deposition temperature between 605° C.-800° C. in a process chamber of the reactor, and depositing the one or more polycrystalline silicon layers on the substrate by using a silicon source gas including SiH4 or SiH2Cl2, and a dopant gas including BCl3.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 8, 2017
    Assignee: OKMETIC OYJ
    Inventors: Veli Matti Airaksinen, Jari Makinen
  • Patent number: 9647154
    Abstract: This invention relates to the controlled realization of ordered superstructures of octapod-shaped colloidal nanocrystals, formed either in the liquid phase or on a solid substrate. These structures can be applied in many fields of technology.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: May 9, 2017
    Assignee: FONDAZIONE ISTITUTO ITALIANO DI TECNOLOGIA
    Inventors: Karol Miszta, Dirk Dorfs, Giovanni Bertoni, Liberato Manna, Rosaria Brescia, Sergio Marras, Roberto Cingolani, Roman Krahne, Yang Zhang, Fen Qiao
  • Patent number: 9515045
    Abstract: A chip handling apparatus, unit and method is presented. The chip handling apparatus comprises a chip supply station; a chip mounting station; and one or more chip handling units configured to pick a chip from the supply station, transport the chip to the mounting station, and place the chip at a mounting location; wherein each chip handling unit is configured to temporarily retain the chip in a defined position relative to the chip handling unit. The chip handling apparatus further comprises means for inducing sonic vibrations in the chip when retained by one of the chip handling units; and means for measuring the vibrations induced in the chip.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 6, 2016
    Assignee: Kulicke and Soffa Die Bonding GmbH
    Inventors: Andreas Marte, Tim Oliver Stadelmann
  • Patent number: 9508786
    Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 29, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Fu Chung, Chu-Wei Hu, Yuan-Hung Chung
  • Patent number: 9484199
    Abstract: Embodiments of the present invention generally relate to methods for forming a SiGe layer. In one embodiment, a seed SiGe layer is first formed using plasma enhanced chemical vapor deposition (PECVD), and a bulk SiGe layer is formed directly on the PECVD seed layer also using PECVD. The processing temperature for both seed and bulk SiGe layers is less than 450 degrees Celsius.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: November 1, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hyo-In Chi, Farzad Dean Tajik, Michel Anthony Rosa
  • Patent number: 9419546
    Abstract: The present invention relates to an energy harvester device comprising a plurality of elongate resonator beams. The resonator beams include a piezoelectric material extending between first and second ends. One or more bases are connected to the first end of each of the resonator beams, with the second end of the resonator beams being freely extending from the one or more bases as a cantilever. A mass is attached to each of the second ends of the resonator beams. Each of the resonator beams is tuned to a resonant frequency offset relative to each of the other resonator beams by 0.1/W to 0.9/W, wherein W is a temporal width between a first impulse and a second impulse which excite motion of the resonator beams. Also disclosed is a system comprising an apparatus and the energy harvester device, as well as methods of using and designing the system.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: August 16, 2016
    Assignee: MicroGen Systems, Inc.
    Inventor: David Trauernicht
  • Patent number: 9406785
    Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 2, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Doo Hyoung Lee, Bo Sung Kim, Chan Woo Yang, Seung-Ho Jung, Yeon Taek Jeong, June Whan Choi, Tae-Young Choi
  • Patent number: 9260789
    Abstract: A metal article comprises an alloy substrate having a surface and a non-diffused metal monolayer disposed thereon. The surface has a first surface work function value ?s. The non-diffused monolayer deposited on the surface has a second surface work function value ?s that is less negative than the first surface work function value. A method for depositing the monolayer via underpotential deposition (UPD) is also disclosed.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: February 16, 2016
    Assignee: United Technologies Corporation
    Inventors: Weilong Zhang, Xiaomei Yu, Lei Chen, Mark R. Jaworowski, Joseph J. Sangiovanni
  • Patent number: 9252248
    Abstract: An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 2, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masami Jintyou, Yamato Aihara, Katsuaki Tochibayashi, Toru Arakawa
  • Patent number: 9177761
    Abstract: A structure of a plasma CVD apparatus for forming a dense semiconductor film is provided. Further, a technique for forming a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains is provided. An electrode supplied with electric power for generating plasma is included in a reaction chamber of the plasma CVD apparatus. This electrode has a common plane on a surface opposite to a substrate, and the common plane is provided with depressed openings. Gas supply ports are provided on the bottom of the depressed openings or on the common plane of the electrode. The depressed openings are provided in isolation from one another.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: November 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9064703
    Abstract: A low temperature polysilicon film and a manufacturing method thereof, a thin film transistor and a manufacturing method thereof and a display panel are provided. The manufacturing method of the low temperature polysilicon film includes crystallizing a nano-silicon thin film to form the low temperature polysilicon film.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: June 23, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhen Liu
  • Publication number: 20150147872
    Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Inventors: Lup San Leong, Alan Cing Gie Lim, Ling Wu, Jian Bo Yang
  • Patent number: 9040396
    Abstract: An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Yamato Aihara, Katsuaki Tochibayashi, Toru Arakawa
  • Publication number: 20150140795
    Abstract: The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step. Then the foreign substrate is heated to such an extent that the semiconductor thin film melts. Then the temperature is slowly decreased to below the melting temperature of the semiconductor material. During the cooling process, the foreign substrate is heated in such a way that, proceeding from the surface of the foreign substrate, the temperature continuously decreases in a vertical direction perpendicular through the semiconductor thin film to the surface of the thin film.
    Type: Application
    Filed: June 17, 2013
    Publication date: May 21, 2015
    Inventor: Jean-Paul Theis
  • Publication number: 20150132927
    Abstract: The present invention provides a polysilicon manufacturing method that controls a growth direction of polysilicon, including the following steps: (1) forming a first buffer layer (20) on a substrate (10) through deposition; (2) applying a masking operation to form a lens-like structure (22) on a surface of the first buffer layer (20); (3) depositing and forming an amorphous silicon layer (40) on the first buffer layer (20) of which the surface comprises the lens-like structure (22) formed thereon; (4) subjecting the amorphous silicon layer (40) to rinsing; (5) irradiating the amorphous silicon layer (40) with an intense light (50) from the side of the substrate (10) so as to generate a crystal seed at a bottom of the amorphous silicon layer (40); and (6) applying a laser annealing operation to the amorphous silicon layer (40) that comprises a crystal seed generated therein so as to have amorphous silicon contained in the amorphous silicon layer (40) crystallized and forming a polysilicon layer (70).
    Type: Application
    Filed: November 18, 2013
    Publication date: May 14, 2015
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Xiang Zhang
  • Patent number: 9012295
    Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
  • Patent number: 9000440
    Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Mo Chung, Jin-Wook Seo, Tak-Young Lee
  • Publication number: 20150075614
    Abstract: A method includes the steps of performing a coating or printing of ink for producing a compound semiconductor thin film so as to form a compound semiconductor coating film, the ink including 50% by mass or more of amorphous compound nanoparticles, mechanically applying a pressure to the compound semiconductor coating film, and subjecting the compound semiconductor coating film to a heat-treatment to form a compound semiconductor thin film.
    Type: Application
    Filed: November 26, 2014
    Publication date: March 19, 2015
    Applicants: TOPPAN PRINTING CO., LTD., TOKYO INSTITUTE OF TECHNOLOGY, RYUKOKU UNIVERSITY
    Inventors: Yiwen ZHANG, Akira YAMADA, Takahiro WADA
  • Publication number: 20150079772
    Abstract: The present invention relates to a method for forming a crystallised silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallised, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallised in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallising said layer of silicon with the expected grain size, characterised in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.
    Type: Application
    Filed: April 8, 2013
    Publication date: March 19, 2015
    Inventors: Jean-Paul Garandet, Virginie Brize, Etienne Pihan, Alain Straboni, Florent Dupont
  • Publication number: 20150064885
    Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.
    Type: Application
    Filed: June 19, 2014
    Publication date: March 5, 2015
    Inventors: Bo-Young Lee, Jong-Wan Choi, Dae-Hun Choi, Myoung-Bum Lee
  • Patent number: 8969183
    Abstract: Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 3, 2015
    Assignees: President and Fellows of Harvard College, Massachusetts Institute of Technology
    Inventors: Mark T. Winkler, Tonio Buonassisi, Riley E. Brandt, Michael J. Aziz, Austin Joseph Akey
  • Patent number: 8969150
    Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Katou, Taro Moriya, Hiroyoshi Kudou, Satoshi Uchiya
  • Patent number: 8962354
    Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
  • Publication number: 20150035036
    Abstract: According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.
    Type: Application
    Filed: March 5, 2014
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Konno, Ryota Katsumata, Yoshiaki Fukuzumi
  • Publication number: 20150017788
    Abstract: A system and method for growing polycrystalline silicon-germanium film that includes mixing a GeH4 gas and a SiH4 gas to coat and grow polycrystalline silicon-germanium film on a silicon wafer. The GeH4 gas and the SiH4 gas are also heated and the pressure around the wafer is reduced to at least 2.5*10?3 mBar to produce the polycrystalline silicon-germanium film. The polycrystalline silicon-germanium film is then annealed to improve its resistivity.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventor: Vu A. Vu
  • Publication number: 20150017787
    Abstract: A method and fluidized bed reactor for reducing or eliminating contamination of silicon-coated particles are disclosed. The metal surface of one or more fluidized bed reactor components is at least partially coated with a hard protective layer comprising a material having an ultimate tensile strength of at least 700 MPa at 650° C.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Matthew J. Miller, Michael V. Spangler
  • Patent number: 8895415
    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Dong Niu, Joseph L. Womack
  • Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Patent number: 8889530
    Abstract: A highly dislocation free compound semiconductor, e.g. AlxInyGa1-x-yN (0?x, y?1), is formed on a lattice mismatched substrate, e.g. Si, by first depositing a polycrystalline buffer layer on the substrate. A defective layer is then created at or near the interface of the substrate and the polycrystalline buffer layer, e.g. through ion implantation. A monocrystalline template layer of the compound semiconductor is then created on the buffer layer, and an epilayer of the compound semiconductor is grown on the template layer. A compound semiconductor based device structure may be formed in the epilayer.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: November 18, 2014
    Assignee: The Research Foundation of State University of New York
    Inventors: Fatemeh Shahedipour-Sandvik, Di Wu, Jamil Kahn Muhammad
  • Patent number: 8889531
    Abstract: A semiconductor body comprised of a semiconductor material includes a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction, a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the first, along the reference direction, and a third, strained monocrystalline region between the first region and the second region.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reinhart Job
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Publication number: 20140332814
    Abstract: Methods of producing arrays of thin crystal grains of layered semiconductors, including the creation of stable atomic-layer-thick to micron-thick membranes of crystalline semiconductors by chemical vapor deposition.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 13, 2014
    Applicant: The University of Houston System
    Inventors: Haibing Peng, Guoxiong Su, Debtanu De
  • Publication number: 20140332818
    Abstract: A low temperature polysilicon film and a manufacturing method thereof, a thin film transistor and a manufacturing method thereof and a display panel are provided. The manufacturing method of the low temperature polysilicon film includes crystallizing a nano-silicon thin film to form the low temperature polysilicon film.
    Type: Application
    Filed: June 7, 2013
    Publication date: November 13, 2014
    Inventor: Zhen Liu
  • Publication number: 20140322900
    Abstract: A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof The apparatus comprises a reaction furnace, having reaction gas input pipelines respectively arranged at a furnace opening part and a furnace tail part. During thin film deposition, each reaction gas is synchronously introduced into the reaction furnace through the input pipeline at the furnace opening part and the input pipeline at the furnace tail part.
    Type: Application
    Filed: December 3, 2012
    Publication date: October 30, 2014
    Applicant: Wuxi China Resources Huajing Microelectronics Co., Ltd
    Inventors: Xunhui Wang, Xiao Wu, Qijun Guo, Jianchao Fan
  • Publication number: 20140319539
    Abstract: A method for manufacturing a semiconductor wafer includes a carbon layer formation step, a through hole formation step, a feed layer formation step, and an epitaxial layer formation step. In the carbon layer formation step, a carbon layer (71) is formed on a surface of a substrate (70) made of polycrystalline SiC. In the through hole formation step, through holes (71c) are formed in the carbon layer (71) formed on the substrate (70). In the feed layer formation step, a Si layer (72) and a 3C—SiC polycrystalline layer (73) are formed on a surface of the carbon layer (71). In the epitaxial layer formation step, the substrate (70) is heated so that a seed crystal made of 4H—SiC single crystal is formed on portions of the surface of the substrate (70) that are exposed through the through holes (71c), and a close-spaced liquid-phase epitaxial growth of the seed crystal is caused to form a 4H—SiC single crystal layer.
    Type: Application
    Filed: August 24, 2012
    Publication date: October 30, 2014
    Applicants: TOYO TANSO CO., LTD., KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Noboru Ohtani, Shoji Ushio, Ayumu Adachi, Satoru Nogami
  • Patent number: 8871552
    Abstract: Although Cl (chlorine) is no longer supplied in the course of a first process in which a detecting layer formed by a polycrystalline film or a polycrystalline lamination film by vapor deposition or sublimation is formed, an additional source (e.g., HCl of Cl-containing gas) other than a source is supplied at the start or in the course of the first process. Thus, the detecting layer as the polycrystalline film or the polycrystalline lamination film of CdTe, ZnTe, or CdZnTe can be doped with Cl uniformly in a thickness direction from the start until the end of the first process in film formation. As a result, uniform crystal particles and uniform detection characteristics can be achieved.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 28, 2014
    Assignees: Shimadzu Corporation, Institute of National Colleges of Technology, Japan
    Inventors: Satoshi Tokuda, Koichi Tanabe, Toshinori Yoshimuta, Hiroyuki Kishihara, Masatomo Kaino, Akina Yoshimatsu, Toshiyuki Sato, Shoji Kuwabara
  • Publication number: 20140315375
    Abstract: Provided is a substrate processing apparatus.
    Type: Application
    Filed: November 16, 2012
    Publication date: October 23, 2014
    Applicant: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Il-Kwang Yang, Sung-Tae Je, Byoung-Gyu Song, Yong-Ki Kim, Kyong-Hun Kim, Yang-Sik Shin
  • Patent number: 8865484
    Abstract: Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 21, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Monica Mathur, Michael Miller, Prashant B. Phatak
  • Patent number: 8865579
    Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: October 21, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunwoo Lee, Sangwoo Lee, Changwon Lee, Jeonggil Lee
  • Patent number: 8859404
    Abstract: A seed crystal including mixed phase grains having high crystallinity at a low density is formed under a first condition over an insulating film, and then a first microcrystalline semiconductor film is formed over the seed crystal under a second condition that allows the mixed phase grains to grow and a space between the mixed phase grains to be filled. Then, a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a third condition that allows formation of a microcrystalline semiconductor film having high crystallinity without increasing the space between the mixed phase grains included in the first microcrystalline semiconductor film.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryu Komatsu, Yasuhiro Jinbo, Hidekazu Miyairi
  • Patent number: 8853063
    Abstract: A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: October 7, 2014
    Assignee: Avogy, Inc.
    Inventors: David P. Bour, Thomas R. Prunty, Linda Romano, Richard J. Brown, Isik C. Kizilyalli, Hui Nie
  • Publication number: 20140295651
    Abstract: A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventor: Jamal RAMDANI
  • Publication number: 20140295650
    Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jung Li, Chia-Jui Liang, Po-Chao Tsao, Ching-Ling Lin, En-Chiuan Liou
  • Patent number: 8847303
    Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata