Doping Of Semiconductor Patents (Class 438/495)
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Patent number: 7550365Abstract: An electrical device includes an interconnect and a pair substrates at least one of which includes an integrated circuit, the pair of substrates being bonded together by a bond that includes a structure having multiple widths and a composition that is selected from the group consisting of a graded material and a first material upon a second material.Type: GrantFiled: January 27, 2005Date of Patent: June 23, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Timothy R. Emery, William J. Edwards, Donald W. Schulte
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Publication number: 20090130828Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.Type: ApplicationFiled: January 16, 2009Publication date: May 21, 2009Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventor: Xingbi Chen
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Patent number: 7534685Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (14), which reaches down to the insulator (11) and surrounds a region (13?) of the monocrystalline silicon (13) of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region (17?) on a portion of the monocrystalline silicon region, forming a doped silicon layer region (18) on the insulating layer region (17?), and forming an insulating outside sidewall spacer (61) on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region (13?), the insulating layer region (17?), and the doped silicon layer region (18) constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.Type: GrantFiled: September 1, 2006Date of Patent: May 19, 2009Assignee: Infineon Technologies AGInventor: Ted Johansson
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Patent number: 7504279Abstract: A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers.Type: GrantFiled: November 29, 2007Date of Patent: March 17, 2009Assignee: Oerlikon Trading AG, TrubbachInventors: Ulrich Kroll, Cedric Bucher, Jacques Schmitt, Markus Poppeller, Christoph Hollenstein, Juliette Ballutaud, Alan Howling
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Publication number: 20090050958Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the spacer layer.Type: ApplicationFiled: September 8, 2008Publication date: February 26, 2009Inventors: Qi Wang, Amber Crellin-Ngo, Hossein Paravi
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Publication number: 20080197407Abstract: A method for controlling the thickness of an expitaxially grown semiconductor material includes providing a semiconductor substrate that is doped by dopants of a first type; forming a buffer layer atop the semiconductor substrate, the buffer layer being doped with dopants of a second type that has much less diffusivity relative to that of dopants of the first type and forming the expitaxially grown layer atop the buffer layer to a desired thickness. The buffer layer, which acts to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer, can be doped with arsenic or carbon or both arsenic and carbon. A semiconductor device includes the buffer layer to counter an up-diffusion of the dopants of the first type from the substrate into the epitaxially grown layer.Type: ApplicationFiled: February 28, 2008Publication date: August 21, 2008Inventors: Ashok Challa, Alan Elbanhawy, Steven P. Sapp, Qi Wang, Peter H. Wilson, Babak S. Sani, Christopher B. Kocon
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Publication number: 20080173895Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Inventors: Jer-Shen Maa, Tingkai Li, Douglas J. Tweet, Gregory M. Stecker, Sheng Teng Hsu
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Patent number: 7344909Abstract: A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers.Type: GrantFiled: October 22, 2003Date of Patent: March 18, 2008Assignee: OC Oerlikon Balzers AGInventors: Ulrich Kroll, Cédric Bucher, Jacques Schmitt, Markus Poppeller, Christoph Hollenstein, Juliette Ballutaud, Alan Howling
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Patent number: 7341787Abstract: The invention relates to a process for producing highly doped semiconductor wafers, in which at least two dopants which are electrically active and belong to the same group of the periodic system of the elements are used for the doping. The invention also relates to a semiconductor wafer which is free of dislocations and is doped with at least two electrically active dopants which belong to the same group of the periodic system of the elements.Type: GrantFiled: January 26, 2005Date of Patent: March 11, 2008Assignee: Siltronic AGInventors: Rupert Krautbauer, Erich Gmeilbauer, Robert Vorbuchner, Martin Weber
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Patent number: 7268079Abstract: A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in size by means of an etching method. In another embodiment, the semiconductor body is partially removed in a region outside the first semiconductor zone. At least one second semiconductor zone is then fabricated in the partially removed region.Type: GrantFiled: August 19, 2005Date of Patent: September 11, 2007Assignee: Infineon Technologies AGInventors: Elmar Falck, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Reiner Barthelmess
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Patent number: 7160748Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: GrantFiled: February 24, 2005Date of Patent: January 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Patent number: 7135387Abstract: A method for stably activating pn-successive layers in a semiconductor element in a short time is disclosed. Pulsed beams, each of which has a pulse shape that is approximately rectangular, are projected from respective laser irradiation devices and successively combined into a pulsed beam equivalent to one pulse, with which the doped layer region is irradiated. By successively projecting the pulsed beams onto the doped layer region in this way, an effect is obtained which is the same as that of irradiating the doped layer region with a single pulsed beam having a long full-width at half maximum. A high activation ratio from a shallow region to a deep region of the doped layer region is enabled. This can stably activate the semiconductor element having the pn-successive layers as the doped layer region in a short time, making possible the manufacture of semiconductor elements having superior device characteristics.Type: GrantFiled: June 24, 2004Date of Patent: November 14, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Haruo Nakazawa, Mitsuaki Kirisawa, Kazuo Shimoyama
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Patent number: 7094670Abstract: A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma while minimizing deposition and minimizing etching by holding the temperature of the workpiece within a temperature range that is above a workpiece deposition threshold temperature and below a workpiece etch threshold temperature.Type: GrantFiled: January 28, 2005Date of Patent: August 22, 2006Assignee: Applied Materials, Inc.Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
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Patent number: 6982212Abstract: In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.Type: GrantFiled: November 20, 2002Date of Patent: January 3, 2006Assignee: Koninklijke Philips Electronics N.V.Inventor: Peter Adriaan Stolk
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Patent number: 6921678Abstract: The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.Type: GrantFiled: May 9, 2003Date of Patent: July 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Ishibashi, Ayumu Tsujimura, Yoshiaki Hasegawa, Nobuyuki Otsuka, Gaku Sugahara, Ryoko Miyanaga, Toshitaka Shimamoto, Kenji Harafuji, Yuzaburo Ban, Kiyoshi Ohnaka
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Patent number: 6890816Abstract: High quality epitaxial layers of monocrystalline perovskite materials (18) can be grown overlying monocrystalline substrates (12) such as gallium arsenide wafers by forming a metal template layer (16) on the monocrystalline substrate. The structure includes a metal-containing layer (16) to mitigate unwanted oxidation of underlying layers and a low-temperature seed layer (19) that prevents degradation of an epitaxial layer (14) during growth of the perovskite layer (18).Type: GrantFiled: February 7, 2003Date of Patent: May 10, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Yong Liang, Ravindranath Droopad
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Patent number: 6855991Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: March 31, 2004Date of Patent: February 15, 2005Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
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Patent number: 6776842Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.Type: GrantFiled: January 15, 2002Date of Patent: August 17, 2004Assignee: STMicroelectronics S.A.Inventors: Didier Dutartre, Patrick Jerier
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Patent number: 6740547Abstract: A process for fabricating thin film transistors is disclosed, which comprises a two-step laser annealing process as follows: crystallizing the channel portion by irradiating the channel portion with an irradiation beam; and modifying the electric properties of the source and the drain by irradiating the source and the drain with an irradiation beam in a step independent to the first step of crystallizing the channel portion.Type: GrantFiled: February 21, 2002Date of Patent: May 25, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang
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Patent number: 6737339Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: October 24, 2001Date of Patent: May 18, 2004Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
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Patent number: 6716690Abstract: Multiple dopant implantations are performed on a FinFET device to thereby distribute the dopant in a substantially uniform manner along a vertical depth of the FinFET in the source/drain junction. Each of the multiple implantations may be performed at different tilt angles.Type: GrantFiled: March 12, 2003Date of Patent: April 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Judy Xilin An, Bin Yu
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Patent number: 6686281Abstract: A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3 as a doping gas. The substrate processing apparatus includes a plurality of gas outlets for supplying GeH4 at different locations in the reaction tube and a doping gas line for supplying BCl3 at least at an upstream side of gas flow in the reaction tube.Type: GrantFiled: September 5, 2002Date of Patent: February 3, 2004Assignee: Hitachi Kokusai Electric Inc.Inventors: Hirohisa Yamazaki, Takaaki Noda
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Patent number: 6635956Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: GrantFiled: September 9, 2002Date of Patent: October 21, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Patent number: 6593217Abstract: A semiconductor device with low contact resistance which can cope with the miniaturization of semiconductor devices as well as a manufacturing method thereof which is easy and inexpensive can be obtained. Impurity regions on an Si substrate, an interlayer insulation film, source and drain interconnections, a metal silicide layer larger in diameter than the lower edge of the contact holes around the impurity regions are provided and the metal silicide layer includes an interface making up a border between the upper metal silicide layer contacting with the bottom of the interlayer insulation film and the lower metal silicide layer contacting with the impurity region surface. Thus, the contact area between the source and drain lines and the impurity regions can be increased via the metal silicide layer so as to reduce the contact resistance.Type: GrantFiled: August 11, 2000Date of Patent: July 15, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiko Fujisawa
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Publication number: 20030077884Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: ApplicationFiled: October 24, 2001Publication date: April 24, 2003Inventors: Wen Lin, Charles W. Pearce
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Patent number: 6465333Abstract: When the temperature of a silicon substrate is increased, a first annealing gas which is mainly composed of argon or the like that does not react with said silicon substrate with a trace of oxygen added thereto, is supplied to the position of the silicon substrate to prevent any unwanted reaction from occurring on the silicon substrate whose temperature is increasing. When the temperature of the silicon substrate is lowered, a second annealing gas which is mainly composed of nitrogen or the like which has a high thermal conductivity is supplied to the silicon substrate to quickly lower the temperature of the silicon substrate and prevent a doped impurity from being undesirably diffused.Type: GrantFiled: April 10, 2001Date of Patent: October 15, 2002Assignee: NEC CorporationInventor: Tomoko Matsuda
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Patent number: 6387779Abstract: The present invention relates to a method of crystallizing a silicon film, a thin film transistor, and a fabricating method thereof using the same. More particularly, the present invention relates forming a crystalline silicon film by crystallizing a silicon film using laser energy, and a thin film transistor and a fabricating method thereof using the same. The present invention includes forming a buffer layer on a substrate and forming an amorphous silicon film on the buffer layer wherein the amorphous silicon film includes a first region and second regions connected to both ends of the first region. The buffer layer is etched to a degree by using the amorphous silicon as a mask, wherein a space is formed under the first region and a central part of the second region contacts a remaining portion of the buffer layer. The amorphous silicon film is then crystallized.Type: GrantFiled: April 14, 2000Date of Patent: May 14, 2002Assignee: LG. Philips LCD Co., LTDInventors: Jonghoon Yi, Sanggul Lee
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Publication number: 20020055240Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.Type: ApplicationFiled: December 31, 2001Publication date: May 9, 2002Applicant: The Board of Trustees of the Univ. of ArkansasInventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
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Patent number: 6379990Abstract: A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrate. The membrane is laid at the edge region on a support and is covered over by a covering layer supported on a counter-support. The support and the counter-support have a different etch rate from the membrane. Wet-chemical etching of the layer sequence with an etchant that is selective to the material of the membrane thus leads to the formation of a cavity around the membrane. Preferably, the layers are formed of differently doped materials.Type: GrantFiled: July 6, 1999Date of Patent: April 30, 2002Assignee: Infineon Technologies AGInventors: Karlheinz Müller, Stefan Kolb
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Publication number: 20020034861Abstract: A ZnO based oxide semiconductor layer is grown on a sapphire substrate 1 by supplying, for example, raw materials made of Zn and O constituting ZnO and a p-type dopant material made of N without supplying an n-type dopant material (a-step). By stopping the supply of the material of O and further supplying an n-type dopant material made of Ga, the semiconductor layer is doped with the p-type dopant and the n-type dopant, thereby forming a p-type ZnO layer (2a) (b-step). By repeating the steps (a) and (b) plural times, a p-type ZnO based oxide semiconductor layer is grown. As a result, N to be the p-type dopant can be doped in a stable carrier concentration also during high temperature growth in which a residual carrier concentration can be reduced, and the carrier concentration of the p-type layer made of the ZnO based oxide semiconductor can be increased sufficiently.Type: ApplicationFiled: September 13, 2001Publication date: March 21, 2002Inventors: Kakuya Iwata, Paul Fons, Koji Matsubara, Akimasa Yamada, Shigeru Niki, Ken Nakahara
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Patent number: 6228181Abstract: An epitaxial semiconductor wafer characterized by making the P-N junction face which having either flat or uneven face in a manner of uniformed thickness from the top surface, due to making a P or N type first layer by the Chemical Vapor Deposition on the basic plate and also to making a N or P type secondary layer on said first layer, while both of the layers being highly and pure controlled silicon, and the light reflectors being located at the out side of said each P or N type layer for concentrating the incoming light to the P-N junction portion.Type: GrantFiled: September 28, 1998Date of Patent: May 8, 2001Inventors: Shigeo Yamamoto, Mitsuhiro Maruyama
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Patent number: 6162706Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.Type: GrantFiled: July 29, 1998Date of Patent: December 19, 2000Assignee: STMicroelectronics S.A.Inventors: Didier Dutartre, Patrick Jerier
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Patent number: 6043139Abstract: Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.Type: GrantFiled: November 28, 1995Date of Patent: March 28, 2000Assignee: Lucent Technologies Inc.Inventors: David James Eaglesham, Hans-Joachim Ludwig Gossmann, John Milo Poate, Peter Adriaan Stolk
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Patent number: 6010937Abstract: A heteroepitaxial semiconductor device having reduced density of threading dislocations and a process for forming such a device. According to one embodiment, the device includes a substrate which is heat treated to a temperature in excess of 1000.degree. C., a film of arsenic formed on the substrate at a temperature between 800.degree. C. and 840.degree. C., a GaAs nucleation layer of less than 200 angstroms and formed at a temperature between about 350.degree. C. and 450.degree. C., and a plurality of stacked groups of layers of InP, wherein adjacent InP layers are formed at different temperatures.Type: GrantFiled: September 5, 1995Date of Patent: January 4, 2000Assignee: Spire CorporationInventors: Nasser H. Karam, Steven J. Wojtczuk
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Patent number: 6008110Abstract: A semiconductor substrate has a support substrate formed of monocrystal silicon, an oxide film formed on the support substrate and a thin film of monocrystal silicon formed on the oxide film. The support substrate is a high-concentration P-type substrate to which boron is so doped that a resistivity of the support base is 0.1 .OMEGA..cm or less. In manufacturing: boron is into the support base so that a resistivity of the support base is 0.1 .OMEGA..cm or less; a silicon substrate on which the thin film of monocrystal silicon is formed is heated at 1100.degree. C. or higher for 30 min or longer within a reducing atmosphere; the heat treated silicon substrate is attached to the high-concentration P-type support substrate via the oxide film formed on a surface of any one of the support substrate and the P-type silicon substrate and the attached substrates are heated at 950.degree. C. or higher for 10 min or longer to bond the attached substrates together; and the bonded silicon substrate is thinned.Type: GrantFiled: February 11, 1997Date of Patent: December 28, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shuichi Samata, Yoshiaki Matsushita, Yoko Inoue
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Patent number: 5967795Abstract: A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards its outermost edge.Type: GrantFiled: August 30, 1995Date of Patent: October 19, 1999Assignee: Asea Brown Boveri ABInventors: Mietek Bakowsky, Bo Bijlenga, Ulf Gustafsson, Christopher Harris, Susan Savage
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Patent number: 5913107Abstract: A pair of SiO.sub.2 stripe masks are formed on a p-InP substrate (31) with a separation of 1.5 .mu.m in ?011! direction and an optical waveguide including a p-InP clad layer (32), an active layer (33) and an n-InP clad layer (34) is formed on the p-InP substrate (31) at the 1.5 .mu.m exposed area according to MOVPE selective growth process. Both sides of the optical waveguide are buried with pnpn current blocking structure according to the MOVPE selective growth, wherein a p-InP layer (36) and n-InP layer (37) are formed, then a surface of the n-InP layer (37) is inverted to p-type to form a p-InP inversion layer (38) according to Zn open tube diffusion process carried out in MOVPE system, thereby the interconnection between the n-InP layer (37) and the n-InP clad layer (34) is prevented, and then a p-InP layer (39) and n-InP layer (40) are formed. An n-InP layer (41) is formed thereon.Type: GrantFiled: June 22, 1998Date of Patent: June 15, 1999Assignee: NEC CorporationInventor: Yasutaka Sakata
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Patent number: 5756375Abstract: Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes and hetrojunction bipolar transistors with doped and undoped GaAs layers, AlGaAs and InGaAs.Type: GrantFiled: June 14, 1996Date of Patent: May 26, 1998Assignee: Texas Instruments IncorporatedInventors: Francis G. Celii, Walter M. Duncan, Tae S. Kim
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Patent number: 5733815Abstract: A method of simultaneously forming a gallium arsenide p-i-n structure having p, i, and n regions, which includes heating to dissolve gallium arsenide in a solvent such as bismuth or gallium to form a saturated solution of gallium arsenide in the solvent, contacting the solution with a gaseous mixture, which mixture includes hydrogen, water vapor and products of reactions between the hydrogen and the water vapor with the solvent and with silicon dioxide, to form a contacted solution, coating a suitably selected substrate, such as a group III-V compound such as gallium arsenide, with the contacted solution, cooling the coated substrate to precipitate gallium arsenide from the contacted solution onto the substrate, and removing the substrate coated with a layer of gallium arsenide having a p-i-n structure which constitutes the product having an i region dopant concentration of less than about 10.sup.12 cm.sup.-3.Type: GrantFiled: November 18, 1994Date of Patent: March 31, 1998Assignee: Ramot University Authority for Applied Research & Industrial Development Ltd.Inventors: German Ashkinazi, Mark Leibovich, Boris Meyler, Menachem Nathan, Leonid Zolotarevski, Olga Zolotarevski
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Patent number: 5633180Abstract: A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy.Type: GrantFiled: June 1, 1995Date of Patent: May 27, 1997Assignee: Harris CorporationInventor: George Bajor