Plural Fluid Growth Steps With Intervening Diverse Operation Patents (Class 438/493)
  • Patent number: 10388790
    Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min-hwa Chi, Ajey Jacob, Abhijeet Paul
  • Patent number: 9899489
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 9793104
    Abstract: Provided is a method of epitaxial deposition, which involves dry-etching a semiconductor substrate with a fluorine containing species and exposing the dry-etched substrate to hydrogen atoms, prior to epitaxially depositing a semiconductor layer to the surface of the substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 17, 2017
    Assignee: AIXTRON SE
    Inventors: Maxim Kelman, Shahab Khandan, Scott Dunham, Tac van Huynh, Kenneth B. K. Teo
  • Patent number: 9608067
    Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Hong He, Juntao Li
  • Patent number: 9530643
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9343874
    Abstract: A semiconductor device comprising a silicon substrate on which is grown a <100 nm thick epilayer of AlAs or related compound, followed by a compound semiconductor other than GaN buffer layer. Further III-V compound semiconductor structures can be epitaxially grown on top. The AlAs epilayer reduces the formation and propagation of defects from the interface with the silicon, and so can improve the performance of an active structure grown on top.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: May 17, 2016
    Assignee: UCL BUSINESS PLC
    Inventors: Huiyun Liu, Andrew David Lee, Alwyn John Seeds
  • Patent number: 9093475
    Abstract: A method is provided for forming a printed top gate thin film transistor (TFT) with a short channel length. The method provides a substrate with a low surface energy top surface. A metal ink line is continuously printed across a region of the substrate top surface, and in response to the surface tension of the printed metal ink, discrete spherical ink caps are formed in the region. Then, the surface energy of the substrate top surface in the region is increased. A source metal ink line is printed overlying a source spherical ink cap contact, and a drain metal ink line, parallel to the source metal ink line, is printed overlying a drain spherical ink cap contact. After depositing a semiconductor film, a channel is formed in the semiconductor film between the source and drain spherical ink cap contacts having a channel length equal to the first distance.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: July 28, 2015
    Assignee: Sharp Laboratories of America, Inc
    Inventors: Kurt Ulmer, Kanan Puntambekar
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9040465
    Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B Phatak, Venkat Ananthan, Wayne R French
  • Patent number: 9029245
    Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: May 12, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Ana Claudia Arias
  • Publication number: 20150123146
    Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Bharat KRISHNAN, Jody A. FRONHEISER, Jinping LIU, Bongki LEE
  • Publication number: 20150118800
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 30, 2015
    Inventors: Young-jo TAK, Jae-won LEE, Young-soo PARK, Jun-youn KIM
  • Patent number: 8969994
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli
  • Publication number: 20150050753
    Abstract: Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 19, 2015
    Inventors: Swaminathan T. SRINIVASAN, Atif M. NOORI, David K. CARLSON
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8946005
    Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je-Hun Lee, Do-Hyun Kim, Eun-Guk Lee, Chang-Oh Jeong
  • Publication number: 20140370634
    Abstract: A method for fabricating a nitride semiconductor thin film includes preparing a first nitride single crystal layer doped with an n-type impurity. A plurality of etch pits are formed in a surface of the first nitride single crystal layer by applying an etching gas thereto. A second nitride single crystal layer is grown on the first nitride single crystal layer having the etch pits formed therein.
    Type: Application
    Filed: April 10, 2014
    Publication date: December 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keon Hun LEE, Min Ho KIM, Jong Uk SEO, Suk Ho YOON, Kee Won LEE, Sang Don LEE, Ho Chul LEE
  • Patent number: 8872308
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Publication number: 20140235005
    Abstract: A method of producing a p-type nitride semiconductor includes growing a first nitride semiconductor layer doped with a first concentration of a p-type impurity. The first nitride semiconductor layer is annealed to activate the p-type impurity. A second nitride semiconductor layer doped with a second concentration of a p-type impurity is grown on the first nitride semiconductor layer. The second concentration is higher than the first concentration.
    Type: Application
    Filed: December 15, 2013
    Publication date: August 21, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Hyun LEE, Ki Sung KIM, Bum Joon KIM, Tan Sakong, Suk Ho YOON, Jae Deok JEONG
  • Publication number: 20140191372
    Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 10, 2014
    Inventors: Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 8765500
    Abstract: The present disclosure involves a method of packaging a light-emitting diode (LED). According to the method, a group of metal pads and a group of LEDs are provided. The group of LEDs is attached to the group of metal pads, for example through a bonding process. After the LEDs are attached to the metal pads, each LED is spaced apart from adjacent LEDs. Also according to the method, a phosphor film is coated around the group of LEDs collectively. The phosphor film is coated on top and side surfaces of each LED and between adjacent LEDs. A dicing process is then performed to slice through portions of the phosphor film located between adjacent LEDs. The dicing process divides the group of LEDs into a plurality of individual phosphor-coated LEDs.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Ming Lin
  • Patent number: 8759199
    Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mook Choi, Jae-young Choi, Jin Zhang, Guo Hong
  • Patent number: 8753920
    Abstract: Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. MAn ??(Formula 1) Herein, M is a metal ion, A is an organic ligand which includes ?-substituted carboxylate, and n is a natural number.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo Sung Kim, Doo-Hyoung Lee, Yeon-Taek Jeong, Ki-Beom Lee, Young-Min Kim, Tae-Young Choi, Seon-Pil Jang, Kang-Moon Jo
  • Patent number: 8729672
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 20, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Patent number: 8716836
    Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: May 6, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masahiko Hata, Taketsugu Yamamoto, Kazumi Wada
  • Publication number: 20140110758
    Abstract: The semiconductor device is formed in the form of a GaN-based stacked layer including an n-type drift layer 4, a p-type layer 6, and an n-type top layer 8. The semiconductor device includes a regrown layer 27 formed so as to cover a portion of the GaN-based stacked layer that is exposed to an opening 28, the regrown layer 27 including a channel. The channel is two-dimensional electron gas formed at an interface between the electron drift layer and the electron supply layer. When the electron drift layer 22 is assumed to have a thickness of d, the p-type layer 6 has a thickness in the range of d to 10d, and a graded p-type impurity layer 7 whose concentration decreases from a p-type impurity concentration in the p-type layer is formed so as to extend from a (p-type layer/n-type top layer) interface to the inside of the n-type top layer.
    Type: Application
    Filed: June 8, 2011
    Publication date: April 24, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yu Saitoh, Masaya Okada, Masaki Ueno, Makoto Kiyama
  • Patent number: 8697606
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 15, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Patent number: 8664028
    Abstract: (a) On a growth substrate, a void-containing layer that is made of a group III nitride compound semiconductor and contains voids is formed. (b) On the void-containing layer, an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids is formed. (c) On the n-type layer, an active layer made of a group III nitride compound semiconductor is formed. (d) On the active layer, a p-type layer made of a p-type group III nitride compound semiconductor is formed. (e) A support substrate is bonded above the p-type layer. (f) The growth substrate is peeled off at the boundary where the voids are produced. In the above step (a) or (b), the supply of at least part of the materials that form the layer is decreased, while heating, before the voids are closed.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 4, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yasuyuki Shibata, Ji-Hao Liang
  • Publication number: 20140048902
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Applicant: AVOGY , INC.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edward, Hui Nie, Isik C. Kizilyalli
  • Patent number: 8653563
    Abstract: A semiconductor device includes: a substrate comprised of gallium nitride; an active layer provided on the substrate; a first buffer layer that is provided between the substrate and the active layer and is comprised of indium aluminum nitride (InxAl1?xN, 0.15?x?0.2); and a spacer layer that is provided between the first buffer layer and the active layer and is comprised of aluminum nitride having a thickness of 1 nm or more to 10 nm or less.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumio Yamada, Takeshi Araya
  • Patent number: 8637373
    Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-Sung Chung, Dong-Suk Shin, Dong-Hyuk Kim, Myung-Sun Kim
  • Patent number: 8633569
    Abstract: III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: January 21, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8633040
    Abstract: The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier, core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanocrystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: January 21, 2014
    Assignee: The “Nanotech-Dubna” Trial Center for Science and Technology
    Inventors: Roman Vladimirovich Novichkov, Maxim Sergeevich Wakstein, Ekaterina Leonidovna Nodova, Aleksey Olegovich Maniashin, Irina Ivanovna Taraskina
  • Publication number: 20140001484
    Abstract: A method of manufacturing a gallium nitride (GaN) substrate and a GaN substrate manufactured by the same. The method includes the steps of growing a GaN film on a base substrate and separating the base substrate from the GaN film. The step of growing the GaN film includes forming pits in the GaN film, the pits inducing an inversion domain boundary to be formed inside the GaN film. The GaN substrate can have a predetermined thickness with which it can be handled during layer transfer (LT) processing, and the warping of the GaN substrate can be minimized, thereby preventing cracks due to warping.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 2, 2014
    Inventors: Sungkeun Lim, Boik Park, KwangJe Woo, Woorihan Kim, Joon Hoi Kim, Cheolmin Park, Junyoung Bae, DongYong Lee, Wonjo Lee, JunSung Choi
  • Patent number: 8610121
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Alexander Gorer, David E. Lazovsky
  • Publication number: 20130288464
    Abstract: A method for making an epitaxial structure includes following steps. A substrate having an epitaxial growth surface is provided. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A graphene layer is applied on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.
    Type: Application
    Filed: December 13, 2012
    Publication date: October 31, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: YANG WEI, SHOU-SHAN FAN
  • Patent number: 8551870
    Abstract: Epitaxially coated semiconductor wafers are produced by minimally the following steps in the order specified: (a) depositing an epitaxial layer on one side of a semiconductor wafer; (b) first polishing the epitaxially coated side of the semiconductor wafer with a polishing pad with fixed abrasive while supplying a polishing solution which is free of solids; (c) CMP polishing of the epitaxially coated side of the semiconductor wafer with a soft polishing pad which contains no fixed abrasive, while supplying a polishing agent suspension; (d) depositing another epitaxial layer on the previously epitaxially coated and polished side of the semiconductor wafer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 8, 2013
    Assignee: Siltronic AG
    Inventors: Juergen Schwandner, Roland Koppert
  • Patent number: 8501597
    Abstract: A method of fabricating a group III-nitride semiconductor includes the following steps of: forming a first patterned mask layer with a plurality of first openings deposited on an epitaxial substrate; epitaxially growing a group III-nitride semiconductor layer over the epitaxial substrate and covering at least part of the first patterned mask layer; etching the group III-nitride semiconductor layer to form a plurality of second openings, which are substantially at least partially aligned with the first openings; and epitaxially growing the group III-nitride semiconductor layer again.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: August 6, 2013
    Assignee: Academia Sinica
    Inventors: Yuh-Jen Cheng, Ming-Hua Lo, Hao-Chung Kuo
  • Patent number: 8501598
    Abstract: A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S1) of forming a first epitaxial layer; a trench forming step (S2) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S3, S4, S5) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: August 6, 2013
    Assignees: Sumco Corporation, Denso Corporation
    Inventors: Syouji Nogami, Hitoshi Goto, Takumi Shibata, Tsuyoshi Yamamoto
  • Patent number: 8502310
    Abstract: Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm?3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle ? of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle ?. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: August 6, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Kazuhide Sumiyoshi, Yu Saitoh, Makoto Kiyama
  • Patent number: 8461029
    Abstract: A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 11, 2013
    Assignee: Lattice Power (JIANGXI) Corporation
    Inventors: Fengyi Jiang, Li Wang, Chunlan Mo, Wenqing Fang
  • Publication number: 20130130481
    Abstract: Methods and apparatus for generating and delivering atomic hydrogen to the growth front during the deposition of a III-V film are provided. The apparatus adapts HWCVD technology to a system wherein the Group III precursor and the Group V precursor are delivered to the surface in isolated processing environments within the system. Multiple HWCVD units may be incorporated so that the atomic hydrogen parameters may be varied in a combinatorial manner for the development of III-V films.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Thai Cheng Chua, Timothy Joseph Franklin, Philip Kraus
  • Patent number: 8440017
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 14, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Publication number: 20130095642
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 18, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Feng Nieh, Chung-Yi Yu, Hung-Ta Lin
  • Publication number: 20130082278
    Abstract: A nitride semiconductor device and a method to produce the same are disclosed. The method includes steps of sequentially growing a channel layer and a first layer with bandgap energy Eg greater than that of channel layer; forming a gate replica on the first layer; selectively growing a second layer with Eg also greater than or equal to Eg of the channel layer; removing the gate replica to form a recess in the second layer; and forming the gate electrode in the recess and onto the first layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8399290
    Abstract: A method is provided for fabricating a printed organic thin film transistor (OTFT) with a patterned organic semiconductor using a fluropolymer banked crystallization well. In the case of a bottom gate OTFT, a substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode, and source (S) and drain (D) electrodes are formed overlying the gate dielectric. A gate dielectric OTFT channel interface region is formed between the S/D electrodes. A well with fluropolymer containment and crystallization banks is then formed, to define an organic semiconductor print area. The well is filled with an organic semiconductor, covering the S/D electrodes and the gate dielectric OTFT channel interface. Then, the organic semiconductor is crystallized. Predominant crystal grain nucleation originates from regions overlying the S/D electrodes. As a result, an organic semiconductor channel is formed, interposed between the S/D electrodes.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: March 19, 2013
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Kanan Puntambekar, Lisa H. Stecker, Kurt Ulmer
  • Publication number: 20130065341
    Abstract: According to one embodiment, a method for fabricating a stacked nitride-compound semiconductor structure includes forming a first protection film on a second surface of a substrate, forming a first nitride-compound semiconductor layer on the first surface of the substrate, forming a second protection film on the first nitride-compound semiconductor layer, removing the first protection film to expose the second surface of the substrate, forming a second nitride-compound semiconductor layer on the second surface of the substrate, and removing the second protection film to expose the first surface of the second nitride-compound semiconductor layer.
    Type: Application
    Filed: March 9, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro KAI, Hideto Sugawara
  • Patent number: 8389445
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Thomas R. Boussie, Alexander Gorer, David E. Lazovsky
  • Patent number: 8367587
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: February 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Thomas R. Boussie, Alexander Gorer, David E. Lazovsky
  • Publication number: 20130001586
    Abstract: A method for forming a substrate includes forming a base layer comprising a Group III-V material on a substrate, cooling the base layer and inducing cracks in the base layer, and forming a bulk layer comprising a Group III-V material on the base layer after cooling.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Applicant: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Bernard Beaumont, Jean-Pierre Faurie