Doping Of Semiconductor Patents (Class 438/495)
  • Patent number: 9214396
    Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Gerd Zschaetzsch
  • Patent number: 9112057
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a semiconducting surface and forming a first epitaxial layer on the semiconducting surface. The first epitaxial layer includes a first semiconducting material doped in-situ with at least one dopant of a first conductivity type. The method also includes adding at least one dopant of a second conductivity type into one portion of the substrate to define at least one counter-doped region with an overall doping of the second conductivity type and at least one other region with an overall doping of the first conductivity type in the other portions of substrate. The method further includes forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a second semiconducting material that is substantially undoped.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Sameer Pradhan, Dalong Zhao, Lingquan Wang, Pushkar Ranade, Lance Scudder
  • Patent number: 9023720
    Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 5, 2015
    Assignee: Sen Corporation
    Inventors: Genshu Fuse, Michiro Sugitani
  • Publication number: 20150076664
    Abstract: One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Peter IRSIGLER, Thomas NEIDHART, Guenter SCHAGERL, Hans-Joachim SCHULZE
  • Publication number: 20150069416
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chiharu OTA, Kazuto TAKAO, Johji NISHIO, Takashi SHINOHE
  • Patent number: 8969184
    Abstract: A method for fabricating a porous semiconductor body region, including producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and filling the trench with a semiconductor material of the semiconductor body.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: March 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Francisco Javier Santos Rodriguez
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20140231969
    Abstract: A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned.
    Type: Application
    Filed: April 24, 2014
    Publication date: August 21, 2014
    Applicant: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Armin Willmeroth, Michael Rueb, Holger Kapels
  • Publication number: 20140231751
    Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
    Type: Application
    Filed: August 13, 2013
    Publication date: August 21, 2014
    Inventors: Makoto WADA, Hisao MIYAZAKI, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Tadashi SAKAI
  • Patent number: 8785306
    Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Patent number: 8729637
    Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: May 20, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
  • Publication number: 20140117381
    Abstract: Disclosed is an epitaxial wafer including a substrate and an epitaxial structure disposed on the substrate, wherein the epitaxial structure is doped with an n-type or p-type dopant and has a doping uniformity of 10% or less.
    Type: Application
    Filed: October 31, 2013
    Publication date: May 1, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Seok Min Kang, Ji Hye Kim
  • Patent number: 8685809
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Publication number: 20140050242
    Abstract: A semiconductor device includes a substrate supporting a plurality of layers that include at least one modulation doped quantum well (QW) structure offset from a quantum dot in quantum well (QD-in-QW) structure. The modulation doped QW structure includes a charge sheet spaced from at least one QW by a spacer layer. The QD-in-QW structure has QDs embedded in one or more QWs. The QD-in-QW structure can include at least one template/emission substructure pair separated by a barrier layer, the template substructure having smaller size QDs than the emission substructure. A plurality of QD-in-QW structures can be provided to support the processing (emission, absorption, amplification) of electromagnetic radiation of different characteristic wavelengths (such as optical wavelengths in range from 1300 nm to 1550 nm).
    Type: Application
    Filed: June 19, 2013
    Publication date: February 20, 2014
    Inventor: Geoff W. Taylor
  • Publication number: 20140034997
    Abstract: A method for manufacturing a bipolar punch-through semiconductor device is disclosed, which includes providing a wafer having a first and a second side, wherein on the first side a high-doped layer of the first conductivity type having constant high doping concentration is arranged; epitaxially growing a low-doped layer of the first conductivity type on the first side; performing a diffusion step by which a diffused inter-space region is created at the inter-space of the layers; creating at least one layer of the second conductivity type on the first side; and reducing the wafer thickness within the high-doped layer on the second side so that a buffer layer is created, which can include the inter-space region and the remaining part of the high-doped layer, wherein the doping profile of the buffer layer decreases steadily from the doping concentration of the high-doped region to the doping concentration of the drift layer.
    Type: Application
    Filed: October 4, 2013
    Publication date: February 6, 2014
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Arnost KOPTA, Thomas CLAUSEN, Maxi ANDENNA
  • Publication number: 20140001514
    Abstract: A semiconductor device includes a device region. The device region includes at least one device region section including dopant atoms of a first doping type and with a first doping concentration of at least 1E16 cm?3 and dopant atoms of a second doping type and with a second doping concentration of at least 1E16 cm?3.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz Hirler, Anton Mauder, Helmut Strack, Frank Kahlmann, Gerhard Miller
  • Publication number: 20130337640
    Abstract: A method for fabricating a porous semiconductor body region, including producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and filling the trench with a semiconductor material of the semiconductor body.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 19, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Hans-Joachim SCHULZE, Anton MAUDER, Francisco Javier SANTOS RODRIGUEZ
  • Patent number: 8558316
    Abstract: A semiconductor device comprises a substrate, a gate structure formed on the substrate, a channel region below the gate structure in the substrate, a first source/drain region and a second source/drain region located at opposite side of the gate structure, a first lightly-doped drain (LDD) junction region formed between the first source/drain region and one end of the channel region, a second lightly-doped drain (LDD) junction region formed between the second source/drain region and the other end of the channel region, a metal silicide layer having a first metal formed on the first and second source/drain regions, an insulating layer formed on the metal silicide layer and the gate structure having a first opening to expose the metal silicide layer, and a conductive layer having the first metal and filling the first opening to contact the metal silicide layer.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-ki Jung
  • Patent number: 8546247
    Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hidenobu Fukutome, Youichi Momiyama
  • Patent number: 8501141
    Abstract: An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: August 6, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka University
    Inventors: Takayuki Sato, Seiji Nagai, Makoto Iwai, Shuhei Higashihara, Yusuke Mori, Yasuo Kitaoka
  • Publication number: 20130168738
    Abstract: Provided is a semiconductor wafer including a base wafer, a first crystalline layer, a second crystalline layer, and an insulating layer that are positioned in the stated order, the semiconductor wafer further including: a third crystalline layer positioned either between the first crystalline layer and the second crystalline layer or between the base wafer and the first crystalline layer. The second crystalline layer and the third crystalline layer are made of a crystal that either lattice matches or pseudo lattice matches a crystal making the first crystalline layer, and has a wider band gap than the crystal making the first crystalline layer. The third crystalline layer includes a first atom that will be a donor or an acceptor. When the third crystalline layer includes a first atom that will be a donor, the second crystalline layer includes a second atom that will be an acceptor.
    Type: Application
    Filed: February 26, 2013
    Publication date: July 4, 2013
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: SUMITOMO CHEMICAL COMPANY, LIMITED
  • Patent number: 8470712
    Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 25, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Michel Bruel, Bernard Aspar, Christophe Maleville
  • Publication number: 20130122676
    Abstract: The present disclosure provides methods of semiconductor device fabrication for 3D devices. One method includes provide a substrate having a recess and forming a doping layer on the substrate and in the recess. The substrate is then annealed. The annealing drives dopants of a first type from the doping layer into the substrate. This can form a doped region that may be the source/drain extension of the 3D device. An epitaxial region is then grown in the recess. The epitaxial region can form the source/drain region of the 3D device.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventor: Pei-Ren Jeng
  • Publication number: 20130075855
    Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Publication number: 20130072004
    Abstract: The present invention is directed to a method for forming multiple active components, such as bipolar transistors, MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of increasing operation voltage over an existing device of same functionality by adding a few steps in the early manufacturing process of the existing device therefore without drastically affecting the device performance.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 8399340
    Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akihiko Ohi
  • Publication number: 20130056795
    Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
    Type: Application
    Filed: December 22, 2011
    Publication date: March 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
  • Patent number: 8383495
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: February 26, 2013
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Maik Haeberlen, Joerg Lindner, Bernd Stritzker
  • Patent number: 8350270
    Abstract: A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: January 8, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shoyu Watanabe, Shuhei Nakata, Kenichi Ohtsuka
  • Patent number: 8334156
    Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 ?m. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol Kyu Kim, Yung Ho Ryu, Soo Min Lee, Jong In Yang, Tae Hyung Kim
  • Patent number: 8231726
    Abstract: An object of the present invention is to obtain, with respect to a semiconductor light-emitting element using a group III nitride semiconductor substrate, a semiconductor light-emitting element having an excellent light extraction property by selecting a specific substrate dopant and controlling the concentration thereof. The semiconductor light-emitting element comprises a substrate composed of a group III nitride semiconductor comprising germanium (Ge) as a dopant, an n-type semiconductor layer composed of a group III nitride semiconductor formed on the substrate, an active layer composed of a group III nitride semiconductor formed on the n-type semiconductor layer, and a p-type semiconductor layer composed of a group III nitride semiconductor formed on the active layer in which the substrate has a germanium (Ge) concentration of 2×1017 to 2×1019 cm?3.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: July 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Hisashi Minemoto, Yasuo Kitaoka, Yasutoshi Kawaguchi, Yasuhito Takahashi, Yoshiaki Hasegawa
  • Patent number: 8198628
    Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: June 12, 2012
    Assignee: Soitec
    Inventors: Robert Langer, Hacène Lahreche
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8163635
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Sen Corporation
    Inventors: Michiro Sugitani, Genshu Fuse
  • Publication number: 20120040521
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventor: Xingbi CHEN
  • Patent number: 8102026
    Abstract: To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value ?? obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×1017 cm?3.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 24, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Eri, Takeshi Meguro
  • Publication number: 20110306191
    Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: FUJI ELECTRONIC CO., LTD.
    Inventor: Akihiko OHI
  • Patent number: 8021947
    Abstract: In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, James Sellers, Prasad Venkatraman
  • Publication number: 20110151650
    Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 23, 2011
    Applicant: SILTRONIC AG
    Inventors: Brian Murphy, Maik Häberlen, Jörg Lindner, Bernd Stritzker
  • Patent number: 7959733
    Abstract: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 14, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Pao-Hwa Chou, Chaeho Kim
  • Publication number: 20110068397
    Abstract: Power devices and associated methods of manufacturing are disclosed herein. In one embodiment, a power device includes a drain at a first end, a source and a gate at a second end, and a drift region between the drain at the first end and the source at the second end. The drift region includes a p-type dopant column juxtaposed with an n-type dopant column. The p-type dopant column and the n-type dopant column together have a width less than 12 microns.
    Type: Application
    Filed: September 24, 2009
    Publication date: March 24, 2011
    Inventor: Donald R. Disney
  • Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Publication number: 20110012133
    Abstract: A silicon carbide MOSFET that exhibits a high source-to-drain withstand voltage and that involves a smaller difference between gate-to-drain capacitance achieved in an activated state and gate-to-drain capacitance achieved in a deactivated state. A silicon carbide drift layer of a first conductivity type is provided on a silicon carbide substrate of a first conductivity type; a pair of base regions are provided in a surface layer portion of the silicon carbide drift layer and exhibit a second conductivity type; a pair of source regions are provided in interiors of surface layer portions of the pair of base regions and exhibit a first conductivity type; and semi-insulating regions are provided between the silicon carbide substrate and the pair of base regions.
    Type: Application
    Filed: March 4, 2009
    Publication date: January 20, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shoyu Watanabe, Shuhei Nakata, Kenichi Ohtsuka
  • Patent number: 7718518
    Abstract: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: May 18, 2010
    Assignee: ASM International N.V.
    Inventors: Peter Marc Zagwijn, Theodorus Gerardus Maria Oosterlaken, Steven R. A. Van Aerde, Pamela René Fischer
  • Publication number: 20100078775
    Abstract: A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Armin Willmeroth, Michael Rueb, Holger Kapels
  • Publication number: 20090267174
    Abstract: A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a semiconductor material applied in epitaxial growth zones, wherein the epitaxial growth zones include an epitaxially grown semiconductor material which is non-doped to lightly doped. Towards the substrate, the epitaxial growth zones are provided with a first conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of a second, complementary conduction type. Towards the front side, the epitaxial growth zones are provided with a second, complementary conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of the first conduction type.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 29, 2009
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Armin Willmeroth, Michael Rueb
  • Publication number: 20090258478
    Abstract: Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional embodiments are described.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
    Applicant: Atmel Corporation
    Inventor: Darwin G. Enicks
  • Patent number: 7595260
    Abstract: A bulk-doped semiconductor may be at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may have a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: September 29, 2009
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Publication number: 20090189192
    Abstract: The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer (5), on a substrate (1), the substrate (1) comprising at least a Ge surface (3), preferably with hexagonal symmetry. The method comprises heating the substrate (1) to a nitridation temperature between 400° C. and 940° C. while exposing the substrate (1) to a nitrogen gas flow and subsequently depositing the group III-nitride layer, e.g. GaN layer (5), onto the Ge surface (3) at a deposition temperature between 100° C. and 940° C. By a method according to embodiments of the invention, a group III-nitride layer, e.g. GaN layer (5), with good crystal quality may be obtained. The present invention furthermore provides a group III-nitride/substrate structure formed by the method according to embodiments of the present invention and a semiconductor device comprising at least one such structure.
    Type: Application
    Filed: July 9, 2007
    Publication date: July 30, 2009
    Inventors: Ruben Lieten, Stefan Degroote
  • Patent number: 7550365
    Abstract: An electrical device includes an interconnect and a pair substrates at least one of which includes an integrated circuit, the pair of substrates being bonded together by a bond that includes a structure having multiple widths and a composition that is selected from the group consisting of a graded material and a first material upon a second material.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: June 23, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Timothy R. Emery, William J. Edwards, Donald W. Schulte