Coating Of Semiconductive Substrate With Nonsemiconductive Material Patents (Class 438/496)
  • Patent number: 10043662
    Abstract: A method of forming a semiconductor substrate including forming a base layer of a Group 13-15 material on a growth substrate during a growth process, forming a mask having mask regions and gap regions overlying the base layer during the growth process, and preferentially removing a portion of the base layer underlying the mask during the growth process.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 7, 2018
    Assignee: SAINT-GOBAIN CRISTAUX ET DETECTEURS
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 9153437
    Abstract: Methods for forming inorganic nanostructures are provided. The methods create the inorganic nanostructures by positioning a writing electrode (e.g., a conductive “stamp”) spaced nanometers above a substrate such that a precursor is intermediate the two. Applying an electric field, a voltage bias, an ionic current, or an electronic current between the writing electrode and the substrate converts the precursor into an inorganic solid material (e.g., a semiconductor such as silicon or germanium) in the area of the writing electrode.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 6, 2015
    Assignee: University of Washington through its Center for Commercialization
    Inventors: Marco Rolandi, Hideki Sato, Stephanie Vasko, Michael Brasino, Adnan Kapetanovic, Vamsi Talla
  • Patent number: 9070881
    Abstract: A method of manufacturing an organic semiconductor thin film includes coating an organic semiconductor solution on a substrate, and shearing the organic semiconductor solution in a direction that results in a shearing stress being applied to the organic semiconductor solution to form the organic semiconductor thin film, wherein a speed of the shearing is controlled such that an intermolecular distance of the organic semiconductor solution is adjusted.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: June 30, 2015
    Assignees: Samsung Electronics Co., LTD., The Board of Trustees of the Leland Stanford Junior University
    Inventors: Zhenan Bao, Gaurav Giri, Sang-yoon Lee, Stefan Mannsfeld
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Patent number: 8963295
    Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 24, 2015
    Assignee: Tsinghua University
    Inventors: Jing Wang, Renrong Liang, Lei Guo, Jun Xu
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8883564
    Abstract: A process for producing a substrate, which comprises processing an aluminum/graphite composite into plates having a thickness of 0.5-3 mm using a multi-wire saw under the following conditions (1) to (4): (1) the wires have abrasive grains bonded thereto which are one or more substances selected from diamond, C—BN, silicon carbide, and alumina and have an average particle diameter of 10-100 ?m; (2) the wires have a diameter of 0.1-0.3 mm; (3) the wires are run at a rate of 100-700 m/min; and (4) the composite is cut at a rate of 0.1-2 mm/min. The aluminum/graphite composite has a surface roughness (Ra) of 0.1-3 ?m, a thermal conductivity at 25° C. of 150-300 W/mK, a ratio of the maximum to the minimum value of thermal conductivity in three perpendicular directions of 1-1.3, a coefficient of thermal expansion at 25-150° C. of 4×106 to 7.5×10?6/K, a ratio of the maximum to the minimum value of coefficient of thermal expansion in three perpendicular directions of 1-1.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: November 11, 2014
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Hideki Hirotsuru, Satoshi Higuma, Shinya Narita, Yoshihiko Tsujimura
  • Patent number: 8841199
    Abstract: A method of forming a semiconductor device is provided. The method includes preparing a substrate having a transistor region and an alignment region, forming a first trench and a second trench in the substrate of the transistor region and in the substrate of the alignment region, respectively, forming a drift region in the substrate of the transistor region, forming two third trenches respectively adjacent to two ends of the drift region, and forming an isolation pattern in the first trench, a buried dielectric pattern in the second trench, and dielectric patterns in the two third trenches, respectively. A depth of the first trench is less than a depth of the third trenches, and the depth of the first trench is equal or substantially equal to a depth of the second trench.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yongdon Kim
  • Patent number: 8796121
    Abstract: A method of forming a REO dielectric layer and a layer of a-Si between a III-N layer and a silicon substrate. The method includes depositing single crystal REO on the substrate. The single crystal REO has a lattice constant adjacent the substrate matching the lattice constant of the substrate and a lattice constant matching a selected III-N material adjacent an upper surface. A uniform layer of a-Si is formed on the REO. A second layer of REO is deposited on the layer of a-Si with the temperature required for epitaxial growth crystallizing the layer of a-Si and the crystallized silicon being transformed to amorphous silicon after transferring the lattice constant of the selected III-N material of the first layer of REO to the second layer of REO, and a single crystal layer of the selected III-N material deposited on the second layer of REO.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 5, 2014
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun
  • Publication number: 20140213045
    Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Bum BAE, Eun Soo NAM, Jae Kyoung MUN, Sung Bock KIM, Hae Cheon KIM, Chull Won JU, Sang Choon KO, Jong-Won LIM, Ho Kyun AHN, Woo Jin CHANG, Young Rak PARK
  • Patent number: 8680693
    Abstract: The present invention provides a stacked organic light emitting device, comprising a first conductive layer, at least one intermediate conductive layer and a second conductive layer, and light emitting units disposed between the conductive layers, wherein at least two non-neighboring conductive layers among the conductive layers are conductive layers belonging to Group 1 such that they are electrically connected with each other to a common potential; at least one non-neighboring conductive layer among the conductive layers which are not electrically connected with the conductive layers belonging to Group 1 to a common potential are conductive layers belonging to Group 2 such that they are electrically connected with each other to a common potential; and the conductive layers belonging to Group 1 and the conductive layers belonging to Group 2 are connected with each other via a voltage regulator for alternately applying a positive voltage and a negative voltage.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: March 25, 2014
    Assignee: LG Chem. Ltd.
    Inventors: Min-Soo Kang, Jeoung-Kwen Noh, Jung-Hyoung Lee
  • Patent number: 8680507
    Abstract: A DBR/gallium nitride/aluminum nitride base grown on a silicon substrate includes a Distributed Bragg Reflector (DBR) positioned on the silicon substrate. The DBR is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the DBR, an inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 25, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8604486
    Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: December 10, 2013
    Assignee: International Rectifier Corporation
    Inventor: Zhi He
  • Patent number: 8592292
    Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 26, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, Jamal Ramdani
  • Publication number: 20130264598
    Abstract: A method can be used for producing a semiconductor layer sequence, which is based on a nitride compound semiconductor material and which comprises a microstructured outer surface. The method has the following steps: A) growing at least one first semiconductor layer of the semiconductor layer sequence on a substrate; B) applying an etch-resistant layer on the first semiconductor layer; C) growing at least one further semiconductor layer on the layer sequence obtained in step B); D) separating the semiconductor layer sequence from the substrate, a separating zone of the semiconductor layer sequence being at least partly removed; E) etching the obtained separating surface of the semiconductor layer sequence by an etching means such that a microstructuring of the first semiconductor layer is carried out and the microstructured outer surface is formed.
    Type: Application
    Filed: September 30, 2011
    Publication date: October 10, 2013
    Applicant: OSRAM OPTP SEMICONDUCTORS GMBH
    Inventors: Joachim Hertkorn, Tetsuya Taki, Jürgen Off
  • Publication number: 20130200388
    Abstract: A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, a Schottky electrode disposed in a first area on the Al-doped GaN layer, an AlGaN layer disposed in a second area on the Al-doped GaN layer, and an ohmic electrode disposed on the AlGaN layer. The first area is different from the second area.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 8, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Samsung Electronics Co., Ltd.
  • Patent number: 8501597
    Abstract: A method of fabricating a group III-nitride semiconductor includes the following steps of: forming a first patterned mask layer with a plurality of first openings deposited on an epitaxial substrate; epitaxially growing a group III-nitride semiconductor layer over the epitaxial substrate and covering at least part of the first patterned mask layer; etching the group III-nitride semiconductor layer to form a plurality of second openings, which are substantially at least partially aligned with the first openings; and epitaxially growing the group III-nitride semiconductor layer again.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: August 6, 2013
    Assignee: Academia Sinica
    Inventors: Yuh-Jen Cheng, Ming-Hua Lo, Hao-Chung Kuo
  • Patent number: 8497193
    Abstract: A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other gases such as hydrogen to increase oxidation rate, diluent gas such as nitrogen or O2, enter the chamber through another inlet. The chamber is maintained at a low pressure below 20 Torr and the substrate is advantageously maintained at a temperature less than 800° C. Alternatively, the oxidation may be performed in an LPCVD chamber including a pedestal heater and a showerhead gas injector in opposition to the pedestal.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 30, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yoshitaka Yokota, Sundar Ramamurthy, Vedapuram Achutharaman, Cory Czarnik, Mehran Behdjat, Christopher Olsen
  • Patent number: 8476739
    Abstract: A graphene-on-oxide substrate according to the present invention includes: a substrate having a metal oxide layer formed on its surface; and, formed on the metal oxide layer, a graphene layer including at least one atomic layer of the graphene. The graphene layer is grown generally parallel to the surface of the metal oxide layer, and the inter-atomic-layer distance between the graphene atomic layer adjacent to the surface of the metal oxide layer and the surface atomic layer of the metal oxide layer is 0.34 nm or less. Preferably, the arithmetic mean surface roughness Ra of the metal oxide layer is 1 nm or less.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: July 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Okai, Motoyuki Hirooka, Takashi Kyotani, Hironori Orikasa
  • Patent number: 8460977
    Abstract: A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8445317
    Abstract: Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Ha Jeong, Jung-Ho Kim, Kihyun Hwang, Yong-Hoon Son
  • Patent number: 8426296
    Abstract: The disclosed subject matter relates to systems and methods for preparing epitaxially textured polycrystalline films. In one or more embodiments, the method for making a textured thin film includes providing a precursor film on a substrate, the film includes crystal grains having a surface texture and a non-uniform degree of texture throughout the thickness of the film, wherein at least a portion of the this substrate is transparent to laser irradiation; and irradiating the textured precursor film through the substrate using a pulsed laser crystallization technique at least partially melt the film wherein the irradiated film crystallizes upon cooling to form crystal grains having a uniform degree of texture.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: April 23, 2013
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8409366
    Abstract: In a separation method of a nitride semiconductor layer, a graphene layer in the form of a single layer or two or more layers is formed on a surface of a first substrate. A nitride semiconductor layer is formed on the graphene layer so that the nitride semiconductor layer is bonded to the graphene layer with a bonding force due to regularity of potential at atomic level at an interface therebetween without utilizing covalent bonding. The nitride semiconductor layer is separated from the first substrate with a force which is greater than the bonding force between the nitride semiconductor layer and the graphene layer, or greater than a bonding force between respective layers of the graphene layer.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: April 2, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Masaaki Sakuta, Akihiro Hashimoto
  • Patent number: 8377625
    Abstract: A method of producing a copolymer solution for semiconductor lithography having a copolymer and a solvent for coating film formation, which copolymer contains at least one repeating unit selected from the group consisting of: a repeating unit (A) having a hydroxyl group; a repeating unit (B) having a structure in which a hydroxyl group is protected by a group which suppresses dissolution into an alkaline developer and which dissociates in the action of an acid; a repeating unit (C) having a lactone structure; and a repeating unit (D) having a cyclic ether structure, the difference in the copolymer concentration among a plurality of containers which were filled with copolymer solution from the same manufacturing lot is not more than a certain range, or the method includes a certain production step.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: February 19, 2013
    Assignee: Maruzen Petrochemical Co., Ltd.
    Inventors: Takanori Yamagishi, Ichiro Kato, Akiko Tanaka, Miyako Asano
  • Patent number: 8372671
    Abstract: Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Patent number: 8368118
    Abstract: A semiconductor structure includes a substrate, a thermally and electrically conductive mask positioned upon the substrate, and an epitaxial lateral over growth (ELOG) material positioned upon the thermally and electrically conductive mask.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: February 5, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shih-Yuan Wang, Lars Helge Thylen, Sagi Varghese Mathai
  • Publication number: 20120313106
    Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventor: Zhi He
  • Patent number: 8242004
    Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first spin-on-dielectric layer is formed over a semiconductor substrate. An abnormal oxidation of the first spin-on-dielectric layer is carried out. A surface of the first spin-on-dielectric layer is removed. A second spin-on-dielectric layer is formed over the first spin-on-dielectric layer. A non-abnormal oxidation of the first and second spin-on-dielectric layers is carried out to modify the second spin-on-dielectric layer without modifying the first spin-on-dielectric layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 14, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Jiro Miyahara
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8178429
    Abstract: Fabrication of a semiconductor structure is achieved by using a Dip Pen Nanolithography (DPN) tip to apply a metal catalyst to a prepared substrate. The catalyst is applied in a predetermined pattern, and crystal growth is established at the catalyst site.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 15, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ryan P. Lu, Ayax D. Ramirez, Stephen D. Russell
  • Patent number: 8173525
    Abstract: Systems and methods of nanomaterial transfer are described. A method of nanomaterial transfer involving fabricating a template and synthesizing nanomaterials on the template. Subsequently, the nanomaterials are transferred to a substrate by pressing the template onto the substrate. In some embodiments, the step of transferring the nanomaterials involves pressing the template onto the substrate such that the nanomaterials are embedded below a surface layer of the substrate. In some embodiments, the temperature of the plurality of nanomaterials is raised to assist the transfer of the nanomaterials to the substrate.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 8, 2012
    Assignee: Georgia Tech Research Corporation
    Inventors: Samuel Graham, Jr., William P. King, Ching-ping Wong
  • Patent number: 8168518
    Abstract: A gate insulating film (13) is formed on a substrate (1) so as to cover a gate electrode (11), and an amorphous silicon film (semiconductor thin film) (15) is further formed. A light absorption layer (19) is formed thereon through a buffer layer (17). Energy lines Lh are applied to the light absorption layer (19) from a continuous-wave laser such as a semiconductor laser. This oxidizes only a surface side of the light absorption layer Lh and produces a beautiful crystalline silicon film (15a) obtained by crystallizing the amorphous silicon film (15) using heat generated by thermal conversion of the energy lines Lh at the light absorption layer (19) and heat of the oxidation reaction. This provides a method for crystallizing a thin film with good controllability at low costs achieved with simpler process.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Sony Corporation
    Inventors: Nobuhiko Umezu, Koichi Tsukihara, Goh Matsunobu, Yoshio Inagaki, Koichi Tatsuki, Shin Hotta, Katsuya Shirai
  • Patent number: 8168467
    Abstract: The present invention provides improved solar cells. This patent teaches a particularly efficient method of device manufacture based on incorporating the solar cell fabrication into the widely used, high temperature, Float Glass manufacture process.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: May 1, 2012
    Inventors: James P Campbell, Harry R Campbell, Ann B Campbell, Joel F Farber
  • Patent number: 8159037
    Abstract: Provided are a stack structure including an epitaxial graphene, a method of forming the stack structure, and an electronic device including the stack structure. The stack structure includes: a Si substrate; an under layer formed on the Si substrate; and at least one epitaxial graphene layer formed on the under layer.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-sung Woo, Sun-ae Seo, Dong-chul Kim, Hyun-jong Chung, Dae-young Jeon
  • Patent number: 8158451
    Abstract: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 17, 2012
    Assignee: IMEC
    Inventors: Ngoc Duy Nguyen, Roger Loo, Matty Caymax
  • Patent number: 8124503
    Abstract: A new and useful nanotube growth substrate conditioning processes is herein disclosed that allows the growth of vertical arrays of carbon nanotubes where the average diameter of the nanotubes can be selected and/or controlled as compared to the prior art.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: February 28, 2012
    Assignee: William Marsh Rice University
    Inventors: Robert H. Hauge, Ya-Qiong Xu, Hongwei Shan, Nolan Walker Nicholas, Myung Jong Kim, Howard K. Schmidt, W. Carter Kittrell
  • Patent number: 8101446
    Abstract: There is provided a method for the production of diode laser bars from a wafer, wherein a metal layer is applied to the wafer in such a way that it does not extend up to the later facets of the diode laser bars to be separated, the diode laser bars are separated and stacked one atop another, the metal layer producing a gap between the facets of the stacked diode laser bars and the metal layer being selected in such a way that clogging of the gap during coating of a facet is prevented.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: January 24, 2012
    Assignee: JENOPTIK Diode Lab GmbH
    Inventors: Juergen Sebastian, Ralf Huelsewede
  • Patent number: 7989271
    Abstract: A method for fabricating an LCD device is disclosed, in which a reliable thin film pattern is formed as process deviation is minimized. The method includes forming a thin film on a substrate; forming an etch resist solution on the thin film; applying a soft mold having a concave portion and a convex portion to the etch resist solution, wherein the convex portion includes a first width and a second width different than the first width; forming an etch resist pattern having a predetermined linewidth controlled by the pressure applied by the soft mold; hardening the etch resist pattern; separating the soft mold from the substrate; and patterning the thin film using the etch resist pattern as a mask.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: August 2, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Yeon Heui Nam, Jin Wuk Kim
  • Patent number: 7989242
    Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: August 2, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Byung-Geol Kim, Gee-Sung Chae, Jae-Seok Heo, Woong-Gi Jun
  • Patent number: 7960259
    Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 14, 2011
    Assignee: International Technology Center
    Inventors: Brian D. Schultz, Gary Elder McGuire
  • Patent number: 7955960
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
  • Patent number: 7931844
    Abstract: An imprint lithography apparatus is disclosed which has a needle, and a substrate table arranged to hold a substrate to be imprinted, wherein the needle is moveable between a first position and a second position, the first position being such that in use the needle penetrates a layer of imprintable material on the substrate, and the second position being such that in use the needle is disengaged from the imprintable material on the substrate, the substrate table and the needle arranged such that one may be scanned relative to the other.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: April 26, 2011
    Assignee: ASML Netherlands B.V.
    Inventor: Joeri Lof
  • Patent number: 7927977
    Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: April 19, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Raghuveer S. Makala, Vance Dunton, Yoichiro Tanaka, Steven Maxwell, Tong Zhang, Steven J. Radigan
  • Patent number: 7863075
    Abstract: A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d).
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 4, 2011
    Assignee: TG Solar Corporation
    Inventors: Taek Yong Jang, Byung Il Lee
  • Patent number: 7838377
    Abstract: A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: November 23, 2010
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20100167446
    Abstract: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.
    Type: Application
    Filed: December 28, 2009
    Publication date: July 1, 2010
    Applicant: IMEC
    Inventors: Ngoc Duy Nguyen, Roger Loo, Matty Caymax
  • Patent number: 7723244
    Abstract: A method for internal electrical insulation of a substrate for a power semiconductor module having a framelike insulating housing with a cap and having an insulating substrate. The substrate has conductor tracks and power semiconductor components mounted thereon. The power semiconductor components are connected to connection elements, e.g., further conductor tracks or power semiconductor components, by means of bond connections. The method is characterized by the following steps: a) forming the substrate; b) coating the substrate with a viscous dielectric insulation compound in a casting process or immersion process; c) initiating the cross-linking of the insulation compound; d) with the substrate in a suspended position, permitting excess insulation compound to drip off, and securely enveloping the bond connections with insulation compound; and e) placing the substrate in the housing.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: May 25, 2010
    Assignee: SEMIKRON Elektronik GmbH & Co. KG
    Inventors: Karlheinz Augustin, Christian Göbl
  • Patent number: 7718528
    Abstract: A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Robert P. Meagley, Heidi B. Cao, Kevin P. O'Brien
  • Patent number: 7709383
    Abstract: A film forming method comprising forming a liquid coating film on a substrate by supplying a liquid containing a coating type thin film forming substance and a solvent onto the substrate, substantially converging a variation in film thickness of the coating film, making the coating film stand by in an atmosphere including moisture under a predetermined condition after the substantial-convergence, the predetermined condition being such that a product of a time for which the coating film is exposed to the atmosphere and a water content per unit volume in an atmosphere in the vicinity of a surface of the coating film is made to be greater than or equal to a predetermined value, and forming a solid thin film on the substrate after the stand-by, the thin film being formed by carrying out an elimination of the solvent in the coating film and heat treatment for generating an irreversible reaction to the coating type thin film forming substance in the coating film.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 4, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Tomoyuki Takeishi, Shinichi Ito
  • Publication number: 20100096727
    Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the semiconductor substrate self-separates from the starting substrate without further process steps.
    Type: Application
    Filed: August 24, 2006
    Publication date: April 22, 2010
    Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle