Enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication
According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.
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In the present application, “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN) and the like. Analogously, “III-nitride semiconductor” refers to a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like.
1. FIELD OF THE INVENTIONThe present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of group III-V high electron mobility transistor (HEMT) fabrication.
2. BACKGROUND ARTHigh electron mobility transistors (HEMTs) utilizing group III-V heterojunction structures, such as III-nitride heterojunctions, typically operate using piezoelectric polarization fields to generate a two dimensional electron gas (2DEG) that allows for high current densities with low resistive losses. The 2DEG can arise naturally at an interface of the III-nitride materials forming the heterojunction and, due to the 2DEG, conventional III-nitride HEMTs typically conduct without the application of a gate potential. That is to say, conventional III-nitride and other group III-V HEMTs tend to be normally ON, or depletion mode devices.
Although due to their high breakdown voltage, high current density, and low ON resistance, III-nitride HEMTs are advantageous when used in power applications, the normally ON nature of conventional III-nitride HEMT structures can introduce problems when such depletion mode transistors are used as power devices. For example, in power applications it is desirable to avoid conducting current through the III-nitride HEMTs before control circuitry is fully powered and operational. Accordingly, it would be desirable to provide III-nitride HEMTs that are normally OFF, or enhancement mode transistors to, for example, avoid current conduction problems during start-up and other circuit transitions.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing a solution enabling fabrication of an enhancement mode group III-V HEMT, i.e. a normally OFF group III-V HEMT, suitable for use in power applications.
SUMMARY OF THE INVENTIONThe present invention is directed to an enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
The present invention is directed to an enhancement mode group high electron mobility transistor (HEMT) and method for fabrication. Although the invention is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art.
The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be borne in mind that, unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals.
As previously explained, although III-nitride HEMTs, such as the GaN HEMT comprised of conventional structure 100 in
Referring to
Referring now to
Proceeding on to
Beginning with step 210 in
Continuing on to step 220 in
GaN body 312 may be formed over substrate 302 using any of a number of conventional growth techniques. For example, GaN body 312 may be formed over transition structure 304 using molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxy (HVPE), to name a few suitable approaches.
Referring to step 230 of
It is noted that, as is true for all of
Continuing now to step 240 in
Moving on to step 250 of flowchart 200 and structure 350 in
P type III-nitride gate layer 352 may be selectively formed in opening 344 using an MOCVD process, for example. As shown in
Although the present method characterizes P type III-nitride gate layer 352 as being formed by selective growth of a P type semiconductor material in opening 344 of hard mask 342, other approaches to forming P type III-nitride gate layer 352 are contemplated by the present inventor. For example, in an alternative embodiment, steps 210-230 may be followed by formation of a P type III-nitride material layer, for example as a blanket layer over AlGaN barrier layer 314. Such a layer of P type III-nitride material could then be suitably masked to protect a region of the P type III-nitride material layer corresponding to P type III-nitride gate layer 352, and the unprotected portions of the P type III-nitride material layer could be removed, leaving P type III-nitride gate layer 352.
Proceeding to step 260 of flowchart 200 and referring to
Continuing now to
Gate structure 462, including P type III-nitride gate layer 452, conductive gate electrode 464, and gate dielectric 466, corresponds to gate structure 362 including P type III-nitride gate layer 352, conductive gate electrode 364, and gate dielectric 366, in
As illustrated in
Thus, the concepts disclosed in the present application advantageously enable fabrication of an enhancement mode group III-V HEMT suitable for use in power applications. From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
Claims
1. An enhancement mode high electron mobility transistor (HEMT) comprising:
- a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body;
- a gate structure formed over said group III-V barrier layer, said gate structure including a P type group III-V gate layer formed on said group III-V barrier layer, and one of a conductive gate electrode and a gate dielectric formed directly on said P type group III-V gate layer, wherein said P type group III-V gate layer prevents a two dimensional electron gas (2DEG) from being formed in said heterojunction under said gate structure.
2. The enhancement mode HEMT of claim 1, wherein said heterojunction comprises a III-nitride heterojunction.
3. The enhancement mode HEMT of claim 1, wherein said P type group III-V gate layer comprises a P type III-nitride material.
4. The enhancement mode HEMT of claim 1, wherein said conductive gate electrode is formed on said P type group III-V gate layer.
5. The enhancement mode HEMT of claim 1, wherein said conductive gate electrode is selected from the group consisting of titanium (Ti), aluminum (Al), and doped polysilicon.
6. The enhancement mode HEMT of claim 1, wherein said gate dielectric is formed on said P type group III-V gate layer.
7. The enhancement mode HEMT of claim 1, wherein said gate dielectric is selected from the group consisting of aluminum oxide (Al2O3), silicon nitride (Si3N4), and silicon dioxide (SiO2).
8. The enhancement mode HEMT of claim 1, wherein said group III-V semiconductor body comprises gallium nitride (GaN).
9. The enhancement mode HEMT of claim 1, wherein said group III-V barrier layer comprises aluminum gallium nitride (AlGaN).
10. The enhancement mode HEMT of claim 1, wherein said group III-V semiconductor body is formed over a substrate, and further comprising a transition structure for reducing a lattice mismatch between said substrate and said group III-V semiconductor body.
11. The enhancement mode HEMT of claim 1, wherein said group III-V semiconductor body is formed over a substrate selected from the group consisting of silicon (Si), silicon carbide (SiC), and sapphire.
12. A method for fabricating an enhancement mode high electron mobility transistor (HEMT), said method comprising:
- forming a group III-V semiconductor body over a substrate;
- forming a group III-V barrier layer over said group III-V semiconductor body;
- forming a gate structure over said group III-V barrier layer to prevent a two dimensional electron gas (2DEG) from being formed under said gate structure;
- said gate structure including a P type group III-V gate layer formed on said group III-V barrier layer, and one of a conductive gate electrode and a gate dielectric formed directly on said P type group III-V gate layer.
13. The method of claim 12, wherein forming said gate structure further comprises:
- forming a mask over said group III-V barrier layer;
- creating an opening in said mask to expose a portion of said group III-V barrier layer;
- forming said P type group III-V gate layer in said opening.
14. The method of claim 12, wherein forming said gate structure further comprises:
- forming a hard mask over said group III-V barrier layer;
- creating an opening in said hard mask to expose a portion of said group III-V barrier layer;
- forming said P type group III-V gate layer in said opening.
15. The method of claim 12, wherein said P type group III-V gate layer is formed using a metalorganic chemical vapor deposition (MOCVD) process.
16. The method of claim 12, wherein said P type group III-V gate layer comprises a P type III-nitride material.
17. The method of claim 12, further comprising forming a transition structure over said substrate before forming said group III-V semiconductor body, said transition structure reducing a lattice mismatch between said substrate and said group III-V semiconductor body.
18. The method of claim 12, wherein forming said gate structure comprises forming said gate dielectric on said P type group III-V gate layer, and further comprises forming said conductive gate electrode over said gate dielectric.
19. The method of claim 12, wherein said enhancement mode HEMT comprises a III-nitride HEMT.
20. The method of claim 12, wherein forming said group III-V barrier layer over said group III-V semiconductor body comprises forming an aluminum gallium nitride (AlGaN) barrier layer over a gallium nitride (GaN) semiconductor body.
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Type: Grant
Filed: Jun 10, 2011
Date of Patent: Dec 10, 2013
Patent Publication Number: 20120313106
Assignee: International Rectifier Corporation (El Segundo, CA)
Inventor: Zhi He (El Segundo, CA)
Primary Examiner: Phuc Dang
Application Number: 13/157,562
International Classification: H01L 31/0256 (20060101);