Abstract: A method of fabricating a compound semiconductor device having an ohmic electrode of a low contact potential includes a first cleaning step of heating a compound semiconductor substrate containing a first conductivity type impurity in a temperature range of not more than 250° C. and etching its surface with hydrogen chloride at the temperature of not more than 250° C., and a second cleaning step of performing a radical hydrotreatment on the compound semiconductor substrate at a temperature not more than 250° C., after the first cleaning step. The first cleaning step removes an oxide film but leaves chlorine on the surface of the substrate. The second cleaning step removes the chlorine. The temperature of not more than 250° C. avoids damaging other layers such as an active layer on the opposite surface of the substrate.

Abstract: A method of forming a single crystalline silicon pattern using a structural selective epitaxial growth technique and a selective silicon etching technique, wherein an insulating layer pattern is formed on a semiconductor substrate; polycrystalline silicon is grown on the insulating layer pattern and simultaneously, single crystalline silicon is grown on the semiconductor substrate between the insulating layer patterns. Then, the polycrystalline silicon is removed from the insulating layer pattern. Preferably, the growing of the silicon is performed at a temperature of between about 700 to about 750° C. and a pressure of between about 5 to about 200 Torr. Removing the polycrystalline silicon is performed at a temperature of between about 700 to about 800° C. employing an etch recipe in which polycrystalline silicon has a faster etching rate than single crystalline silicon.

Abstract: Islands of compound semiconductor material can be formed in silicon wafers by etching wells into the silicon wafer, growing an accommodating layer on the silicon wafer, and then growing a compound semiconductor layer on the accommodating layer. The accommodating layer may be a layer of monocrystalline oxide and an amorphous interface layer of silicon oxide separating the monocrystalline oxide from the silicon wafer. The layer or layers that make up the accommodating layer can be annealed to form a single amorphous layer. A template layer may be grown between the accommodating layer and the monocrystalline compound semiconductor layer. The various layers follow the contours of the wells in the silicon wafer. A polishing step removes the various layers except in the wells, leaving a flat silicon surface having islands of monocrystalline compound semiconductor material separated from the silicon by the accommodating layer, and by the template layer if present.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow columns of metal silicide embedded in a matrix of single crystal, epitaxially grown silicon. Higher substrate temperatures and lower deposition rates yield larger columns that are farther apart while more silicon produces smaller columns. Column shapes and locations are selected by seeding the substrate with metal silicide starting regions. A variety of 3-dimensional, exemplary electronic devices are disclosed.

Abstract: A method of exposing a substrate to a pattern of a reticle by synchronously scanning the reticle and the substrate in a direction relative to a slit-shaped illumination area which is formed on the reticle. The method includes steps of providing a reticle on which first and second patterns are formed along the direction, with a space therebetween, exposing a substrate to the first and second patterns of the reticle under different exposure conditions in one scanning process and changing over the exposure conditions when the illumination area exists in the space on the reticle during the one scanning process.

Abstract: A method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front, includes the following process steps:

Abstract: A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.

Abstract: Process and apparatus for automated production of optical devices comprising two plane parallel optical surfaces of a desired optical performance for transmitted light, by measuring and quantifying the spectral response of intensity versus wavelength across the working surface area of a starter optical device as compared to an acceptable computer model, as a three dimensional contour map of optical thickness based on the assumption of a constant index of refraction, then reducing the high spots by automated means such as polishing, and measuring the spectral response again.

Abstract: A method of vapor phase epitaxy deposition of silicon on a silicon substrate on or in which exist areas containing dopants at high concentration, among which is boron, while avoiding a selfdoping of the epitaxial layer by boron, including the step of introducing a chlorinated gas, before the epitaxial deposition step, to etch the substrate across a thickness smaller than 100 nm.

Abstract: An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer.

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions.

Abstract: A method of fabricating quantum wire structures and devices, and quantum dot structures and devices comprise steps of: depositing an insulating layer on a semiconductor substrate, forming a line patterns and a square patterns in an insulating layer, forming a V-grooved patterned structures and a reverse quadrilateral pyramid patterned structures by thermal etching to evaporate portions of the quantum well layer that are not protected by line-shaped mask regions and square-shaped mask regions of the masking layer, forming a quantum wires and a quantum dots by alternatively growing a barrier layer and an active layer on a V-grooved patterned substrate and a reverse quadrilateral pyramid patterned substrate.

Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.

Abstract: Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 .mu.ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, T.sub.t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T.sub.t.

Abstract: In order to facilitate resuming molecular beam epitaxy after etching a substrate or an epitaxial layer, the etching method is implemented in an ultra-high vacuum, and it consists in producing at least two simultaneous chemical beams converging towards the substrate or the layer, the beams being formed of substances, each of which is capable of reacting with elements of different types in the substrate or the layer so as to form volatile compounds. Application in particular to manufacturing photonic and optoelectronic components.

Abstract: A method of a manufacturing a semiconductor device whereby a layer of insulating material and a layer of polycrystalline silicon are provided on a surface of a monocrystalline wafer. A window is then provided in the layer of polycrystalline silicon and a protective layer is formed on the wall of this window. Then the layer of insulating material is removed within the window and below an edge of the layer of polycrystalline silicon adjoining the window. Subsequently, silicon is selectively grown on the mono- and polycrystalline silicon exposed in and adjacent the window from a vapor comprising chlorine as well as silicon at low pressure. The silicon wafer is cleaned before the selective deposition through heating in an atmosphere comprising hydrogen at a pressure of at least 1 atmosphere. This cleaning safeguards that the deposited monocrystalline silicon will always be connected to the layer of polycrystalline silicon by the deposited polycrystalline silicon.

Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .

Abstract: A method of removing an oxide mask during fabrication of semiconductor devices which includes providing a providing a III-V compound semiconductor substrate having a surface, the surface having a growth area and a masked area masked by an oxide film formed on the surface thereof. The oxide film is removed with a Trisdimethylamino group V compound.

Abstract: A p-i-n structure for use in photoconductors and diodes is disclosed, being formed of an Al.sub.x Ga.sub.1-x N alloy (X=0.fwdarw.1) with In.sub.y Ga.sub.1-Y N (Y=0.fwdarw.1) which as grown by MOCVD procedure with the p-type layer adjacent the substrate. In the method of the subject invention, buffer layers of p-type material are grown on a substrate and then doped. The active, confinement and cap layers of n-type material are next grown and doped. The structure is masked and etched as required to expose a surface which is ion implanted and annealed. A p-type surface contact is formed on this ion-implanted surface which is of sufficiently low resistance as to provide good quality performance for use in a device.

Abstract: A semiconductor device having: an underlie having a semiconductor surface capable of growing thereon single crystal; and a first semiconductor layer, the first semiconductor layer including: a first region of group III-V compound semiconductor epitaxially grown on generally the whole area of the semiconductor surface; and second regions of group III-V compound semiconductor disposed and scattered in the first region, the second region having a different composition ratio of constituent elements from the first region, wherein lattice constants of the first and second regions in no strain state differ from a lattice constant of the semiconductor surface, and a difference between the lattice constant of the second region in no strain state and the lattice constant of the semiconductor surface is greater than a difference between the lattice constant of the first region in no strain state and the lattice constant of the semiconductor surface.

Abstract: On a surface of a p-type GaAs (111)B substrate 11, a mesa groove is formed along a [211]A direction. TDMAAs as a group V material and TMGa as a group III material are supplied at 8.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow n-type GaAs 13 dominantly on a side surface of a mesa 12. Subsequently, the group V material is changed to metal As. As.sub.4 and MAGa are supplied at 5.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow p-type GaAs 14 only on a side surface of the GaAs 13. Then, the group V material is again changed to TDMAAs. TDMAAs and TMGa are supplied both at 8.times.10.sup.-4 Pa to grow p-type GaAs 15.