Fluid Growth From Gaseous State Combined With Preceding Diverse Operation Patents (Class 438/503)
  • Patent number: 11421320
    Abstract: A chemical delivery system includes a bulk container, a run/refill chamber, a first conduit and a second conduit. The bulk container stores a precursor. The run/refill chamber includes a plurality of spaced tubes having a plurality of surfaces for receiving the precursor in vapor form and storing the precursor in solid form. The first conduit connects the bulk container to the run/refill chamber for transporting the precursor from the bulk container to the run/refill chamber in vapor form. The second conduit connects the run/refill chamber to a deposition chamber for transporting the precursor from the run/refill chamber to the deposition chamber in vapor form.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 23, 2022
    Assignee: ENTEGRIS, INC.
    Inventors: David James Eldridge, David Peters, Robert Wright, Jr., Bryan C. Hendrix, Scott L. Battle, John Gregg
  • Patent number: 11417518
    Abstract: There is included (a) forming a protective film on a surface of a third base by supplying a processing gas to a substrate in which a first base containing no oxygen, a second base containing oxygen, and the third base containing no oxygen and no nitrogen are exposed on a surface of the substrate; (b) modifying a surface of the second base to be fluorine-terminated by supplying a fluorine-containing gas to the substrate after the protective film is formed on the surface of the third base; and (c) selectively forming a film on a surface of the first base by supplying a film-forming gas to the substrate after the surface of the second base is modified.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 16, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takayuki Waseda, Takashi Nakagawa, Kimihiko Nakatani, Motomu Degai, Yoshitomo Hashimoto
  • Patent number: 11295950
    Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 5, 2022
    Assignee: Soitec
    Inventors: David Sotta, Jean-Marc Bethoux, Oleg Kononchuk
  • Patent number: 11261539
    Abstract: In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 1, 2022
    Assignee: TOYO TANSO CO., LTD.
    Inventors: Satoshi Torimi, Yusuke Sudo, Masato Shinohara, Youji Teramoto, Takuya Sakaguchi, Satoru Nogami, Makoto Kitabatake
  • Patent number: 11152248
    Abstract: Embodiments disclosed herein relate to cluster tools for forming and filling trenches in a substrate with a flowable dielectric material. In one or more embodiments, a cluster tool for processing a substrate contains a load lock chamber, a first vacuum transfer chamber coupled to the load lock chamber, a second vacuum transfer chamber, a cooling station disposed between the first vacuum transfer chamber and the second vacuum transfer chamber, a factory interface coupled to the load lock chamber, a plurality of first processing chambers coupled to the first vacuum transfer chamber, wherein each of the first processing chambers is a deposition chamber capable of performing a flowable layer deposition, and a plurality of second processing chambers coupled to the second vacuum transfer chamber, wherein each of the second processing chambers is a plasma chamber capable of performing a plasma curing process.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: October 19, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Yong Sun, Jinrui Guo, Praket P. Jha, Jung Chan Lee, Tza-Jing Gung, Mukund Srinivasan
  • Patent number: 10797148
    Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark Van Dal, Matthias Passlack, Martin Christopher Holland
  • Patent number: 10658468
    Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
  • Patent number: 10483097
    Abstract: A method for in-situ dry cleaning of a SiGe semiconductor surface, ex-situ degreases the Ge containing semiconductor surface and removes organic contaminants. The surface is then dosed with HF (aq) or NH4F (g) generated via NH3+NH or NF3 with H2 or H2O to remove oxygen containing contaminants. In-situ dosing of the SiGe surface with atomic H removes carbon containing contaminants.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 19, 2019
    Assignee: The Regents of the University of California
    Inventors: Tobin Kaufman-Osborn, Andrew C. Kummel, Kiarash Kiantaj
  • Patent number: 9818599
    Abstract: A method for in-situ dry cleaning of a SiGe semiconductor surface doses the SiGe surface with ex-situ wet HF in a clean ambient environment or in-situ dosing with gaseous NH4F to remove oxygen containing contaminants. Dosing the SiGe surface with atomic H removes carbon containing contaminants. Low temperature annealing pulls the surface flat. Passivating the SiGe semiconductor surface with H2O2 vapor for a sufficient time and concentration forms an a oxygen monolayer(s) of —OH sites on the SiGe. Second annealing the SiGe semiconductor surface is conducted at a temperature below that which would induce dopant diffusion. A method for in-situ dry cleaning of a SiGe semiconductor surface, ex-situ degreases the Ge containing semiconductor surface and removes organic contaminants. The surface is then dosed with HF(aq) or NH4F(g) generated via NH3+NH or NF3 with H2 or H2O to remove oxygen containing contaminants. In-situ dosing of the SiGe surface with atomic H removes carbon containing contaminants.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: November 14, 2017
    Assignee: The Regents of the University of California
    Inventors: Tobin Kaufman-Osborn, Andrew C. Kummel, Kiarash Kiantaj
  • Patent number: 9704708
    Abstract: A method for forming a film on a substrate is provided. The method includes positioning a substrate within a processing volume of a process chamber and heating the substrate. The method further includes forming a semiconductor film on the substrate by exposing the substrate to two or more reactants including a silicon source and a halogenated dopant source. The semiconductor film includes one or more epitaxial regions and one or more non-epitaxial regions.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 11, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Yihwan Kim, Xuebin Li
  • Patent number: 9679767
    Abstract: Provided is a method of manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a SiC substrate using a SiC-CVD furnace which is installed in a glove box. The method includes a SiC substrate placement step of placing the SiC substrate in the SiC-CVD furnace while circulating gas in the glove box.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 13, 2017
    Assignee: SHOWA DENKO K.K.
    Inventors: Akira Miyasaka, Yutaka Tajima, Yoshiaki Kageshima, Daisuke Muto, Kenji Momose
  • Patent number: 9640736
    Abstract: Disclosed is a silicon nano crystal light emitting diode, including: a photoelectric conversion layer formed of a silicon nitride layer including a silicon nano crystal; an electron injection layer formed on the photoelectric conversion layer; and a hole injection layer, which faces the electron injection layer with the photoelectric conversion layer interposed therebetween, has an energy band gap higher than that of the photoelectric conversion layer, and has a refractive index lower than that of a silicon thin film.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: May 2, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chul Huh, Bong Kyu Kim, Chang Geun Ahn
  • Patent number: 9515140
    Abstract: A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 9385265
    Abstract: A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: July 5, 2016
    Assignee: LUMILEDS LLC
    Inventors: Jonathan J. Wierer, Jr., John E. Epler
  • Patent number: 9177799
    Abstract: Provided is a substrate processing apparatus, a semiconductor device manufacturing method, and a substrate manufacturing method. The substrate processing apparatus comprises: a reaction chamber configured to process substrates; a first gas supply system configured to supply at least a silicon-containing gas and a chlorine-containing gas or at least a gas containing silicon and chlorine; a first gas supply unit connected to the first gas supply system; a second gas supply system configured to supply at least a reducing gas; a second gas supply unit connected to the second gas supply system; a third gas supply system configured to supply at least a carbon-containing gas and connected to at least one of the first gas supply unit and the second gas supply unit; and a control unit configured to control the first to third gas supply systems.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: November 3, 2015
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yoshinori Imai, Hideji Shibata, Takafumi Sasaki
  • Patent number: 9142621
    Abstract: A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: September 22, 2015
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Chun-Ju Tun, Yi-Chao Lin, Chen-Fu Chiang, Cheng-Huang Kuo
  • Patent number: 9099611
    Abstract: Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: August 4, 2015
    Assignees: LG INNOTEK CO., LTD., TAMURA CORPORATION, KOHA CO., LTD.
    Inventor: Yong Tae Moon
  • Patent number: 9034739
    Abstract: A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a second mask layer over the first mask layer; annealing the second mask layer to form islands; etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars; and growing semiconductor material between the pillars and then over the tops of the pillars.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 19, 2015
    Assignee: Seren Photonics Limited
    Inventor: Tao Wang
  • Patent number: 9023721
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Patent number: 9018082
    Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 28, 2015
    Assignees: International Business Machines Corporation, King Abdulaziz City for Science and Technology
    Inventors: Maha M. Khayyat, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 8986464
    Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Yukimune Watanabe
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8962456
    Abstract: Objects of the present invention are to provide a method for producing a Group III nitride semiconductor single crystal, which method enables production of a Group III nitride semiconductor single crystal having a flat surface by means of a crucible having any inside diameter; to provide a self-standing substrate obtained from the Group III nitride semiconductor single crystal; and to provide a semiconductor device employing the self-standing substrate. The production method includes adding the template, a flux, and semiconductor raw materials to a crucible and growing a Group III nitride semiconductor single crystal while the crucible is rotated. In the growth of the semiconductor single crystal, the crucible having an inside diameter R (mm) is rotated at a maximum rotation speed ? (rpm) satisfying the following conditions: ?1?4????1+4; ?1=10z; and z=?0.78×log10(R)+3.1.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shiro Yamazaki, Miki Moriyama
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20150017789
    Abstract: The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 105 cm?2, combined with a high-purity active layer of Ga1-x-yAlxInyN (0?x?1, 0?y?1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.
    Type: Application
    Filed: August 14, 2014
    Publication date: January 15, 2015
    Applicant: SIXPOINT MATERIALS, INC.
    Inventor: TADAO HASHIMOTO
  • Patent number: 8927398
    Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8921237
    Abstract: A method of depositing a film using an atomic layer deposition (ALD) method while rotating a turntable provided inside a chamber and including a substrate mounting portion, onto which a substrate can be mounted, to cause the substrate to pass through first and second process areas, into which different gases to be mutually reacted are respectively supplied, including coating the turntable with the film under a state where the wafer is not mounted onto the turntable, the turntable is rotated, and the substrate mounting portion has a predetermined temperature; and processing to deposit the film on the wafer under a state where the wafer is mounted onto the turntable, the turntable is rotated, and the substrate has a temperature equal to or less than the predetermined temperature.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 30, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kentaro Oshimo, Masato Koakutsu, Hiroko Sasaki, Hiroaki Ikegawa
  • Patent number: 8912079
    Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: December 16, 2014
    Assignees: The University of Tokyo, V Technology Co., Ltd.
    Inventors: Motoichi Ohtsu, Takashi Yatsui, Tadashi Kawazoe, Shunsuke Yamazaki, Koichi Kajiyama, Michinobu Mizumura, Keiichi Ito
  • Patent number: 8900979
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 2, 2014
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Publication number: 20140342536
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Jie Bai, Anthony J. Lochtefeld, Ji-Soo Park
  • Patent number: 8889533
    Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takafumi Sasaki, Yoshinori Imai, Koei Kuribayashi, Sadao Nakashima
  • Patent number: 8865574
    Abstract: A method for electrodepositing nanoparticles onto a substrate, including heating a nonaqueous polar suspension of a plurality of semiconducting nanoparticles to a temperature between about 30 degrees Celsius and about 100 degrees Celsius, placing a substrate into the suspension, imparting opposite surface charges onto the plurality of semiconducting particles and onto the substrate, establishing an electric field in the suspension, depositing a film of semiconducting particles onto the substrate to define a coated substrate, removing the coated substrate from the suspension into air, and coating the film of semiconducting particles with an electrically conducting metal layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 21, 2014
    Inventor: Michael Haag
  • Patent number: 8846502
    Abstract: Atomic layer deposition (ALD) processes for forming thin films comprising GaN are provided. In some embodiments, ALD processes for forming doped GaN thin films are provided. The thin films may find use, for example, in light-emitting diodes.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: September 30, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi Haukka, Viljami J. Pore, Antti Niskanen
  • Patent number: 8847363
    Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Patent number: 8841206
    Abstract: A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Yun-Mo Chung, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee, Min-Jae Jeong, Yong-Duck Son, Byung-Soo So, Seung-Kyu Park, Dong-Hyun Lee, Kil-Won Lee, Jae-Wan Jung
  • Patent number: 8842710
    Abstract: There are provided a process for producing a semiconductor device and a semiconductor device which allow conductivity distribution to be formed without making refractive index distributed even in a material system of a semiconductor difficult to be subjected to ion implantation. The process for producing a semiconductor device includes the steps of forming a semiconductor layer containing a dopant; forming a concave and convex structure on the semiconductor layer by partially removing the semiconductor layer; and forming a conductivity distribution reflecting the concave and convex structure in the semiconductor layer by performing heat treatment on the semiconductor layer in which the concave and convex structure has been formed at a temperature at which a material forming the semiconductor layer causes mass transport and filling up a hole of a concave portion of the concave and convex structure with the material forming the semiconductor layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: September 23, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nagatomo, Takeshi Kawashima, Katsuyuki Hoshino, Shoichi Kawashima
  • Patent number: 8822314
    Abstract: An epitaxial growth method includes plasma treating a surface of a bulk crystalline Aluminum Nitride (AlN) substrate and subsequently heating the substrate in an ammonia-rich ambient to a temperature of above 1000° C. for at least 5 minutes without epitaxial growth. After heating the surface, a III-nitride layer is epitaxially grown on the surface.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 2, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Mark R. Teepe, Thomas Wunderer, Zhihong Yang, Noble M. Johnson, Clifford Knollenberg
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8815712
    Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8815717
    Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Harada, Koichi Tachibana, Toshiki Hikosaka, Hajime Nago, Shinya Nunoue
  • Patent number: 8809170
    Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 19, 2014
    Assignee: ASM America Inc.
    Inventor: Matthias Bauer
  • Patent number: 8759204
    Abstract: The inventive concept provides methods for manufacturing a semiconductor substrate. The method may include forming a stop pattern surrounding an edge of a substrate, forming a transition layer an entire top surface of the substrate except the stop pattern, and forming an epitaxial semiconductor layer on the transition layer and the stop pattern. The epitaxial semiconductor layer may not be grown from the stop pattern. That is, the epitaxial semiconductor layer may be isotropically grown from a top surface and a sidewall of the transition layer by a selective isotropic growth method, so that the epitaxial semiconductor layer may gradually cover the stop pattern.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: June 24, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Bum Bae, Sung Bock Kim, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 8731344
    Abstract: A method for manufacturing a semiconductor optical modulator includes forming a p-type semiconductor layer on a main surface of a p-type semiconductor substrate; forming a pair of stripe-shaped masks on the p-type semiconductor layer, the stripe-shaped masks extending in a first direction along the main surface of the p-type semiconductor substrate and being spaced apart from each other; simultaneously forming a hole and a pair of stripe structures extending in the first direction by etching the p-type semiconductor layer through the stripe-shaped masks, the pair of stripe structures defining the hole; after removing the stripe-shaped masks, forming a buried layer in the hole; forming a core layer on the buried layer and the stripe structures; and forming an upper cladding layer on the core layer. The buried layer is made of a semiconductor material with a lower optical absorption loss than that of the p-type semiconductor layer.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 20, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Yagi
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Patent number: 8729676
    Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: May 20, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Shiga, Hiroshi Takeno
  • Patent number: 8709923
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20140103362
    Abstract: A composite substrate 10 includes a sapphire body 1A, a seed crystal film 4 composed of gallium nitride crystal and provided on a surface of the sapphire body, and a gallium nitride crystal layer 7 grown on the seed crystal film 4 and having a thickness of 200 ?m or smaller. Voids 5 are provided along an interface between the sapphire body 1A and the seed crystal film 4 in a void ratio of 4.5 to 12.5 percent.
    Type: Application
    Filed: December 24, 2013
    Publication date: April 17, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Makoto Iwai
  • Patent number: 8680581
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 25, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoyuki Nakada, Koji Okuno, Yasuhisa Ushida
  • Patent number: 8679956
    Abstract: A method and apparatus that includes a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume is provided. The showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. The showerhead may include a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: March 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Alexander Tam, Anzhong Chang, Sumedh Acharya
  • Patent number: 8669168
    Abstract: A method of preparing GaN material includes subjecting a GaN substrate to at least two cycles of Ga deposition and desorption, then applying a layer of AlN to the GaN substrate, then growing GaN on the AlN layer by molecular beam epitaxy. This results in reduced concentrations of oxygen, carbon, and silicon impurities.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: March 11, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: David F. Storm, Douglas S. Katzer, Glenn G. Jernigan, Steven C. Binari