Doping Of Semiconductor Patents (Class 438/505)
  • Patent number: 10268967
    Abstract: In this statement, realization of “Non-volatile molecular multiple quantum bit (NVQB)” is described. NVQB is the long-term macroscopic time scale analog of MMQB. To realize NVQB, while inverted population of the gas is kept, entanglement generation and coherent state keeping must be carried out for a long-term quantum computation. Operating principle of molecular quantum computer is entanglement generation among huge-number of molecular ro-vibronic eigenstates by emission and absorption of photons due to the Fermi golden rule. Each single photon generated in induced absorption and induced emission sews many quantum states of many molecules by the Fermi golden rule. This results entanglement. When NVQB is realized, NVQB is not only used as “quantum storage device” up to 2Na, but also NVQB itself makes practical reasonable commercial molecular quantum computer be realized at once. NVQB is an alias of long-term successfully operating molecular quantum computer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 23, 2019
    Inventor: Keisaku Ishii
  • Patent number: 9171718
    Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 27, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang
  • Patent number: 9023720
    Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 5, 2015
    Assignee: Sen Corporation
    Inventors: Genshu Fuse, Michiro Sugitani
  • Publication number: 20150053259
    Abstract: Apparatus and methods to incorporate p-type dopants in II-VI semiconducting layers are disclosed herein. In some embodiments, radical nitrogen is introduced in a physical vapor deposition apparatus operating at moderate pressures (e.g. 10?5 Torr to 100 Torr). The radical nitrogen allows for in-situ doping of II-VI materials, such as ZnTe, to degenerate levels.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 26, 2015
    Applicant: PLANT PV
    Inventors: Brian E. Hardin, James Randy Groves, Stephen T. Connor, Craig H. Peters
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8921237
    Abstract: A method of depositing a film using an atomic layer deposition (ALD) method while rotating a turntable provided inside a chamber and including a substrate mounting portion, onto which a substrate can be mounted, to cause the substrate to pass through first and second process areas, into which different gases to be mutually reacted are respectively supplied, including coating the turntable with the film under a state where the wafer is not mounted onto the turntable, the turntable is rotated, and the substrate mounting portion has a predetermined temperature; and processing to deposit the film on the wafer under a state where the wafer is mounted onto the turntable, the turntable is rotated, and the substrate has a temperature equal to or less than the predetermined temperature.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 30, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kentaro Oshimo, Masato Koakutsu, Hiroko Sasaki, Hiroaki Ikegawa
  • Patent number: 8900980
    Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Shih-Hsieng Huang, Ta-Wei Wang
  • Patent number: 8842710
    Abstract: There are provided a process for producing a semiconductor device and a semiconductor device which allow conductivity distribution to be formed without making refractive index distributed even in a material system of a semiconductor difficult to be subjected to ion implantation. The process for producing a semiconductor device includes the steps of forming a semiconductor layer containing a dopant; forming a concave and convex structure on the semiconductor layer by partially removing the semiconductor layer; and forming a conductivity distribution reflecting the concave and convex structure in the semiconductor layer by performing heat treatment on the semiconductor layer in which the concave and convex structure has been formed at a temperature at which a material forming the semiconductor layer causes mass transport and filling up a hole of a concave portion of the concave and convex structure with the material forming the semiconductor layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: September 23, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nagatomo, Takeshi Kawashima, Katsuyuki Hoshino, Shoichi Kawashima
  • Patent number: 8809986
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 19, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
  • Patent number: 8779399
    Abstract: The present invention provides an electrostatic deflector which deflects a plurality of charged particle beams, the deflector comprising a first electrode member including a plurality of first electrode pairs arranged along a first axis direction in an oblique coordinate system, and a second electrode member including a plurality of second electrode pairs arranged along a second axis direction in the oblique coordinate system, wherein each of the plurality of charged particle beams is deflected by a corresponding first electrode pair of the plurality of first electrode pairs, and a corresponding second electrode pair of the plurality of second electrode pairs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshiro Yamanaka
  • Patent number: 8772140
    Abstract: A unipolar semiconductor component having a drift layer is produced by forming the drift layer with a continuously decreasing concentration of a charge carrier doping along the growth direction of the drift layer by way of epitaxial precipitation of the material of the drift layer, which comprises at least one wide band gap material. By using silicon carbide for the drift layer formed by the epitaxial precipitation, a subsequent change of the continuously decreasing concentration of the charge carrier doping due to a diffusion of the dopant atoms in downstream processes is suppressed. The production method can be used in particular to implement a unipolar semiconductor component comprising a drift layer, which component has an advantageous ratio of a comparatively high reverse bias voltage with relatively low forward losses, in a simple and/or cost-effective manner. The unipolar semiconductor component can be an active or passive semiconductor component.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Elpelt, Peter Friedrichs
  • Patent number: 8704335
    Abstract: A bipolar transistor is fabricated having a collector (52) in a substrate (1) and a base (57, 58) and an emitter (59) formed over the substrate. The base has a stack region (57) which is laterally separated from the emitter (59) by an electrically insulating spacer (71). The insulating spacer (71) has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a ?-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 22, 2014
    Assignee: NXP, B.V.
    Inventors: Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Philippe Meunier-Beillard
  • Patent number: 8664093
    Abstract: Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Daniel T. Pham, William J. Taylor, Jr.
  • Publication number: 20130237042
    Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.
    Type: Application
    Filed: September 4, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Chiharu Ota, Takashi Shinohe
  • Patent number: 8518809
    Abstract: A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: August 27, 2013
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Watanabe, Yasuo Kitou, Yasushi Furukawa, Kensaku Yamamoto, Hidefumi Takaya, Masahiro Sugimoto, Yukihiko Watanabe, Narumasa Soejima, Tsuyoshi Ishikawa
  • Patent number: 8501571
    Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8470697
    Abstract: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: June 25, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Ki Bum Nam, Hwa Mok Kim, James S. Speck
  • Patent number: 8470675
    Abstract: A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Sridhar, Sameer Pendharkar
  • Patent number: 8450191
    Abstract: Methods of forming polysilicon layers are described. The methods include forming a high-density plasma from a silicon precursor in a substrate processing region containing the deposition substrate. The described methods produce polycrystalline films at reduced substrate temperature (e.g. <500° C.) relative to prior art techniques. The availability of a bias plasma power adjustment further enables adjustment of conformality of the formed polysilicon layer. When dopants are included in the high density plasma, they may be incorporated into the polysilicon layer in such a way that they do not require a separate activation step.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: May 28, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Xiaolin Chen, Young S. Lee
  • Patent number: 8445367
    Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Tae Noh, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
  • Publication number: 20130109161
    Abstract: A metal organic chemical vapor deposition apparatus includes reaction chambers in which nitride layers is deposited on a substrate using a group III-V material, a buffer chamber connected to the reaction chambers and in which a transfer robot is disposed to transfer the substrate into the reaction chambers, a gas supply device configured to selectively supply one or more of hydrogen, nitrogen, and ammonia gases into the buffer chamber so that when the buffer chamber communicates with one of the reaction chambers, the buffer chamber has the same atmosphere as an atmosphere of the reaction chamber, and a heater disposed in the buffer chamber. Nitride layers are deposited on a substrate in the reaction chambers, and the temperature and gas atmosphere of the buffer chamber are adjusted such that when the substrate is transferred, epitaxial layers formed on the substrate can be stably maintained.
    Type: Application
    Filed: December 17, 2012
    Publication date: May 2, 2013
    Applicant: LIGADP CO., LTD.
    Inventor: LIGADP CO., LTD.
  • Patent number: 8399340
    Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akihiko Ohi
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Publication number: 20120187419
    Abstract: The invention relates to a production method for a unipolar semiconductor component having a drift layer (16), comprising the following step: forming the drift layer (16) with a continuously decreasing concentration of a charge carrier doping (n) along the growth direction (19) of the drift layer (16) by way of epitaxial precipitation of the material of the drift layer (16), which comprises at least one wide band gap material. By using silicon carbide for the drift layer (16) formed by the epitaxial precipitation, a subsequent change of the continuously decreasing concentration of the charge carrier doping (n) due to a diffusion of the dopant atoms in downstream processes is suppressed. The production method can be used in particular to implement a unipolar semiconductor component comprising a drift layer (16), which component has an advantageous ratio of a comparatively high reverse bias voltage with relatively low forward losses, in a simple and/or cost-effective manner.
    Type: Application
    Filed: July 12, 2010
    Publication date: July 26, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Rudolf Elpelt, Peter Friedrichs
  • Patent number: 8216921
    Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: July 10, 2012
    Assignee: Covalent Materials Corporation
    Inventor: Tatsuo Fujii
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8163635
    Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Sen Corporation
    Inventors: Michiro Sugitani, Genshu Fuse
  • Patent number: 8101528
    Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: January 24, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau
  • Patent number: 8102026
    Abstract: To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value ?? obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×1017 cm?3.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 24, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Eri, Takeshi Meguro
  • Patent number: 8088677
    Abstract: A method of manufacturing a semiconductor device including implanting an element selected from fluorine and nitrogen, over the entire region of a semiconductor substrate; oxidizing the semiconductor substrate to thereby form a first oxide film over the surface of the semiconductor substrate; selectively removing the first oxide film in a partial region; oxidizing the semiconductor substrate in the partial region to thereby form a second oxide film thinner than the first oxide film in the partial region; and forming gates to thereby form transistors.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: January 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Gen Tsutsui
  • Patent number: 8084312
    Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, P R Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider
  • Patent number: 8034648
    Abstract: Optimizing the regrowth over epitaxial layers during manufacture of a distributed feedback laser. In one example embodiment, a method for depositing an InP regrowth layer on an epitaxial base portion of a distributed feedback laser includes growing a first portion of the regrowth layer at an initial substrate temperature of approximately 580 degrees Celsius to a thickness between approximately 300 Angstroms and approximately 900 Angstroms, increasing the substrate temperature from the initial substrate temperature to an increased substrate temperature of approximately 660 degrees Celsius, growing a second portion of the regrowth layer at the increased substrate temperature, doping a first part of an uppermost layer of the regrowth layer at a concentration of approximately 8.00*10^17/cm3 at the increased substrate temperature, and doping a second part of the uppermost layer of the regrowth layer at a concentration between approximately 1.90*10^18/cm3 and approximately 2.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: October 11, 2011
    Assignee: Finisar Corporation
    Inventors: Yuk Lung Ha, David Bruce Young, Ashish Verma, Roman Dimitrov
  • Patent number: 8034669
    Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel
  • Patent number: 7951694
    Abstract: A method of manufacturing a nitride semiconductor structure includes disposing a semiconductor substrate in a molecular beam epitaxy reactor; growing a wetting layer comprising AlxInyGa(1?(x+y))As(0?x+y?1) or AlxInyGa(1?(x+y))P(0?x+y?1) on the substrate; in-situ annealing the wetting layer; growing a first AlGaInN layer on the wetting layer using plasma activated nitrogen as the source of nitrogen with an additional flux of phosphorous or arsenic; and growing a second AlGaInN layer on the first AlGaInN layer using ammonia as a source of nitrogen.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 31, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jonathan Heffernan
  • Patent number: 7947548
    Abstract: A method includes forming elongate structures (5) on a first substrate (3), such that the material composition of each elongate structure (7) varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices (1, 2) are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate (7). The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices (1,2) to be provided on a common substrate. In particular, only one transfer step is necessary.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: May 24, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
  • Patent number: 7939437
    Abstract: A method for the production of a contact structure of a solar cell allows p-contacts and n-contacts to be produced simultaneously.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: May 10, 2011
    Assignee: Deutsche Cell GmbH
    Inventors: Andreas Krause, Bernd Bitnar, Holger Neuhaus
  • Patent number: 7897495
    Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Andrew M. Lam, Yihwan Kim
  • Patent number: 7867551
    Abstract: A method of forming a doped Group IBIIIAVIA absorber layer for solar cells by reacting a partially reacted precursor layer with a dopant structure. The precursor layer including Group IB, Group IIIA and Group VIA materials such as Cu, Ga, In and Se are deposited on a base and partially reacted. After the dopant structure is formed on the partially reacted precursor layer, the dopant structure and partially reacted precursor layer is fully reacted. The dopant structure includes a dopant material such as Na.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 11, 2011
    Assignee: SoloPower, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20100244101
    Abstract: There is provided a method for fabricating a semiconductor device capable of setting carbon concentration within crystal to a desirable value while improving electron mobility. The carbon concentration within a buffer layer is controlled by introducing material gas of hydrocarbon or organic compounds containing carbon such as propane as a dopant in forming the buffer layer by introducing trimethylgallium (TMGa) and ammonium (NH3) as gaseous nitride compound semiconductor materials into a chamber in which a substrate is disposed.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 30, 2010
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Takuya Kokawa, Sato Yoshihiro, Kato Sadahiro, Iwami Masayuki
  • Patent number: 7799626
    Abstract: A lateral DMOS device and a fabrication method therefor that may include forming a second conductive type well in a first conductive type semiconductor substrate and forming a Schottky contact in contact with the second conductive type well in a Schottky diode region, thereby preventing breakdown of the device due to high voltage.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 21, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Sung-Man Pang
  • Patent number: 7772097
    Abstract: An embodiment provides a method for selectively depositing a single crystalline film. The method includes providing a substrate, which includes a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology. A silicon precursor and BCl3 are intermixed to thereby form a feed gas. The feed gas is introduced to the substrate under chemical vapor deposition conditions. A Si-containing layer is selectively deposited onto the first surface without depositing on the second surface by introducing the feed gas.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: August 10, 2010
    Assignee: ASM America, Inc.
    Inventors: Pierre Tomasini, Nyles Cody
  • Patent number: 7713753
    Abstract: A method of fabricating a device includes: providing a substrate having a patterned surface, depositing a first-level self-assembled material on at least a portion of the patterned surface, wherein the position and/or orientation of the first-level self-assembled material is directed by the patterned surface, to form a first nanostructure pattern, and depositing a second-level self-assembled material on at least a portion of the first nanostructure pattern to form an array of nanostructures of the second-level self-assembled material. An apparatus fabricated using the method is also provided.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: May 11, 2010
    Assignee: Seagate Technology LLC
    Inventors: Shuaigang Xiao, Xiaomin Yang
  • Patent number: 7700467
    Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: April 20, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Scott Gregory Bushman, Periannan Chidambaram
  • Patent number: 7682953
    Abstract: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 23, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Ki Bum Nam, Hwa Mok Kim, James S. Speck
  • Patent number: 7648895
    Abstract: A vertical CVD apparatus is arranged to process a plurality of target substrates all together to form a silicon germanium film. The apparatus includes a reaction container having a process field configured to accommodate the target substrates, and a common supply system configured to supply a mixture gas into the process field. The mixture gas includes a first process gas of a silane family and a second process gas of a germane family. The common supply system includes a plurality of supply ports disposed at different heights.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: January 19, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Masaki Kurokawa, Katsuhiko Komori, Norifumi Kimura, Kazuhide Hasebe, Takehiko Fujita, Akitake Tamura, Yoshikazu Furusawa
  • Publication number: 20100009525
    Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 14, 2010
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Patent number: 7642178
    Abstract: A method for manufacturing a semiconductor device includes steps of: forming a first epitaxial film on a silicon substrate; forming a trench in the first epitaxial film; and forming a second epitaxial film on the first epitaxial film and in the trench. The step of forming the second epitaxial film includes a final step, in which a mixed gas of a silicon source gas and a halide gas is used. The silicon substrate has an arsenic concentration defined as ?. The second epitaxial film has an impurity concentration defined as ?. The arsenic concentration and the impurity concentration has a relationship of: ??3×1019×ln(?)?1×1021.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: January 5, 2010
    Assignees: DENSO CORPORATION, Sumco Corporation
    Inventors: Shoichi Yamauchi, Takumi Shibata, Tomonori Yamaoka, Syouji Nogami
  • Publication number: 20090291519
    Abstract: Disclosed herein is a light emitting device. The light emitting device includes an n-type nitride semiconductor layer; an active layer on the n-type semiconductor layer, an AlN/GaN layer of a super lattice structure formed by alternately growing an AlN layer and a GaN layer on the active layer, and a p-type nitride semiconductor layer on the AlN/GaN layer of the super lattice structure. At least one of the AlN layer and the GaN layer is doped with a p-type dopant. A method for manufacturing the light emitting device is also provided.
    Type: Application
    Filed: August 4, 2009
    Publication date: November 26, 2009
    Applicant: SEOUL OPTO DEVICE CO., LTD.
    Inventors: Gyu Beom KIM, Sang Joon Lee, Chang Suk Han, Kwang Choong Kim
  • Publication number: 20090261327
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 22, 2009
    Applicant: Infineon Technologies AG
    Inventors: Herbert Schaefer, Martin Franosch, Thomas Meister, Josef Boeck
  • Patent number: RE43045
    Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: December 27, 2011
    Assignee: Cree, Inc.
    Inventor: David Todd Emerson