Ion Implantation Patents (Class 438/506)
  • Patent number: 9059398
    Abstract: Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: June 16, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jisoo Kim, Mang-Mang Ling, Khoi Doan, Chi Hong Ching, Srinivas D. Nemani
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Patent number: 9023722
    Abstract: A workpiece is implanted to affect growth of a compound semiconductor, such as GaN. Implanted regions of a workpiece increase, reduce, or prevent growth of this compound semiconductor. Combinations of implants may be performed to cause increased growth in certain regions of the workpiece, such as between regions where growth is reduced. Growth also may be reduced or prevented at the periphery of the workpiece.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 5, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Simon Ruffell
  • Patent number: 9018024
    Abstract: An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Jason E. Cummings, Toshiharu Furukawa, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 8993418
    Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 31, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Vincent Destefanis, Nicolas Loubet
  • Patent number: 8969181
    Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 3, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Morgan D. Evans, Christopher R. Hatem
  • Patent number: 8925479
    Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keung Hui, Chun-Lin Chang, Jong-I Mou
  • Patent number: 8912612
    Abstract: A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8906759
    Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8900980
    Abstract: MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Shih-Hsieng Huang, Ta-Wei Wang
  • Patent number: 8846508
    Abstract: Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald England, Andrew M. Waite, Simon Ruffell
  • Patent number: 8835287
    Abstract: A workpiece is implanted to improve growth of a compound semiconductor, such as GaN. This workpiece may be implanted such that the workpiece has a dose at a center different from a dose at a periphery. This workpiece also may be implanted one or more times to form a pattern of lines, which may be a grid, a series of circles, or other shapes. The distance between certain pairs of lines may be different across the workpiece.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Morgan D. Evans
  • Patent number: 8779399
    Abstract: The present invention provides an electrostatic deflector which deflects a plurality of charged particle beams, the deflector comprising a first electrode member including a plurality of first electrode pairs arranged along a first axis direction in an oblique coordinate system, and a second electrode member including a plurality of second electrode pairs arranged along a second axis direction in the oblique coordinate system, wherein each of the plurality of charged particle beams is deflected by a corresponding first electrode pair of the plurality of first electrode pairs, and a corresponding second electrode pair of the plurality of second electrode pairs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshiro Yamanaka
  • Patent number: 8772130
    Abstract: In order to keep the crystallinity of the semiconductor thin film layer high, a temperature of a semiconductor substrate during hydrogen ion addition treatment is suppressed to lower than or equal to 200° C. In addition, the semiconductor substrate is subjected to plasma treatment while the semiconductor substrate is kept at a temperature of higher than or equal to 100° C. and lower than or equal to 400° C. after the hydrogen ion addition treatment, whereby Si—H bonds which have low contribution to separation of the semiconductor thin film layer can be reduced while Si—H bonds which have high contribution to separation of the semiconductor thin film layer, which are generated by the hydrogen ion addition treatment, are kept.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroshi Ohki
  • Publication number: 20140134780
    Abstract: Provided is an epitaxial silicon wafer with reduced metal contamination achieved by higher gettering capability and a method of efficiently producing the same. The method of producing an epitaxial wafer includes a wafer production step of pulling a single crystal silicon ingot having a COP formation region by Czochralski process, and subjecting the obtained single crystal silicon ingot to slicing, thereby producing a silicon wafer 10 including COPs; a cluster ion irradiation step of irradiating the produced silicon wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16, contained as a solid solution in a surface portion 10A of the silicon wafer 10; and an epitaxial layer formation step of forming an epitaxial layer 20 on the modifying layer 18 of the silicon wafer 10.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 15, 2014
    Applicant: SUMCO CORPORATION
    Inventor: Takeshi Kadono
  • Publication number: 20140134779
    Abstract: Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. A method of producing an epitaxial silicon wafer includes a first step of irradiating a silicon wafer free of dislocation clusters and COPs with cluster ions to form a modifying layer formed from a constituent element of the cluster ions in a surface portion of the silicon wafer; and a second step of forming an epitaxial layer on the modifying layer of the silicon wafer.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 15, 2014
    Applicant: SUMCO CORPORATION
    Inventor: Takeshi Kadono
  • Patent number: 8697554
    Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: April 15, 2014
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: William E. Tennant, Gerard J. Sullivan, Mark Field
  • Patent number: 8691673
    Abstract: A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hak-Lay Chuang, Ming Zhu, Lee-Wee Teo, Bao-Ru Young
  • Publication number: 20140080247
    Abstract: The present invention provides a method of more efficiently producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. A method of producing a semiconductor epitaxial wafer 100 according to the present invention includes a first step of irradiating a semiconductor wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16 in a surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.
    Type: Application
    Filed: March 19, 2012
    Publication date: March 20, 2014
    Applicant: SUMCO CORPORATION
    Inventors: Takeshi Kadono, Kazunari Kurita
  • Patent number: 8673753
    Abstract: In a multi-energy ion implantation process, an ion implanting system having an ion source, an extraction assembly, and an electrode assembly is used to implant ions into a target. An ion beam having a first energy may be generated using the ion source and the extraction assembly. A first voltage may be applied across the electrode assembly. The ion beam may enter the electrode assembly at the first energy, exit the electrode assembly at a second energy, and implant ions into the target at the second energy. A second voltage may be applied across the electrode assembly. The ion beam may enter the electrode assembly at the first energy, exit the electrode assembly at a third energy, and implants ions into the target at the third energy. The third energy may be different from the second energy.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 18, 2014
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventor: Zhimin Wan
  • Publication number: 20140057421
    Abstract: A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 27, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: JUNJI OH, MASANORI TERAHARA
  • Patent number: 8598017
    Abstract: The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. There is provided a fiber SOI substrate 5 comprising a fiber 1 with a polygonal cross section, and a semiconductor thin film 3 crystallized after film formation on at least one surface of the fiber 1, and a plurality of grooves 8 that extend in a linear direction of the fiber 1 and are arranged at intervals in a width direction are formed on a surface of the fiber 1.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 3, 2013
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Takashi Fuyuki, Kenkichi Suzuki, Sadayuki Toda, Hisashi Koaizawa
  • Patent number: 8518808
    Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 27, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Boris N. Feigelson, Travis Anderson, Francis J. Kub
  • Patent number: 8501570
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Jeff J. Xu, Ming-Jie Huang, Yimin Huang, Zhiqiang Wu, Min Cao
  • Patent number: 8487280
    Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Gary E. Dickerson, Julian G. Blake
  • Patent number: 8409975
    Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 2, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Liujiang Yu
  • Patent number: 8399340
    Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akihiko Ohi
  • Publication number: 20130029480
    Abstract: A method of making a three-dimensional structure in semiconductor material includes providing a substrate (20) is provided having at least a surface including semiconductor material. Selected areas of the surface of the substrate are exposed to a focussed ion beam whereby the ions are implanted in the semiconductor material in the selected areas. Several layers of a material selected from the group consisting of mono-crystalline, poly-crystalline or amorphous semiconductor material, are deposited on the substrate surface and between depositions focussed ion beam is used to expose the surface so as to define a three-dimensional structure. Material not part of the final structure (30) defined by the focussed ion beam is etched away so as to provide a three-dimensional structure on the substrate (20).
    Type: Application
    Filed: April 5, 2011
    Publication date: January 31, 2013
    Inventors: Frank Niklaus, Andreas Fischer
  • Patent number: 8361869
    Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: January 29, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huajie Zhou, Yi Song, Qiuxia Xu
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Patent number: 8304329
    Abstract: Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: November 6, 2012
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Jun Zeng, Mohamed N. Darwish
  • Patent number: 8298915
    Abstract: Method for forming a semi-conducting structure includes the formation of at least one part of a circuit or a component, in or on a superficial layer of a substrate, the substrate including a buried layer underneath the superficial layer, and an underlying layer serving as first support, a transfer of said substrate onto a handle substrate, and then an elimination of the first support, the formation of an electrically conducting or ground plane forming layer, on at least one part of said buried layer, the formation, on said electrically conducting or ground plane forming layer, of a bonding layer, a transfer of the structure obtained onto a second support and an elimination of said handle substrate.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 30, 2012
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Bernard Aspar
  • Patent number: 8298889
    Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
  • Patent number: 8263483
    Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Patent number: 8198180
    Abstract: In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer comprising dispersed gas pockets is deposited on the ion implanted region.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 12, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jose Ignacio Del Agua Borniquel, Tze Poon, Robert Schreutelkamp, Majeed Foad
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8173991
    Abstract: An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 8, 2012
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Stauss, Matthias Peter, Alexander Walter
  • Patent number: 8174074
    Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chung-Hsun Lin, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20120104347
    Abstract: A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method of forming a resistive random access memory device is also disclosed. The method comprises forming a plurality of memory cells wherein each cell of the plurality of memory cells is formed by forming a metal on a first electrode, forming a chalcogenide material on the metal by a gas cluster ion beam process, and forming a second electrode on the chalcogenide material. A method of forming another resistive random access memory device and a random access memory device including the chalcogenide material are also disclosed.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 3, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Timothy A. Quick
  • Publication number: 20110306192
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Application
    Filed: April 11, 2011
    Publication date: December 15, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong Seok EUN, Tae Kyun KIM, Kyong Bong ROUH, Eun Shil PARK
  • Patent number: 8067301
    Abstract: A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A transistor directly connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern. Since the ion-implantation interrupting pattern is located on an upper portion of the gate electrode pattern of the transistor in the vicinity of the photo-detective device, a threshold voltage of the gate electrode pattern of the transistor in the vicinity of the photo-detective device is adjusted to a desired value.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duk-Min Yi, Sung-Keun Won, Jun-Yeoul You
  • Patent number: 8034208
    Abstract: A method of transferring a layer of a first material onto a second substrate of a second material includes, a step of forming a first embrittlement plane in a first substrate in first material, by a first ion and/or atom implantation through a first face of said substrate, a step of forming a second embrittlement plane in said first substrate, by a first ion and/or atom implantation through a second face of said substrate, in order to reduce a curvature of this first substrate, a step of assembling the first and second substrates, and a step of separating a layer from the first substrate at the level of the first embrittlement plane, without separation at the level of the second embrittlement plane.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 11, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Jean-Claude Roussin
  • Patent number: 8012843
    Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: September 6, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
  • Patent number: 7943402
    Abstract: A method of characterizing an ion implantation process, the method including a first step of producing a PN junction degraded by the ion implantation of species, the species implantation being obtained by the ion implantation process to be characterized; a second step of measuring a parameter representative of an electrical conduction of the degraded PN junction and a dispersion of the parameter on a surface on which the degraded PN junction is produced, the parameter and the dispersion forming a reference parameter and a reference dispersion, the first and second steps being repeated in time so as to follow the evolution of the parameter representative of electrical conduction with relation to the reference parameter and the dispersion of the representative parameter with relation to the reference dispersion.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: May 17, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Frédéric Milesi, Frédéric Mazen
  • Patent number: 7939418
    Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: May 10, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Yong-sun Sohn, Min Yong Lee
  • Patent number: 7935616
    Abstract: Methods of fabricating semiconductor p-n junctions and semiconductor devices containing p-n junctions are disclosed in which the p-n junctions contain concentration profiles for the p-type and n-type dopants that are controllable and independent of a dopant diffusion profile. The p-n junction is disposed between a layer of semiconductor doped with a p-type dopant and a layer of semiconductor doped with an n-type dopant. The p-n junction is fabricated using a crystal growth process that allows dynamic control and variation of both p-type and n-type dopant concentrations during the crystal growth process.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: May 3, 2011
    Inventors: Robert H. Burgener, II, Roger L. Felix, Gary M. Renlund
  • Patent number: 7927988
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating process to form an insulating layer between the first and second layers while preventing loss of the second layer using the anti-oxidation layer.
    Type: Grant
    Filed: June 21, 2009
    Date of Patent: April 19, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In-Gyoo Kim, O-Kyun Kwon, Dong-Woo Suh, Gyung-Ock Kim
  • Patent number: 7927986
    Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
  • Patent number: 7924159
    Abstract: The present invention involves a system and method of remotely detecting the presence of a wafer comprising, a passive RFID circuit, wherein the RFID circuit is attached to an end of a transfer arm located inside a vacuum chamber of an ion implantation system, a reader located outside the vacuum chamber, and wherein the RFID tag provides an indication relating to whether or not a wafer is secured by the transfer arm.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: April 12, 2011
    Assignee: Axcelis Technologies Inc.
    Inventors: Kan Ota, Michael Chen, David K. Bernhardt
  • Patent number: 7858503
    Abstract: In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer is deposited on the ion implanted region. The substrate is annealed to volatize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process. An intermediate product comprises a substrate, a plurality of ion implantation regions on the substrate, and a porous capping layer covering the ion implantation regions.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: December 28, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Jose Ignacio Del Agua Borniquel, Tze Poon, Robert Schreutelkamp, Majeed Foad