Doping Of Semiconductor Patents (Class 438/508)
  • Patent number: 9150417
    Abstract: The present disclosure relates to a process for growth of graphene at a temperature above 1400° C. on a silicon carbide surface by sublimation of silicon from the surface. The process comprises heating under special conditions up to growth temperature which ensured that the surface undergoes the proper modification for allowing homogenous graphene in one or more monolayers.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: October 6, 2015
    Assignee: Graphensic AB
    Inventors: Rositsa Yakimova, Tihomir Iakimov, Mikael Syvajarvi
  • Patent number: 9023721
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Publication number: 20150087140
    Abstract: A film forming method according to an embodiment includes: (a) a step of supplying a first precursor gas of a semiconductor material into a processing vessel in which a processing target substrate is disposed, the first precursor gas being adsorbed onto the processing target substrate during the step; (b) a step of supplying a second precursor gas of a dopant material into the processing vessel, the second precursor gas being adsorbed onto the processing target substrate during the step; and (c) a step of generating the plasma of a reaction gas in the processing vessel, a plasma treatment being performed during the step so as to modify a layer adsorbed onto the processing target substrate.
    Type: Application
    Filed: April 22, 2013
    Publication date: March 26, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Nozawa, Hirokazu Ueda
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8932943
    Abstract: A method of manufacturing a nitride semiconductor light emitting device which includes forming an n-type semiconductor layer, forming an active layer on the n-type semiconductor layer, forming a superlattice layer by alternately stacking at least two nitride layers made of InxAlyGa(1-x-y)N (0?x?1, 0?y?1, and 0?x+y?1) having different energy bandgaps from each other and doped with a p-type dopant, and forming a p-type semiconductor layer on the superlattice layer. The forming of the superlattice layer is performed by adjusting a flow rate of a p-type dopant source gas to reduce the flow rate in a growth termination period of the superlattice layer by no greater than about half of the flow rate in a growth initiation period of the superlattice layer while being doped with the p-type dopant.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Cheon, Yu Ri Sohn
  • Patent number: 8921211
    Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 30, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Mario Giuseppe Saggio, Angelo Magri′
  • Publication number: 20140361408
    Abstract: A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Robert J. Falster, Vladimir V. Voronkov
  • Publication number: 20140299918
    Abstract: A semiconductor substrate and a fabrication method thereof, and a semiconductor apparatus using the same and a fabrication method thereof are provided. The semiconductor substrate includes a semiconductor wafer, a silicon germanium (SiGe)-based impurity doping region formed on the semiconductor wafer, and a protection layer formed on the SiGe-based impurity doping region.
    Type: Application
    Filed: July 25, 2013
    Publication date: October 9, 2014
    Applicant: SK hynix Inc.
    Inventors: Jong Chul LEE, Min Yong LEE, Jin Ku LEE
  • Publication number: 20140299872
    Abstract: Substrates for an electronic circuit and device manufacturing methods are disclosed. According to an embodiment, the substrate comprises: a silicon or germanium wafer impregnated with impurities that form one or more deep energy levels within the band gap of the material forming the wafer, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and a device layer formed on a surface of said wafer, said device layer comprising electronically functional components formed in a layer of Periodic Table Group III-V or II-VI material. The wafer may be formed from Cz silicon or Cz germanium, for example.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 9, 2014
    Applicant: Isis Innovation Limited
    Inventors: Peter Wilshaw, Kanad Mallik, Doug Jordan, Cornelis De Groot
  • Patent number: 8842710
    Abstract: There are provided a process for producing a semiconductor device and a semiconductor device which allow conductivity distribution to be formed without making refractive index distributed even in a material system of a semiconductor difficult to be subjected to ion implantation. The process for producing a semiconductor device includes the steps of forming a semiconductor layer containing a dopant; forming a concave and convex structure on the semiconductor layer by partially removing the semiconductor layer; and forming a conductivity distribution reflecting the concave and convex structure in the semiconductor layer by performing heat treatment on the semiconductor layer in which the concave and convex structure has been formed at a temperature at which a material forming the semiconductor layer causes mass transport and filling up a hole of a concave portion of the concave and convex structure with the material forming the semiconductor layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: September 23, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nagatomo, Takeshi Kawashima, Katsuyuki Hoshino, Shoichi Kawashima
  • Publication number: 20140264363
    Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.
    Type: Application
    Filed: July 22, 2013
    Publication date: September 18, 2014
    Inventors: Mingwei Zhu, Nag B. Patibandla, Rongjun Wang, Daniel Lee Diehl, Vivek Agrawal, Anantha Subramani
  • Patent number: 8815621
    Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaki Ueno, Yusuke Yoshizumi, Takao Nakamura
  • Patent number: 8796097
    Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: August 5, 2014
    Assignee: University of South Carolina
    Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
  • Publication number: 20140213046
    Abstract: A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method.
    Type: Application
    Filed: March 28, 2014
    Publication date: July 31, 2014
    Applicant: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8790980
    Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: July 29, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jin Ping Liu, Jundson Robert Holt
  • Publication number: 20140141603
    Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ferruccio FRISINA, Mario Giuseppe SAGGIO, Angelo MAGRI'
  • Patent number: 8685845
    Abstract: A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Dube, Ashima B. Chakravarti, Jinghong H. Li, Rainer Loesing, Dominic J. Schepis
  • Patent number: 8679957
    Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Chiharu Ota, Takashi Shinohe
  • Publication number: 20140054680
    Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 27, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Takao NAKAMURA, Hiroshi AMANO
  • Publication number: 20140054550
    Abstract: The present disclosure provides an n-doping method of graphene, including supplying a reaction gas containing a carbon source and heat to a substrate and reacting to grow graphene on the substrate; and n-doping the graphene by a doping solution containing an n-type dopant or a vapor containing an n-type dopant, an n-doped graphene produced by the method, and a device including the n-doped graphene.
    Type: Application
    Filed: September 3, 2013
    Publication date: February 27, 2014
    Applicant: GRAPHENE SQUARE INC.
    Inventors: Byung Hee HONG, Eun Seon KIM
  • Publication number: 20140034965
    Abstract: According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region.
    Type: Application
    Filed: March 8, 2013
    Publication date: February 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chiharu OTA, Johji Nishio, Kazuto Takao, Takashi Shinohe
  • Patent number: 8637955
    Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 28, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lingquan Wang, Teymur Bakhishev, Dalong Zhao, Pushkar Ranade, Sameer Pradhan, Thomas Hoffmann, Lucian Shifren, Lance Scudder
  • Patent number: 8597978
    Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
  • Patent number: 8575010
    Abstract: The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: November 5, 2013
    Assignee: Soitec
    Inventors: Alexis Drouin, Bernard Aspar, Christophe Desrumaux, Olivier Ledoux, Christophe Figuet
  • Patent number: 8557671
    Abstract: A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: October 15, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Publication number: 20130267082
    Abstract: Disclosed are chalcogenide-containing precursors for use in the manufacture of semiconductor, photovoltaic, LCD-TFT1 or fiat panel type devices. Also disclosed a methods of synthesizing the chalcogenide-containing precursors and vapor deposition methods, preferably thermal ALD, using the chaicogenide-containing precursors to form chaicogenide-containing films.
    Type: Application
    Filed: December 29, 2010
    Publication date: October 10, 2013
    Applicant: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Julien Gatineau, Mao Minoura, Hana Ishii
  • Patent number: 8513644
    Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 20, 2013
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Asaf Albo, Gad Bahir, Dan Fekete
  • Patent number: 8502191
    Abstract: A semiconductor device includes: a silicon layer (12); an intermediate silicide layer (28) that is provided on the silicon layer (12), has openings, and includes barium silicide; and an upper silicide layer (14) that covers the intermediate silicide layer (28), is positioned to be in contact with the silicon layer (12) through the openings, has a higher dopant concentration than the dopant concentration of the intermediate silicide layer (28), and includes barium silicide.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: August 6, 2013
    Assignees: University of Tsukuba, Tohoku University
    Inventors: Takashi Suemasu, Noritaka Usami
  • Patent number: 8501571
    Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8470689
    Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3 or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 25, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Desplobain, Frederic-Xavier Gaillard, Yves Morand, Fabrice Nemouchi
  • Patent number: 8450131
    Abstract: An array of sensor devices, each sensor including a set of semiconducting nanotraces having a width less than about 100 nm is provided. Method for fabricating the arrays is disclosed, providing a top-down approach for large arrays with multiple copies of the detection device in a single processing step. Nanodimensional sensing elements with precise dimensions and spacing to avoid the influence of electrodes are provided. The arrays may be used for multiplex detection of chemical and biomolecular species. The regular arrays may be combined with parallel synthesis of anchor probe libraries to provide a multiplex diagnostic device. Applications for gas phase sensing, chemical sensing and solution phase biomolecular sensing are disclosed.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: May 28, 2013
    Assignee: Nanohmics, Inc.
    Inventors: Steve M. Savoy, Jeremy J. John, Daniel R. Mitchell, Michael K. McAleer
  • Publication number: 20130052810
    Abstract: In one embodiment, a method of producing a porous semiconductor film on a workpiece includes generating semiconductor precursor ions that comprise one or more of: germanium precursor ions and silicon precursor ions in a plasma of a plasma chamber, in which the semiconductor precursor ions are operative to form a porous film on the workpiece. The method further includes directing the semiconductor precursor ions to the workpiece over a range of angles.
    Type: Application
    Filed: August 28, 2012
    Publication date: February 28, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Blake Darby, Ludovic GODET, Xianfeng LU
  • Publication number: 20130037856
    Abstract: This invention relates to a semiconductor device and a manufacturing method therefor for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A SiGe seed layer is formed on sidewalls of the recess, and a first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom. A second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer, and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.
    Type: Application
    Filed: December 7, 2011
    Publication date: February 14, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yonggen He, Huojin Tu, Jing Lin
  • Publication number: 20130029480
    Abstract: A method of making a three-dimensional structure in semiconductor material includes providing a substrate (20) is provided having at least a surface including semiconductor material. Selected areas of the surface of the substrate are exposed to a focussed ion beam whereby the ions are implanted in the semiconductor material in the selected areas. Several layers of a material selected from the group consisting of mono-crystalline, poly-crystalline or amorphous semiconductor material, are deposited on the substrate surface and between depositions focussed ion beam is used to expose the surface so as to define a three-dimensional structure. Material not part of the final structure (30) defined by the focussed ion beam is etched away so as to provide a three-dimensional structure on the substrate (20).
    Type: Application
    Filed: April 5, 2011
    Publication date: January 31, 2013
    Inventors: Frank Niklaus, Andreas Fischer
  • Patent number: 8334156
    Abstract: A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, upper and lower regions are divided along a thickness direction, the nitride single crystal substrate having a thickness of at least 100 ?m. Here, the upper region has a doping concentration that is five times or greater than that of the lower region. Preferably, a top surface of the substrate in the upper region has Ga polarity. Also, according to a specific embodiment of the invention, the lower region is intentionally un-doped and the upper region is n-doped. Preferably, each of the upper and lower regions has a doping concentration substantially identical in a thickness direction.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol Kyu Kim, Yung Ho Ryu, Soo Min Lee, Jong In Yang, Tae Hyung Kim
  • Patent number: 8329541
    Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peide Ye, Zhiyuan Cheng, Yi Xuan, Yanqing Wu, Bunmi Adekore, James Fiorenza
  • Patent number: 8318522
    Abstract: Surface passivation techniques for chamber-split processing are described. A method includes forming a first Group III-V material layer above a substrate, the first Group III-V material layer having a top surface. A passivation layer is deposited on the top surface of the Group III-V material layer. The passivation layer is removed. Subsequently, a second Group III-V material layer is formed above the first Group III-V material layer.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: November 27, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Jie Su
  • Patent number: 8293553
    Abstract: In a method for producing at least at least one area (8) with reduced electrical conductivity within an electrically conductive III-V semiconductor layer (3), a ZnO layer (1) is applied to the area (8) of the semiconductor layer (3) and subsequently annealed at a temperature preferably between 300° C. and 500° C. The ZnO layer (1) is preferably deposited on the III-V semiconductor layer (3) at a temperature of less than 150° C., preferably at a temperature greater than or equal to 25° C. and less than or equal to 120° C. The area (8) with reduced electrical conductivity is preferably located in a radiation emitting optoelectronic device between the active zone (4) and a connecting contact (7) in order to reduce current injection into the areas of the active zone (4) located opposite to the connecting contact (7).
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 23, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Illek, Wilhelm Stein, Robert Walter, Ralph Wirth
  • Patent number: 8293628
    Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 23, 2012
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Asaf Albo, Gad Bahir, Dan Fekete
  • Publication number: 20120244646
    Abstract: According to embodiments, there is provided a manufacturing method of a semiconductor device includes forming a semiconductor thin film on a substrate; processing the thin film to a predetermined shape; executing an ion implantation process on the thin film processed to the predetermined shape; executing an anneal treatment on the thin film on which the ion implantation process has been executed to create a resistor element; and adjusting both or any one of a process condition of the ion implantation process and a treatment condition of the anneal treatment based on at least any one of a film forming condition and a film formation result of the forming and a film process result of the processing.
    Type: Application
    Filed: January 18, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takashi KYUHO
  • Patent number: 8253220
    Abstract: A nitride semiconductor device includes a first nitride semiconductor layer formed on a substrate, a defect induced layer formed on the first nitride semiconductor layer, and a second nitride semiconductor layer formed on the defect induced layer, contacting the defect induced layer, and having an opening through which the defect induced layer is exposed. The defect induced layer has a higher crystal defect density than those of the first and second nitride semiconductor layers.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Ryo Kajitani, Satoshi Tamura, Hideki Kasugai
  • Publication number: 20120193610
    Abstract: The present invention provides a graphene/oxide semiconductor Schottky junction device, a graphene/oxide semiconductor p-n heterojunction device, and fabrication methods thereof. The Schottky junction device comprises graphene vapor-deposited directly on thin films, nanowires, nanotubes, nanobelts or nanoparticles. The p-n heterojunction device is manufactured by doping the graphene of the Schottky junction device so as to convert the graphene into a semiconductor.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 2, 2012
    Applicant: The Industry & Academic Cooperation in Chungnam National University (IAC)
    Inventor: Eui-Tae Kim
  • Patent number: 8227328
    Abstract: This disclosure relates to the synthesis of Er doped GaN epilayers by in-situ doping by metal-organic chemical vapor deposition (MOCVD). In an embodiment, both above and below bandgap excitation results in a sharp PL emission peak at 1.54 ?m. Contrary with other growth methods, MOCVD grown Er-doped GaN epilayers exhibit virtually no visible emission lines, an present a small thermal quenching effect. The Er incorporation has very little effect on the electrical conductivity of the GaN epilayers and Er doped layers retain similar electrical properties as those of undoped GaN.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: July 24, 2012
    Inventors: Hongxing Jiang, Jingyu Lin, Cris Ugolini, John Zavada
  • Patent number: 8216921
    Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: July 10, 2012
    Assignee: Covalent Materials Corporation
    Inventor: Tatsuo Fujii
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Publication number: 20120049150
    Abstract: A semiconductor device includes: a silicon layer (12); an intermediate silicide layer (28) that is provided on the silicon layer (12), has openings, and includes barium silicide; and an upper silicide layer (14) that covers the intermediate silicide layer (28), is positioned to be in contact with the silicon layer (12) through the openings, has a higher dopant concentration than the dopant concentration of the intermediate silicide layer (28), and includes barium silicide.
    Type: Application
    Filed: May 11, 2010
    Publication date: March 1, 2012
    Applicants: TOHOKU UNIVERSITY, UNIVERSITY OF TSUKUBA
    Inventors: Takashi Suemasu, Noritaka Usami
  • Publication number: 20120043556
    Abstract: A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Dube, Ashima B. Chakravarti, Jinghong H. Li, Rainer Loesing, Dominic J. Schepis
  • Patent number: 8102026
    Abstract: To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value ?? obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×1017 cm?3.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 24, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Eri, Takeshi Meguro
  • Patent number: 8088675
    Abstract: A method for obtaining a desired dopant profile of an emitter for a solar cell which includes depositing a first amorphous silicon layer having a first doping level over an upper surface of the crystalline silicon substrate, depositing a second amorphous silicon layer having a second doping level on the first amorphous silicon layer, and heating the crystalline silicon substrate and the first and second amorphous silicon layers to a temperature sufficient to cause solid phase epitaxial crystallization of the first and second amorphous silicon layers, such that the first and second amorphous silicon layers, after heating, have the same grain structure and crystal orientation as the underlying crystalline silicon substrate.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: January 3, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V. S. Rana, Robert Z. Bachrach
  • Publication number: 20110281424
    Abstract: A relaxed InGaN template is formed by growing a GaN or InGaN nucleation layer at low temperatures on a conventional base layer (e.g., sapphire). The nucleation layer is typically very rough and multi-crystalline. A single-crystal InGaN buffer layer is then grown at normal temperatures on the nucleation layer. Although not necessary, the buffer layer is typically undoped, and is usually grown at high pressures to encourage planarization and to improve surface smoothness. A subsequent n-doped cap layer can then be grown at low pressures to form the n-contact of a photonic or electronic device. In some cases, a wetting layer—typically low temperature AlN—is grown prior to the nucleation layer. Other templates, such as AlGaN on Si or SiC, are also produced using the method of the present invention.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 17, 2011
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Zhihong Yang, Andre Strittmatter, Mark R. Teepe